Andrew Richard Pleszkun - Publications

Affiliations: 
University of Wisconsin, Madison, Madison, WI 
 University of Colorado, Boulder, Boulder, CO, United States 

30 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2003 Aiken S, Grunwald D, Pleszkun AR, Willeke J. A performance analysis of the iSCSI protocol Digest of Papers - Ieee Symposium On Mass Storage Systems. 123-134. DOI: 10.1109/MASS.2003.1194849  1
2001 Zhang X, Su R, Pleszkun A. Analysis and design trade-offs for magnetic hard disk access time Proceedings of Spie - the International Society For Optical Engineering. 4534: 199-209. DOI: 10.1117/12.448019  1
1998 Grunwald D, Klauser A, Manne S, Pleszkun A. Confidence estimation for speculation control Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 122-131.  1
1998 Metz JL, Pleszkun AR, Johnson KM. CMOS smart photosensor array for optoelectronic hit/miss transform processing of cervical smears Conference Proceedings - Lasers and Electro-Optics Society Annual Meeting-Leos. 2: 67-68.  1
1997 Tyson G, Farrens M, Matthews J, Pleszkun AR. Managing data caches using selective cache line replacement International Journal of Parallel Programming. 25: 213-242. DOI: 10.1007/Bf02700036  1
1995 Tyson G, Farrens M, Matthews J, Pleszkun AR. Modified approach to data cache management Proceedings of the Annual International Symposium On Microarchitecture. 93-103.  1
1995 Carlson LE, Sullivan JF, Bedard AJ, Etter DM, Pleszkun AR. First year engineering projects: An interdisciplinary, hands-on introduction to engineering Asee Annual Conference Proceedings. 2: 2039-2043.  1
1994 Farrens M, Tyson G, Pleszkun AR. Study of single-chip processor/cache organizations for large numbers of transistors Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 338-347.  1
1994 Pleszkun AR. Techniques for compressing program address traces Professional Engineering. 7: 32-39.  1
1992 Tyson G, Farrens M, Pleszkun AR. MISC. A Multiple Instruction Stream Computer Proceedings of the 25th Annual International Symposium On Microarchitecture. 193-196.  1
1991 Farrens MK, Pleszkun AR. Implementation of the PIPE Processor Computer. 24: 65-70. DOI: 10.1109/2.67195  1
1991 Farrens MK, Pleszkun AR. Strategies for achieving improved processor throughput Conference Proceedings - Annual Symposium On Computer Architecture. 362-369.  1
1989 Farrens MK, Pleszkun AR. Improving performance of small on-chip instruction caches Conference Proceedings - Annual Symposium On Computer Architecture. 234-241.  1
1988 Smith JE, Pleszkun AR. Implementing Precise Interrupts in Pipelined Processors Ieee Transactions On Computers. 37: 562-573. DOI: 10.1109/12.4607  1
1988 Pleszkun AR, Sohi GS. PERFORMANCE POTENTIAL OF MULTIPLE FUNCTIONAL UNIT PROCESSORS . 37-44.  1
1988 Pleszkun AR, Sohi GS. Multiple instruction issue and single-chip processors Micro: Annual Microprogramming Workshop. 64-66.  1
1987 Pleszkun AR, Thazhuthaveetil MJ. The Architecture of Lisp Machines Computer. 20: 35-44. DOI: 10.1109/MC.1987.1663507  1
1987 Thazhuthaveetil MJ, Pleszkun AR. On the structural locality of reference in LISP list access streams Information Processing Letters. 26: 105-110. DOI: 10.1016/0020-0190(87)90046-9  1
1987 Craig GL, Goodman JR, Katz RH, Pleszkun AR, Ramachandran K, Sayah J, Smith JE. PIPE: A HIGH PERFORMANCE VLSI PROCESSOR IMPLEMENTATION Journal of Vlsi and Computer Systems. 2: 1-22.  1
1987 Pleszkun AR, Goodman JR, Hsu WC, Joersz RT, Bier G, Woest P, Schechter PB. WISQ: A RESTARTABLE ARCHITECTURE USING QUEUES Conference Proceedings - Annual Symposium On Computer Architecture. 290-299.  1
1986 Pleszkun AR, Thazhuthaveetil MJ. ARCHITECTURE FOR EFFICIENT LISP LIST ACCESS Conference Proceedings - Annual Symposium On Computer Architecture. 191-198.  1
1986 Pleszkun AR, Farrens MK. INSTRUCTION CACHE DESIGN FOR USE WITH A DELAYED BRANCH . 73-88.  1
1986 Pleszkun AR, Sohi GS, Kahhaleh BZ, Davidson ES. FEATURES OF THE STRUCTURED MEMORY ACCESS (SMA) ARCHITECTURE Proceedings - Ieee Computer Society International Conference. 259-263.  1
1985 Hsieh JT, Pleszkun AR, Vernon MK. PERFORMANCE EVALUATION OF A PIPELINED VLSI ARCHITECTURE USING THE GRAPH MODEL OF BEHAVIOR (GMB) . 192-205.  1
1985 Smith JE, Pleszkun AR. IMPLEMENTATION OF PRECISE INTERRUPTS IN PIPELINED PROCESSORS Conference Proceedings - Annual Symposium On Computer Architecture. 36-44.  1
1985 Bier GE, Pleszkun AR. ALGORITHM FOR DESIGN RULE CHECKING ON A MULTIPROCESSOR Proceedings - Design Automation Conference. 299-304.  1
1985 Goodman JR, Hsieh Jt, Liou K, Pleszkun AR, Schechter PB, Young HC. PIPE: A VLSI DECOUPLED ARCHITECTURE Conference Proceedings - Annual Symposium On Computer Architecture. 20-27.  1
1983 Pleszkun AR, Davidson ES. STRUCTURED MEMORY ACCESS ARCHITECTURE Proceedings of the International Conference On Parallel Processing. 461-471.  1
1983 Smith JE, Pleszkun AR, Katz RH, Goodman JR. PIPE: A HIGH PERFORMANCE VLSI ARCHITECTURE . 131-138.  1
1981 Pleszkun AR, Rau BR, Davidson ES. ADDRESS PREDICTION MECHANISM FOR REDUCING PROCESSOR-MEMORY ADDRESS BANDWIDTH . 141-148.  1
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