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Edward Steinberg Davidson - Publications

Affiliations: 
University of Michigan, Ann Arbor, Ann Arbor, MI 
 University of Illinois, Urbana-Champaign, Urbana-Champaign, IL 
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56 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2014 Eichenberger AE, Davidson ES, Abraham SG. Optimum modulo schedules for minimum register requirements Proceedings of the International Conference On Supercomputing. 227-236. DOI: 10.1145/2591635.2667171  0.377
2004 Srinivasan V, Davidson ES, Tyson GS. A Prefetch Taxonomy Ieee Transactions On Computers. 53: 126-140. DOI: 10.1109/Tc.2004.1261824  0.387
2004 Smelyanskiy M, Mahlke S, Davidson ES. Probabilistic predicate-aware modulo scheduling International Symposium On Code Generation and Optimization, Cgo. 151-162. DOI: 10.1109/CGO.2004.1281671  0.691
2003 Annavaram M, Patel JM, Davidson ES. Call graph prefetching for database applications Acm Transactions On Computer Systems. 21: 412-444. DOI: 10.1145/945506.945509  0.709
2003 Smelyanskiy M, Mahlke SA, Davidson ES, Lee HHS. Predicate-aware scheduling: A technique for reducing resource constraints International Symposium On Code Generation and Optimization, Cgo 2003. 169-178. DOI: 10.1109/CGO.2003.1191543  0.693
2002 Vlaovic S, Davidson ES. Boosting trace cache performance with NonHead Miss Speculation Proceedings of the International Conference On Supercomputing. 179-188.  0.767
2002 Vlaovic S, Davidson ES. TAXI: Trace analysis for X86 interpretation Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 508-514.  0.726
2001 Tyson GS, Smelyanskiy M, Davidson ES. Evaluating the use of register queues in software pipelined loops Ieee Transactions On Computers. 50: 769-783. DOI: 10.1109/12.946998  0.716
2001 Srinivasan V, Davidson ES, Tyson GS, Charney MJ, Puzak TR. Branch history guided instruction prefetching Ieee High-Performance Computer Architecture Symposium Proceedings. 291-300.  0.346
2001 Tam ES, Vlaovic SA, Tyson GS, Davidson ES. Allocation by conflict: A simple, effective multilateral cache management scheme Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 133-140.  0.75
2001 Annavaram M, Patel JM, Davidson ES. Data prefetching by dependence graph precomputation Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 52-61.  0.662
2000 Annavaram M, Tyson GS, Davidson ES. Instruction overhead and data locality effects in superscalar processors 2000 Ieee International Symposium On Performance Analysis of Systems and Software, Ispass 2000. 95-100. DOI: 10.1109/ISPASS.2000.842287  0.668
2000 Vlaovic S, Davidson ES, Tyson GS. Improving BTB performance in the presence of DLLs Proceedings of the Annual International Symposium On Microarchitecture. 77-86.  0.761
2000 Smelyanskiy M, Tyson GS, Davidson ES. Register queues: a new hardware/software approach to efficient software pipelining Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 3-12.  0.698
1999 Tam ES, Rivers JA, Srinivasan V, Tyson GS, Davidson ES. Active management of data caches by exploiting reuse information Ieee Transactions On Computers. 48: 1244-1259. DOI: 10.1109/12.811113  0.61
1998 Abandah GA, Davidson ES. Configuration independent analysis for characterizing shared-memory applications Proceedings of the International Parallel Processing Symposium, Ipps. 485-491. DOI: 10.1109/IPPS.1998.669960  0.349
1998 Abandah GA, Davidson ES. Characterizing distributed shared memory performance: A case study of the convex SPP1000 Ieee Transactions On Parallel and Distributed Systems. 9: 206-216. DOI: 10.1109/71.663946  0.468
1998 Rivers JA, Tam ES, Tyson GS, Davidson ES, Farrens M. Utilizing reuse information in data cache management Proceedings of the International Conference On Supercomputing. 449-456.  0.701
1998 Abandah GA, Davidson ES. Effects of architectural and technological advances on the HP/Convex Exemplar's memory and communication performance Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 318-329.  0.363
1998 Tam ES, Rivers JA, Srinivasan V, Tyson GS, Davidson ES. Evaluating the performance of active cache management schemes Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 368-375.  0.307
1998 Tam ES, Rivers JA, Tyson GS, Davidson ES. mlcache: A flexible multi-lateral cache simulator Ieee International Workshop On Modeling, Analysis, and Simulation of Computer and Telecommunication Systems - Proceedings. 19-26.  0.377
1998 Smelyanskiy M, Davidson ES, Volakis JL. Performance optimization of an integral equation code for jet engine scattering on CRAY-C90 Applied Computational Electromagnetics Society Journal. 13: 116-130.  0.692
1997 Rivers JA, Tyson GS, Davidson ES, Austin TM. On high-bandwidth data cache design for multi-issue processors Proceedings of the Annual International Symposium On Microarchitecture. 46-56.  0.365
1997 Rivers JA, Tam ES, Davidson ES. On effective data supply for multi-issue processors Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 519-528.  0.34
1996 Rivers JA, Davidson ES. Performance issues in integrating temporality-based caching with prefetching Performance Evaluation. 27: 189-207. DOI: 10.1016/0166-5316(96)00037-5  0.441
1996 Eichenberger AE, Davidson ES, Abraham SG. Minimizing register requirements of a modulo schedule via optimum stage scheduling International Journal of Parallel Programming. 24: 103-132. DOI: 10.1007/Bf03356744  0.763
1996 Eichenberger AE, Davidson ES. A reduced multipipeline machine description that preserves scheduling constraints Sigplan Notices (Acm Special Interest Group On Programming Languages). 31: 12-21.  0.302
1995 Eichenberger AE, Davidson ES. Stage scheduling: a technique to reduce the register requirements of a modulo schedule Proceedings of the Annual International Symposium On Microarchitecture. 338-349.  0.323
1995 Eichenberger AE, Davidson ES. Register allocation for predicated code Proceedings of the Annual International Symposium On Microarchitecture. 180-191.  0.318
1994 Boyd EL, Azeem W, Lee HH, Shih TP, Hung SH, Davidson ES. A hierarchical approach to modeling and improving the performance of scientific applications on the KSR1 Proceedings of the International Conference On Parallel Processing. 3: III188-III192. DOI: 10.1109/ICPP.1994.30  0.379
1994 Eichenberger AE, Davidson ES, Abraham SG. Minimum register requirements for a modulo schedule Professional Engineering. 7: 75-84.  0.358
1993 Mangione-Smith WH, Shih TP, Abraham SG, Davidson ES. Approaching a Machine-Application Bound in Delivered Performance on Scientific Code Proceedings of the Ieee. 81: 1166-1178. DOI: 10.1109/5.236193  0.745
1993 Sakallah KA, Mudge TN, Burks TM, Davidson ES. Synchronization of Pipelines Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 1132-1146. DOI: 10.1109/43.238606  0.576
1993 Kuck D, Davidson E, Lawrie D, Sameh A, Zhu CQ, Veidenbaum A, Konicek J, Yew P, Gallivan K, Jalby W, Wijshoff H, Bramley R, Yang UM, Emrath P, Padua D, et al. Cedar system and an initial performance study Conference Proceedings - Annual Symposium On Computer Architecture. 213-223.  0.304
1991 Mangione-Smith W, Abraham SG, Davidson ES. A Performance Comparison of the IBM RS/6000 and the Astronautics ZS-1 Computer. 24: 39-46. DOI: 10.1109/2.67192  0.388
1991 Mangione-Smith W, Abraham SG, Davidson ES. Vector register design for polycyclic vector scheduling International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 26: 154-163.  0.305
1990 Mangione-Smith W, Abraham SG, Davidson ES. Effects of memory latency and fine-grain parallelism on Astronautics ZS-1 performance Proceedings of the Hawaii International Conference On System Science. 1: 288-296.  0.417
1988 Davis TA, Davidson ES. Pairwise Reduction for the Direct, Parallel Solution of Sparse, Unsymmetric Sets of Linear Equations Ieee Transactions On Computers. 37: 1648-1654. DOI: 10.1109/12.9742  0.339
1988 McNiven GD, Davidson ES. ANALYSIS OF MEMORY REFERENCING BEHAVIOR FOR DESIGN OF LOCAL MEMORIES . 56-63.  0.314
1986 Kuck DJ, Davidson ES, Lawrie DH, Sameh AH. Parallel supercomputing today and the cedar approach. Science (New York, N.Y.). 231: 967-74. PMID 17740294 DOI: 10.1126/Science.231.4741.967  0.471
1986 Pleszkun AR, Sohi GS, Kahhaleh BZ, Davidson ES. FEATURES OF THE STRUCTURED MEMORY ACCESS (SMA) ARCHITECTURE Proceedings - Ieee Computer Society International Conference. 259-263.  0.743
1986 Hsu PYT, Davidson ES. HIGHLY CONCURRENT SCALAR PROCESSING Conference Proceedings - Annual Symposium On Computer Architecture. 386-395.  0.349
1985 Sohi GS, Davidson ES, Patel JH. EFFICIENT LISP-EXECUTION ARCHITECTURE WITH A NEW REPRESENTATION FOR LIST STRUCTURES Conference Proceedings - Annual Symposium On Computer Architecture. 91-98.  0.326
1984 Sohi GS, Davidson ES. PERFORMANCE OF THE STRUCTURED MEMORY ACCESS (SMA) ARCHITECTURE Proceedings of the International Conference On Parallel Processing. 506-513.  0.329
1983 Abraham JA, Davidson ES, Patel JH. Memory system design for tolerating single event upsets Ieee Transactions On Nuclear Science. 30: 4339-4344. DOI: 10.1109/Tns.1983.4333134  0.616
1983 Yeh PCC, Patel JH, Davidson ES. Shared Cache for Multiple-Stream Computer Systems Ieee Transactions On Computers. 38-47. DOI: 10.1109/TC.1983.1676122  0.613
1983 Pleszkun AR, Davidson ES. STRUCTURED MEMORY ACCESS ARCHITECTURE Proceedings of the International Conference On Parallel Processing. 461-471.  0.707
1982 Yen DWL, Patel JH, Davidson ES. Memory interference in synchronous multiprocessor systems Ieee Transactions On Computers. 1116-1121. DOI: 10.1109/TC.1982.1675928  0.577
1981 Budzinski RL, Davidson ES. A Comparison of Dynamic and Static Virtual Memory Allocation Algorithms Ieee Transactions On Software Engineering. 122-131. DOI: 10.1109/Tse.1981.234515  0.36
1981 Budzinski RL, Davidson ES, Stone HS, Mayeda W. DMIN: An Algorithm for Computing the Optimal Dynamic Allocation in a Virtual Memory Computer Ieee Transactions On Software Engineering. 113-121. DOI: 10.1109/Tse.1981.234514  0.368
1981 Pleszkun AR, Rau BR, Davidson ES. ADDRESS PREDICTION MECHANISM FOR REDUCING PROCESSOR-MEMORY ADDRESS BANDWIDTH . 141-148.  0.716
1980 Kumar B, Davidson ES. COMPUTER SYSTEM DESIGN USING A HIERARCHICAL APPROACH TO PERFORMANCE EVALUATION Communications of the Acm. 23: 511-521. DOI: 10.1145/359007.359012  0.33
1978 Kumar B, Davidson ES. PERFORMANCE EVALUATION OF HIGHLY CONCURRENT COMPUTERS BY DETERMINISTIC SIMULATION Communications of the Acm. 21: 904-913. DOI: 10.1145/359642.359646  0.449
1977 Briggs FA, Davidson ES. Organization of Semiconductor Memories for Parallel-Pipelined Processors Ieee Transactions On Computers. 162-169. DOI: 10.1109/Tc.1977.5009295  0.411
1977 Hammerstrom DW, Davidson ES. INFORMATION CONTENT OF CPU MEMORY REFERENCING BEHAVIOR . 184-192.  0.347
1974 Shar LE, Davidson ES. A multiminiprocessor system implemented through pipelining Computer. 7: 42-51. DOI: 10.1109/Mc.1974.6323457  0.428
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