Edward Steinberg Davidson - Publications

Affiliations: 
University of Michigan, Ann Arbor, Ann Arbor, MI 
 University of Illinois, Urbana-Champaign, Urbana-Champaign, IL 

95 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2014 Eichenberger AE, Davidson ES, Abraham SG. Optimum modulo schedules for minimum register requirements Proceedings of the International Conference On Supercomputing. 227-236. DOI: 10.1145/2591635.2667171  1
2014 Eichenberger AE, Davidson ES, Abraham SG. Author retrospective for optimum modulo schedules for minimum register requirements Proceedings of the International Conference On Supercomputing. 35-36. DOI: 10.1145/2591635.2591653  1
2008 Davidson ES. Perceived continuing education needs and job relevance of health education competencies among health education and promotion practitioners in college health settings. Journal of American College Health : J of Ach. 57: 197-209. PMID 18809537 DOI: 10.3200/JACH.57.2.197-210  0.01
2008 Victor MN, Silzars AK, Davidson ES. A freespace crossbar for multi-core processors Proceedings of the International Conference On Supercomputing. 56-62. DOI: 10.1145/1375527.1375539  1
2004 Srinivasan V, Davidson ES, Tyson GS. A Prefetch Taxonomy Ieee Transactions On Computers. 53: 126-140. DOI: 10.1109/Tc.2004.1261824  1
2004 Smelyanskiy M, Mahlke S, Davidson ES. Probabilistic predicate-aware modulo scheduling International Symposium On Code Generation and Optimization, Cgo. 151-162. DOI: 10.1109/CGO.2004.1281671  1
2003 Annavaram M, Patel JM, Davidson ES. Call graph prefetching for database applications Acm Transactions On Computer Systems. 21: 412-444. DOI: 10.1145/945506.945509  1
2003 Smelyanskiy M, Mahlke SA, Davidson ES, Lee HHS. Predicate-aware scheduling: A technique for reducing resource constraints International Symposium On Code Generation and Optimization, Cgo 2003. 169-178. DOI: 10.1109/CGO.2003.1191543  1
2002 Vlaovic S, Davidson ES. Boosting trace cache performance with NonHead Miss Speculation Proceedings of the International Conference On Supercomputing. 179-188.  1
2002 Vlaovic S, Davidson ES. TAXI: Trace analysis for X86 interpretation Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 508-514.  1
2001 Tyson GS, Smelyanskiy M, Davidson ES. Evaluating the use of register queues in software pipelined loops Ieee Transactions On Computers. 50: 769-783. DOI: 10.1109/12.946998  1
2001 Sarris CD, Tomko K, Czarnul P, Hung SH, Robertson RL, Chun D, Davidson ES, Katchi LPB. Multiresolution time domain modeling for large scale wireless communication problems Ieee Antennas and Propagation Society, Ap-S International Symposium (Digest). 3: 557-560.  1
2001 Srinivasan V, Davidson ES, Tyson GS, Charney MJ, Puzak TR. Branch history guided instruction prefetching Ieee High-Performance Computer Architecture Symposium Proceedings. 291-300.  1
2001 Tam ES, Vlaovic SA, Tyson GS, Davidson ES. Allocation by conflict: A simple, effective multilateral cache management scheme Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 133-140.  1
2001 Annavaram M, Patel JM, Davidson ES. Data prefetching by dependence graph precomputation Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 52-61.  1
2000 Annavaram M, Tyson GS, Davidson ES. Instruction overhead and data locality effects in superscalar processors 2000 Ieee International Symposium On Performance Analysis of Systems and Software, Ispass 2000. 95-100. DOI: 10.1109/ISPASS.2000.842287  1
2000 Smelyanskiy M, Tyson GS, Davidson ES. Register queues: a new hardware/software approach to efficient software pipelining Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 3-12.  1
2000 Vlaovic S, Davidson ES, Tyson GS. Improving BTB performance in the presence of DLLs Proceedings of the Annual International Symposium On Microarchitecture. 77-86.  1
1999 Tam ES, Rivers JA, Srinivasan V, Tyson GS, Davidson ES. Active management of data caches by exploiting reuse information Ieee Transactions On Computers. 48: 1244-1259. DOI: 10.1109/12.811113  1
1999 Meleis WM, Davidson ES. Dual-issue scheduling with spills for binary trees Proceedings of the Annual Acm-Siam Symposium On Discrete Algorithms. 678-686.  1
1998 Abandah GA, Davidson ES. Configuration independent analysis for characterizing shared-memory applications Proceedings of the International Parallel Processing Symposium, Ipps. 485-491. DOI: 10.1109/IPPS.1998.669960  1
1998 Abandah GA, Davidson ES. Characterizing distributed shared memory performance: A case study of the convex SPP1000 Ieee Transactions On Parallel and Distributed Systems. 9: 206-216. DOI: 10.1109/71.663946  1
1998 Tam ES, Rivers JA, Tyson GS, Davidson ES. mlcache: A flexible multi-lateral cache simulator Ieee International Workshop On Modeling, Analysis, and Simulation of Computer and Telecommunication Systems - Proceedings. 19-26.  1
1998 Rivers JA, Tam ES, Tyson GS, Davidson ES, Farrens M. Utilizing reuse information in data cache management Proceedings of the International Conference On Supercomputing. 449-456.  1
1998 Abandah GA, Davidson ES. Effects of architectural and technological advances on the HP/Convex Exemplar's memory and communication performance Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 318-329.  1
1998 Tam ES, Rivers JA, Srinivasan V, Tyson GS, Davidson ES. Evaluating the performance of active cache management schemes Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 368-375.  1
1998 Smelyanskiy M, Davidson ES, Volakis JL. Performance optimization of an integral equation code for jet engine scattering on CRAY-C90 Applied Computational Electromagnetics Society Journal. 13: 116-130.  1
1997 Rivers JA, Tam ES, Davidson ES. On effective data supply for multi-issue processors Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 519-528.  1
1997 Rivers JA, Tyson GS, Davidson ES, Austin TM. On high-bandwidth data cache design for multi-issue processors Proceedings of the Annual International Symposium On Microarchitecture. 46-56.  1
1997 Eichenberger AE, Davidson ES. Efficient Formulation for Optimal Modulo Schedulers Sigplan Notices (Acm Special Interest Group On Programming Languages). 32: 194-205.  1
1996 Rivers JA, Davidson ES. Performance issues in integrating temporality-based caching with prefetching Performance Evaluation. 27: 189-207. DOI: 10.1016/0166-5316(96)00037-5  1
1996 Eichenberger AE, Davidson ES, Abraham SG. Minimizing register requirements of a modulo schedule via optimum stage scheduling International Journal of Parallel Programming. 24: 103-132. DOI: 10.1007/Bf03356744  1
1996 Tomko KA, Davidson ES. Profile driven weighted decomposition Proceedings of the International Conference On Supercomputing. 165-172.  1
1996 Abandah GA, Davidson ES. Modeling the communication performance of the IBM SP2 Ieee Symposium On Parallel and Distributed Processing - Proceedings. 249-257.  1
1996 Eichenberger AE, Davidson ES. A reduced multipipeline machine description that preserves scheduling constraints Sigplan Notices (Acm Special Interest Group On Programming Languages). 31: 12-21.  1
1996 Eichenberger AE, Davidson ES. Reduced multipipeline machine description that preserves scheduling constraints Proceedings of the Acm Sigplan Conference On Programming Language Design and Implementation (Pldi). 12-22.  1
1995 Chang CH, Davidson ES, Sakallah KA. Maximum Rate Single-Phase Clocking of a Closed Pipeline including Wave Pipelining, Stoppability, and Startability Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 1526-1545. DOI: 10.1109/43.476583  1
1995 Eichenberger AE, Davidson ES. Stage scheduling: a technique to reduce the register requirements of a modulo schedule Proceedings of the Annual International Symposium On Microarchitecture. 338-349.  1
1995 Eichenberger AE, Davidson ES. Register allocation for predicated code Proceedings of the Annual International Symposium On Microarchitecture. 180-191.  1
1995 Wellmann JD, Davidson ES. Resource conflict methodology for early-stage design space exploration of superscalar RISC processors Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 110-115.  1
1994 Boyd EL, Azeem W, Lee HH, Shih TP, Hung SH, Davidson ES. A hierarchical approach to modeling and improving the performance of scientific applications on the KSR1 Proceedings of the International Conference On Parallel Processing. 3: III188-III192. DOI: 10.1109/ICPP.1994.30  1
1994 Shih TP, Davidson ES. Grouping array layouts to reduce communication and improve locality of parallel programs Proceedings of the Internatoinal Conference On Parallel and Distributed Systems - Icpads. 558-566.  1
1994 Eichenberger AE, Davidson ES, Abraham SG. Minimum register requirements for a modulo schedule Professional Engineering. 7: 75-84.  1
1993 Mangione-Smith WH, Shih TP, Abraham SG, Davidson ES. Approaching a Machine-Application Bound in Delivered Performance on Scientific Code Proceedings of the Ieee. 81: 1166-1178. DOI: 10.1109/5.236193  1
1993 Sakallah KA, Mudge TN, Burks TM, Davidson ES. Synchronization of Pipelines Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 1132-1146. DOI: 10.1109/43.238606  1
1993 Kuck D, Davidson E, Lawrie D, Sameh A, Zhu CQ, Veidenbaum A, Konicek J, Yew P, Gallivan K, Jalby W, Wijshoff H, Bramley R, Yang UM, Emrath P, Padua D, et al. Cedar system and an initial performance study Conference Proceedings - Annual Symposium On Computer Architecture. 213-223.  1
1993 Boyd EL, Davidson ES. Hierarchical performance modeling with MACS. A case study of the convex C-240 Conference Proceedings - Annual Symposium On Computer Architecture. 203-212.  1
1992 Chang CH, Davidson ES, Sakallah KA. Using constraint geometry to determine maximum rate pipeline clocking Ieee/Acm International Conference On Computer-Aided Design. 142-148.  1
1991 Mangione-Smith W, Abraham SG, Davidson ES. A Performance Comparison of the IBM RS/6000 and the Astronautics ZS-1 Computer. 24: 39-46. DOI: 10.1109/2.67192  1
1991 Sakallah KA, Mudge TN, Burks TM, Davidson ES. Optimal clocking of circular pipelines Ieee International Conference On Computer Design - Vlsi in Computers and Processors. 642-646.  1
1991 Chaar JK, Volz RA, Davidson ES. An integrated approach to developing manufacturing control software Proceedings - Ieee International Conference On Robotics and Automation. 3: 1979-1984.  1
1991 Mangione-Smith W, Abraham SG, Davidson ES. Vector register design for polycyclic vector scheduling International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 26: 154-163.  1
1990 Mangione-Smith W, Abraham SG, Davidson ES. Effects of memory latency and fine-grain parallelism on Astronautics ZS-1 performance Proceedings of the Hawaii International Conference On System Science. 1: 288-296.  1
1990 Chaar JK, Davidson ES. Cyclic job shop scheduling using reservation tables . 2128-2135.  1
1988 Davis TA, Davidson ES. Pairwise Reduction for the Direct, Parallel Solution of Sparse, Unsymmetric Sets of Linear Equations Ieee Transactions On Computers. 37: 1648-1654. DOI: 10.1109/12.9742  1
1988 Tang Jh, Davidson ES, Tong J. Polycyclic vector scheduling vs. chaining on 1-port vector supercomputers . 122-129.  1
1988 McNiven GD, Davidson ES. ANALYSIS OF MEMORY REFERENCING BEHAVIOR FOR DESIGN OF LOCAL MEMORIES . 56-63.  1
1987 Emma PG, Davidson ES. Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance Ieee Transactions On Computers. 859-875. DOI: 10.1109/TC.1987.1676981  1
1987 Davis TA, Davidson ES. PSSOLVE: A CONCURRENT ALGORITHM FOR SOLVING SPARSE SYSTEMS OF LINEAR EQUATIONS Proceedings of the International Conference On Parallel Processing. 483-490.  1
1986 Kuck DJ, Davidson ES, Lawrie DH, Sameh AH. Parallel supercomputing today and the cedar approach. Science (New York, N.Y.). 231: 967-74. PMID 17740294 DOI: 10.1126/Science.231.4741.967  1
1986 Abraham SG, Davidson ES. COMMUNICATION MODEL FOR OPTIMIZING HIERARCHICAL MULTIPROCESSOR SYSTEMS Proceedings of the International Conference On Parallel Processing. 467-474.  1
1986 Pleszkun AR, Sohi GS, Kahhaleh BZ, Davidson ES. FEATURES OF THE STRUCTURED MEMORY ACCESS (SMA) ARCHITECTURE Proceedings - Ieee Computer Society International Conference. 259-263.  1
1986 Hsu PYT, Davidson ES. HIGHLY CONCURRENT SCALAR PROCESSING Conference Proceedings - Annual Symposium On Computer Architecture. 386-395.  1
1986 Tredennick N, Davidson ES. COMPCON PANEL: THE RISC VS. CISC DEBATE Proceedings - Ieee Computer Society International Conference. 312-313.  1
1985 Sohi GS, Davidson ES, Patel JH. EFFICIENT LISP-EXECUTION ARCHITECTURE WITH A NEW REPRESENTATION FOR LIST STRUCTURES Conference Proceedings - Annual Symposium On Computer Architecture. 91-98.  1
1985 Hsu PYT, Rahmeh JT, Davidson ES, Abraham JA. TIDBITS: SPEEDUP VIA TIME-DELAY BIT-SLICING IN ALU DESIGN FOR VLSI TECHNOLOGY Conference Proceedings - Annual Symposium On Computer Architecture. 28-35.  1
1985 Jenkins WK, Davidson ES, Paul DF. CUSTOM-DESIGNED INTEGRATED CIRCUIT FOR THE REALIZATION OF RESIDUE NUMBER DIGITAL FILTERS Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 220-223.  1
1984 Sohi GS, Davidson ES. PERFORMANCE OF THE STRUCTURED MEMORY ACCESS (SMA) ARCHITECTURE Proceedings of the International Conference On Parallel Processing. 506-513.  1
1984 Bose P, Davidson ES. DESIGN OF INSTRUCTION SET ARCHITECTURES FOR SUPPORT OF HIGH-LEVEL LANGUAGES Conference Proceedings - Annual Symposium On Computer Architecture. 198-206.  1
1984 Paul DF, Jenkins WK, Davidson ES. RESIDUE ARITHMETIC FOR REAL-TIME APPLICATIONS: HIGH THROUGHPUT AND RELIABILITY USING CUSTOMIZED MODULES . 689-694.  1
1983 Abraham JA, Davidson ES, Patel JH. Memory system design for tolerating single event upsets Ieee Transactions On Nuclear Science. 30: 4339-4344. DOI: 10.1109/Tns.1983.4333134  1
1983 Yeh PCC, Patel JH, Davidson ES. Shared Cache for Multiple-Stream Computer Systems Ieee Transactions On Computers. 38-47. DOI: 10.1109/TC.1983.1676122  1
1983 Wong CY, Fuchs WK, Abraham JA, Davidson ES. DESIGN OF A MICROPROGRAM CONTROL UNIT WITH CONCURRENT ERROR DETECTION Digest of Papers - Ftcs (Fault-Tolerant Computing Symposium). 476-483.  1
1983 Yeh PCC, Patel JH, Davidson ES. PERFORMANCE OF SHARED CACHE FOR PARALLEL-PIPELINED COMPUTER SYSTEMS Conference Proceedings - Annual Symposium On Computer Architecture. 117-123.  1
1983 Pleszkun AR, Davidson ES. STRUCTURED MEMORY ACCESS ARCHITECTURE Proceedings of the International Conference On Parallel Processing. 461-471.  1
1982 Yen DWL, Patel JH, Davidson ES. Memory interference in synchronous multiprocessor systems Ieee Transactions On Computers. 1116-1121. DOI: 10.1109/TC.1982.1675928  1
1982 Mak GP, Abraham JA, Davidson ES. DESIGN OF PLAS WITH CONCURRENT ERROR DETECTION Digest of Papers - Ftcs (Fault-Tolerant Computing Symposium). 303-310.  1
1981 Pleszkun AR, Rau BR, Davidson ES. ADDRESS PREDICTION MECHANISM FOR REDUCING PROCESSOR-MEMORY ADDRESS BANDWIDTH . 141-148.  1
1980 Kumar B, Davidson ES. COMPUTER SYSTEM DESIGN USING A HIERARCHICAL APPROACH TO PERFORMANCE EVALUATION Communications of the Acm. 23: 511-521. DOI: 10.1145/359007.359012  1
1979 Kaminsky WJ, Davidson ES. Developing a Multiple-Instruction-Stream Single-Chip Processor Computer. 12: 66-76. DOI: 10.1109/MC.1979.1658578  1
1979 Davidson ES. TOWARD A MULTIPLE STREAM MICROPROCESSOR SYSTEM 1
1979 Emer JS, Davidson ES. CONTROL STORE ORGANIZATION FOR MULTIPLE STREAM PIPELINED PROCESSORS . 43-48.  1
1979 Davidson ES. Summary appraisals of the nation's groundwater resources - lower Colorado region Us Geological Survey Professional Paper. 813.  0.01
1978 Kumar B, Davidson ES. PERFORMANCE EVALUATION OF HIGHLY CONCURRENT COMPUTERS BY DETERMINISTIC SIMULATION Communications of the Acm. 21: 904-913. DOI: 10.1145/359642.359646  1
1977 Briggs FA, Davidson ES. Organization of Semiconductor Memories for Parallel-Pipelined Processors Ieee Transactions On Computers. 162-169. DOI: 10.1109/Tc.1977.5009295  1
1977 Hammerstrom DW, Davidson ES. INFORMATION CONTENT OF CPU MEMORY REFERENCING BEHAVIOR . 184-192.  1
1976 Patel JH, Davidson ES. IMPROVING THE THROUGHPUT OF A PIPELINE BY INSERTION OF DELAYS Symp On Comput Archit, 3rd Annu, Conf Proc. 159-164.  1
1975 Davidson ES, Thomas AT, Shar LE, Patel JH. EFFECTIVE CONTROL FOR PIPELINED COMPUTERS . 181-184.  1
1974 Lee HPS, Davidson ES. Redundancy Testing in Combinational Networks Ieee Transactions On Computers. 1029-1047. DOI: 10.1109/T-C.1974.223804  1
1974 Shar LE, Davidson ES. A multiminiprocessor system implemented through pipelining Computer. 7: 42-51. DOI: 10.1109/Mc.1974.6323457  1
1974 Davidson ES. SCHEDULING FOR PIPELINED PROCESSORS . 58-60.  1
1972 Lee HP, Davidson ES. Comments on “A Minimization Technique for TANT Networks” Ieee Transactions On Computers. 407. DOI: 10.1109/TC.1972.5008987  1
1972 Lee HP, Davidson ES. A Transform for NAND Network Design Ieee Transactions On Computers. 12-20. DOI: 10.1109/T-C.1972.223426  1
1969 Davidson ES, Metze G. Remarks on “Comments on ‘An Algorithm for Synthesis of Multiple-Output Combinational Logic’” Ieee Transactions On Computers. 863-864. DOI: 10.1109/T-C.1969.222786  1
1968 Davidson ES, Metze G. Comments on “An Algorithm for Synthesis of Multiple-Output Combinational Logic” Ieee Transactions On Computers. 1091-1092. DOI: 10.1109/Tc.1968.226866  1
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