Yee-Chia Yeo, Ph.D. - Publications

Affiliations: 
2002 University of California, Berkeley, Berkeley, CA, United States 
Area:
Semiconductor Device Technologies

124 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Xu S, Han K, Huang YC, Lee KH, Kang Y, Masudy-Panah S, Wu Y, Lei D, Zhao Y, Wang H, Tan CS, Gong X, Yeo YC. Integrating GeSn photodiode on a 200 mm Ge-on-insulator photonics platform with Ge CMOS devices for advanced OEIC operating at 2 μm band. Optics Express. 27: 26924-26939. PMID 31674563 DOI: 10.1364/Oe.27.026924  0.392
2018 Wang W, Lei D, Huang YC, Lee KH, Loke WK, Dong Y, Xu S, Tan CS, Wang H, Yoon SF, Gong X, Yeo YC. High-performance GeSn photodetector and fin field-effect transistor (FinFET) on an advanced GeSn-on-insulator platform. Optics Express. 26: 10305-10314. PMID 29715969 DOI: 10.1364/Oe.26.010305  0.429
2017 Kumar A, Lee SY, Yadav S, Tan KH, Loke WK, Dong Y, Lee KH, Wicaksono S, Liang G, Yoon SF, Antoniadis D, Yeo YC, Gong X. Integration of InGaAs MOSFETs and GaAs/ AlGaAs lasers on Si Substrate for advanced opto-electronic integrated circuits (OEICs). Optics Express. 25: 31853-31862. PMID 29245855 DOI: 10.1364/Oe.25.031853  0.306
2017 Holland M, van Dal M, Duriez B, Oxland R, Vellianitis G, Doornbos G, Afzalian A, Chen TK, Hsieh CH, Ramvall P, Vasen T, Yeo YC, Passlack M. Atomically flat and uniform relaxed III-V epitaxial films on silicon substrate for heterogeneous and hybrid integration. Scientific Reports. 7: 14632. PMID 29116157 DOI: 10.1038/S41598-017-15025-0  0.411
2017 Dong Y, Wang W, Xu S, Lei D, Gong X, Guo X, Wang H, Lee SY, Loke WK, Yoon SF, Yeo YC. Two-micron-wavelength germanium-tin photodiodes with low dark current and gigahertz bandwidth. Optics Express. 25: 15818-15827. PMID 28789094 DOI: 10.1364/OE.25.015818  0.347
2017 Yadav S, Tan KH, Kumar A, Goh KH, Liang G, Yoon S, Gong X, Yeo Y. Monolithic Integration of InAs Quantum-Well n-MOSFETs and Ultrathin Body Ge p-MOSFETs on a Si Substrate Ieee Transactions On Electron Devices. 64: 353-360. DOI: 10.1109/Ted.2016.2637382  0.422
2016 Low KL, Yeo YC, Liang G. Ultimate performance projection of ultrathin body transistor based on group IV, III-V, and 2-D-materials Ieee Transactions On Electron Devices. 63: 773-780. DOI: 10.1109/Ted.2015.2508815  0.334
2016 Oxland R, Li X, Chang SW, Wang SW, Vasen T, Ramvall P, Contreras-Guerrero R, Rojas-Ramirez J, Holland M, Doornbos G, Chang YS, MacIntyre DS, Thoms S, Droopad R, Yeo YC, et al. InAs FinFETs with Hfin = 20 nm fabricated using a top-down etch process Ieee Electron Device Letters. 37: 261-264. DOI: 10.1109/LED.2016.2521001  0.338
2016 Doornbos G, Holland M, Vellianitis G, Dal MJHV, Duriez B, Oxland R, Afzalian A, Chen T, Hsieh G, Passlack M, Yeo Y. High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si Substrates Ieee Journal of the Electron Devices Society. 4: 253-259. DOI: 10.1109/Jeds.2016.2574203  0.46
2016 Goh KH, Tan KH, Yadav S, Annie, Yoon SF, Liang G, Gong X, Yeo YC. Gate-all-around CMOS (InAs n-FET and GaSb p-FET) based on vertically-stacked nanowires on a Si platform, enabled by extremely-thin buffer layer technology and common gate stack and contact modules Technical Digest - International Electron Devices Meeting, Iedm. 2016: 15.4.1-15.4.4. DOI: 10.1109/IEDM.2015.7409704  0.4
2016 Yeo YC, Gong X, Van Dal MJH, Vellianitis G, Passlack M. Germanium-based transistors for future high performance and low power logic applications Technical Digest - International Electron Devices Meeting, Iedm. 2016: 2.4.1-2.4.4. DOI: 10.1109/IEDM.2015.7409613  0.419
2016 Yadav S, Tan KH, Annie, Goh KH, Subramanian S, Low KL, Chen N, Jia B, Yoon SF, Liang G, Gong X, Yeo YC. First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules Technical Digest - International Electron Devices Meeting, Iedm. 2016: 2.3.1-2.3.4. DOI: 10.1109/IEDM.2015.7409612  0.364
2016 Kohen D, Nguyen XS, Yadav S, Kumar A, Made RI, Heidelberger C, Gong X, Lee KH, Lee KEK, Yeo YC, Yoon SF, Fitzgerald EA. Heteroepitaxial growth of In0.30Ga0.70As high-electron mobility transistor on 200 mm silicon substrate using metamorphic graded buffer Aip Advances. 6: 85106. DOI: 10.1063/1.4961025  0.315
2016 Lei D, Wang W, Zhang Z, Pan J, Gong X, Liang G, Tok ES, Yeo YC. Ge0.83Sn0.17 p-channel metal-oxide-semiconductor field-effect transistors: Impact of sulfur passivation on gate stack quality Journal of Applied Physics. 119. DOI: 10.1063/1.4939761  0.383
2015 Dong Y, Wang W, Lei D, Gong X, Zhou Q, Lee SY, Loke WK, Yoon SF, Tok ES, Liang G, Yeo YC. Suppression of dark current in germanium-tin on silicon p-i-n photodiode by a silicon surface passivation technique. Optics Express. 23: 18611-9. PMID 26191919 DOI: 10.1364/Oe.23.018611  0.344
2015 Dong Y, Wang W, Lei D, Gong X, Zhou Q, Lee SY, Loke WK, Yoon SF, Tok ES, Liang G, Yeo YC. Suppression of dark current in germanium-tin on silicon p-i-n photodiode by a silicon surface passivation technique Optics Express. 23: 18611-18619. DOI: 10.1364/OE.23.018611  0.342
2015 Huang ML, Chang SW, Chen MK, Fan CH, Lin HT, Lin CH, Chu RL, Lee KY, Khaderbad MA, Chen ZC, Chen CH, Lin LT, Lin HJ, Chang HC, Yang CL, ... ... Yeo YC, et al. In0.53Ga0.47As MOSFETs with high channel mobility and gate stack quality fabricated on 300 mm Si substrate Digest of Technical Papers - Symposium On Vlsi Technology. 2015: T204-T205. DOI: 10.1109/VLSIT.2015.7223675  0.331
2015 Van Dal MJH, Duriez B, Vellianitis G, Doornbos G, Passlack M, Yeo YC, Diaz CH. Germanium n-Channel Planar FET and FinFET: Gate-Stack and Contact Optimization Ieee Transactions On Electron Devices. 62: 3567-3574. DOI: 10.1109/Ted.2015.2477441  0.445
2015 Wang SW, Vasen T, Doornbos G, Oxland R, Chang SW, Li X, Contreras-Guerrero R, Holland M, Wang CH, Edirisooriya M, Rojas-Ramirez JS, Ramvall P, Thoms S, MacIntyre DS, Vellianitis G, ... ... Yeo YC, et al. Field-Effect Mobility of InAs Surface Channel nMOSFET with Low Dit Scaled Gate-Stack Ieee Transactions On Electron Devices. 62: 2429-2436. DOI: 10.1109/Ted.2015.2445854  0.426
2015 Guo Y, Zhang X, Low KL, Lam KT, Yeo YC, Liang G. Effect of Body Thickness on the Electrical Performance of Ballistic n-Channel GaSb Double-Gate Ultrathin-Body Transistor Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2014.2387194  0.303
2015 Dong Y, Wang W, Xu X, Gong X, Lei D, Zhou Q, Xu Z, Loke WK, Yoon SF, Liang G, Yeo YC. Germanium-Tin on Si avalanche photodiode: Device design and technology demonstration Ieee Transactions On Electron Devices. 62: 128-135. DOI: 10.1109/Ted.2014.2366205  0.354
2015 Goh KH, Yeo YC. Novel short-channel In0.53Ga0.47As junctionless nanowire nFET with raised s/d structure: An ultimately scaled 1-D transistor architecture 2014 Silicon Nanoelectronics Workshop, Snw 2014. DOI: 10.1109/SNW.2014.7348538  0.328
2015 Esseni D, Ionescu AM, Seabaugh A, Yeo YC. Foreword special issue on transistors with steep subthreshold swing for low-power electronics Ieee Journal of the Electron Devices Society. 3: 86-87. DOI: 10.1109/Jeds.2015.2418911  0.491
2014 Gupta S, Gong X, Zhang R, Yeo YC, Takagi S, Saraswat KC. New materials for post-Si computing: Ge and GeSn devices Mrs Bulletin. 39: 678-686. DOI: 10.1557/Mrs.2014.163  0.397
2014 Guo P, Cheng R, Wang W, Zhang Z, Pan J, Tok ES, Yeo Y. Silicon Surface Passivation Technology for Germanium-Tin P-Channel MOSFETs: Suppression of Germanium and Tin Segregation for Mobility Enhancement Ecs Journal of Solid State Science and Technology. 3. DOI: 10.1149/2.0111408Jss  0.337
2014 Gong X, Yang Y, Guo P, Wang W, Cheng R, Wang L, Tok ES, Yeo YC. (Invited) Germanium-Tin P-Channel Field-Effect Transistor with Low-Temperature Si2H6 Passivation Ecs Transactions. 64: 851-868. DOI: 10.1149/06406.0851ECST  0.304
2014 Ding Y, Zhou Q, Liu B, Gyanathan A, Yeo Y. An Expandable ${\rm ZnS}\hbox{-}{\rm SiO}_{2}$ Liner Stressor for N-Channel FinFETs Ieee Transactions On Electron Devices. 61: 1963-1971. DOI: 10.1109/Ted.2014.2317717  0.372
2014 Low KL, Yeo YC, Liang G. Voltage scalability of double-gate ultra-thin-body field-effect transistors with channel materials from group IV, III-V to 2D-materials based on ITRS metrics for year 2018 and beyond Device Research Conference - Conference Digest, Drc. 203-204. DOI: 10.1109/DRC.2014.6872368  0.33
2013 Liu X, Zhan C, Chan KW, Owen MHS, Liu W, Chi DZ, Tan LS, Chen KJ, Yeo Y. AlGaN/GaN Metal–Oxide–Semiconductor High-Electron-Mobility Transistors with a High Breakdown Voltage of 1400 V and a Complementary Metal–Oxide–Semiconductor Compatible Gold-Free Process Japanese Journal of Applied Physics. 52. DOI: 10.7567/Jjap.52.04Cf06  0.363
2013 Gong X, Su S, Liu B, Wang L, Wang W, Yang Y, Cheng R, Kong E, Cheng B, Han G, Yeo Y. Fabrication and Negative Bias Temperature Instability (NBTI) Study on Ge0.97Sn0.03 P-MOSFETs with Si2H6 Passivation and HfO2 High-k and TaN Metal Gate Ecs Transactions. 50: 949-956. DOI: 10.1149/05009.0949ECST  0.308
2013 Yeo YC, Han G, Gong X, Wang L, Wang W, Yang Y, Guo P, Liu B, Su S, Zhang G, Xue C, Cheng B. (Invited) Tin-Incorporated Source/Drain and Channel Materials for Field-Effect Transistors Ecs Transactions. 50: 931-936. DOI: 10.1149/05009.0931ECST  0.302
2013 Chin H, Ling M, Liu B, Zhang X, Li J, Liu Y, Hu J, Yeo Y. Metrology solutions for high performance germanium multi-gate field-effect transistors using optical scatterometry Proceedings of Spie. 8681. DOI: 10.1117/12.2013413  0.333
2013 Yang Y, Han G, Guo P, Wang W, Gong X, Wang L, Low KL, Yeo YC. Germanium-tin p-channel tunneling field-effect transistor: Device design and technology demonstration Ieee Transactions On Electron Devices. 60: 4048-4056. DOI: 10.1109/TED.2013.2287031  0.382
2013 Liu B, Zhan C, Yang Y, Cheng R, Guo P, Zhou Q, Kong EY, Daval N, Veytizou C, Delprat D, Nguyen B, Yeo Y. Germanium Multiple-Gate Field-Effect Transistor With In Situ Boron-Doped Raised Source/Drain Ieee Transactions On Electron Devices. 60: 2135-2141. DOI: 10.1109/TED.2013.2262135  0.301
2013 Liu B, Gong X, Zhan C, Han G, Chin H, Ling M, Li J, Liu Y, Hu J, Daval N, Veytizou C, Delprat D, Nguyen B, Yeo Y. Germanium Multiple-Gate Field-Effect Transistors Formed on Germanium-on-Insulator Substrate Ieee Transactions On Electron Devices. 60: 1852-1860. DOI: 10.1109/Ted.2013.2258924  0.424
2013 Gong X, Han G, Liu B, Wang L, Wang W, Yang Y, Kong EY, Su S, Xue C, Cheng B, Yeo Y. Sub-400 degrees C Si2H6 Passivation, HfO2 Gate Dielectric, and Single TaN Metal Gate: A Common Gate Stack Technology for In0.7Ga0.3As and Ge1-xSnx CMOS Ieee Transactions On Electron Devices. 60: 1640-1648. DOI: 10.1109/Ted.2013.2255057  0.43
2013 Gong X, Liu B, Yeo Y. Gate Stack Reliability of MOSFETs With High-Mobility Channel Materials: Bias Temperature Instability Ieee Transactions On Device and Materials Reliability. 13: 524-533. DOI: 10.1109/Tdmr.2013.2277935  0.481
2013 Yeo YC. Technology options for reducing contact resistances in nanoscale metal-oxide-semiconductor field-effect transistors Proceedings - Winter Simulation Conference. 128-131. DOI: 10.1109/INEC.2013.6465975  0.319
2013 Guo P, Han G, Gong X, Liu B, Yang Y, Wang W, Zhou Q, Pan J, Zhang Z, Tok ES, Yeo Y. Ge0.97Sn0.03 p-channel metal-oxide-semiconductor field-effect transistors: Impact of Si surface passivation layer thickness and post metal annealing Journal of Applied Physics. 114: 44510. DOI: 10.1063/1.4816695  0.426
2013 Yang Y, Low KL, Wang W, Guo P, Wang L, Han G, Yeo Y. Germanium-tin n-channel tunneling field-effect transistor: Device physics and simulation study Journal of Applied Physics. 113: 194507. DOI: 10.1063/1.4805051  0.309
2013 Guo H, Zhang X, Zhu, Z, Kong E, Yeo Y. Junctionless Π‐gate transistor with indium gallium arsenide channel Electronics Letters. 49: 402-404. DOI: 10.1049/EL.2012.4535  0.337
2013 Wang L, Su S, Wang W, Gong X, Yang Y, Guo P, Zhang G, Xue C, Cheng B, Han G, Yeo Y. Strained germanium–tin (GeSn) p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with ammonium sulfide passivation Solid-State Electronics. 83: 66-70. DOI: 10.1016/J.Sse.2013.01.031  0.398
2012 Zhu Z, Gong X, Ivana I, Yeo Y. In$_{0.53}$Ga$_{0.47}$As N-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Shallow Metallic Source and Drain Extensions and Offset N$^{+}$ Doped Regions for Leakage Suppression Japanese Journal of Applied Physics. 51: 02BF03. DOI: 10.1143/JJAP.51.02BF03  0.305
2012 Ivana I, Subramanian S, Owen MHS, Tan KH, Loke WK, Wicaksono S, Yoon SF, Yeo Y. N-Channel InGaAs Field-Effect Transistors formed on Germanium-on-Insulator Substrates Applied Physics Express. 5: 116502. DOI: 10.1143/APEX.5.116502  0.347
2012 Liu X, Zhan C, Chan KW, Liu W, Tan LS, Chen KJ, Yeo Y. AlGaN/GaN-on-Silicon Metal–Oxide–Semiconductor High-Electron-Mobility Transistor with Breakdown Voltage of 800 V and On-State Resistance of 3 mΩ·cm2 Using a Complementary Metal–Oxide–Semiconductor Compatible Gold-Free Process Applied Physics Express. 5: 66501. DOI: 10.1143/Apex.5.066501  0.375
2012 Han G, Yang Y, Guo P, Zhan C, Low KL, Goh KH, Liu B, Toh EH, Yeo YC. PBTI characteristics of N-channel tunneling field effect transistor with HfO 2 gate dielectric: New insights and physical model International Symposium On Vlsi Technology, Systems, and Applications, Proceedings. DOI: 10.1109/VLSI-TSA.2012.6210114  0.373
2012 Liu B, Gong X, Han G, Lim PSY, Tong Y, Zhou Q, Yang Y, Daval N, Veytizou C, Delprat D, Nguyen B, Yeo Y. High-Performance Germanium $\Omega$ -Gate MuGFET With Schottky-Barrier Nickel Germanide Source/Drain and Low-Temperature Disilane-Passivated Gate Stack Ieee Electron Device Letters. 33: 1336-1338. DOI: 10.1109/Led.2012.2207368  0.453
2011 Han G, Guo P, Yang Y, Fan L, Yee YS, Zhan C, Yeo Y. Source Engineering for Tunnel Field-Effect Transistor: Elevated Source with Vertical Silicon?Germanium/Germanium Heterostructure Japanese Journal of Applied Physics. 50. DOI: 10.1143/Jjap.50.04Dj07  0.478
2011 Zhang X, Guo H, Lin HY, Cheng CC, Ko CH, Wann CH, Luo GL, Chang C, Chien C, Han ZY, Huang SC, Chin HC, Gong X, Koh SM, Lim PSY, ... Yeo YC, et al. Self-aligned contact metallization technology for III-V metal-oxide-semiconductor field effect transistors Journal of Vacuum Science & Technology B. 29: 32209. DOI: 10.1116/1.3592211  0.322
2011 Lam K, Yang Y, Samudra GS, Yeo Y, Liang G. Electrostatics of Ultimately Thin-Body Tunneling FET Using Graphene Nanoribbon Ieee Electron Device Letters. 32: 431-433. DOI: 10.1109/Led.2010.2103372  0.315
2011 Chin H, Gong X, Wang L, Lee HK, Shi L, Yeo Y. III–V Multiple-Gate Field-Effect Transistors With High-Mobility $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ Channel and Epi-Controlled Retrograde-Doped Fin Ieee Electron Device Letters. 32: 146-148. DOI: 10.1109/LED.2010.2091672  0.326
2011 Liu X, Low EKF, Pan J, Liu W, Teo KL, Tan L, Yeo Y. Impact of In situ vacuum anneal and SiH4 treatment on electrical characteristics of AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors Applied Physics Letters. 99: 93504. DOI: 10.1063/1.3633104  0.38
2011 Liu X, Liu B, Low EKF, Liu W, Yang M, Tan L, Teo KL, Yeo Y. Local stress induced by diamond-like carbon liner in AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors and impact on electrical characteristics Applied Physics Letters. 98: 183502. DOI: 10.1063/1.3584856  0.376
2011 Han G, Guo P, Yang Y, Zhan C, Zhou Q, Yeo Y. Silicon-based tunneling field-effect transistor with elevated germanium source formed on (110) silicon substrate Applied Physics Letters. 98: 153502. DOI: 10.1063/1.3579242  0.315
2010 Yang Y, Guo PF, Han GQ, Zhan CL, Fan L, Yeo YC. Drive Current Enhancement with Invasive Source in Double Gate Tunneling Field-Effect Transistors The Japan Society of Applied Physics. DOI: 10.7567/Ssdm.2010.F-5-5  0.31
2010 Koh S, Wong H, Gong X, Ng C, Variam N, Henry T, Erokhin Y, Samudra GS, Yeo Y. Strained n-Channel Field-Effect Transistors with Channel Proximate Silicon–Carbon Source/Drain Stressors for Performance Enhancement Journal of the Electrochemical Society. 157: H1088. DOI: 10.1149/1.3493601  0.307
2010 Lam K, Seah D, Chin S, Bala Kumar S, Samudra G, Yeo Y, Liang G. A Simulation Study of Graphene-Nanoribbon Tunneling FET With Heterojunction Channel Ieee Electron Device Letters. 31: 555-557. DOI: 10.1109/Led.2010.2045339  0.346
2010 Koh S, Samudra GS, Yeo Y. Carrier transport in strained N-channel field effect transistors with channel proximate silicon-carbon source/drain stressors Applied Physics Letters. 97: 032111. DOI: 10.1063/1.3465661  0.321
2009 Yeo YC. Realizing steep subthreshold swing with impact ionization transistors International Symposium On Vlsi Technology, Systems, and Applications, Proceedings. 43-44. DOI: 10.1109/VTSA.2009.5159284  0.318
2009 Lee RTP, Chi DZ, Yeo Y. Platinum Germanosilicide as Source/Drain Contacts in P-Channel Fin Field-Effect Transistors (FinFETs) Ieee Transactions On Electron Devices. 56: 1458-1465. DOI: 10.1109/TED.2009.2021351  0.309
2009 Tan K, Yang M, Liow T, Lee RTP, Yeo Y. Ultra High-Stress Liner Comprising Diamond-Like Carbon for Performance Enhancement of p-Channel Multiple-Gate Transistors Ieee Transactions On Electron Devices. 56: 1277-1283. DOI: 10.1109/TED.2009.2019388  0.307
2009 Yang J, Chen J, Wise R, Steinmann P, Yu M, Kwong D, Li M, Yeo Y, Zhu C. Effective Modulation of Quadratic Voltage Coefficient of Capacitance in MIM Capacitors Using $\hbox{Sm}_{2}\hbox{O}_{3}/\hbox{SiO}_{2}$ Dielectric Stack Ieee Electron Device Letters. 30: 460-462. DOI: 10.1109/Led.2009.2015970  0.353
2009 Sinha M, Lee RTP, Tan KM, Lo GQ, Chor EF, Yeo YC. Novel aluminum segregation at NiSi/p+-Si source/drain contact for drive current enhancement in PFinFETs Ieee Electron Device Letters. 30: 85-87. DOI: 10.1109/LED.2008.2008826  0.319
2008 Chin H, Zhu M, Samudra G, Yeo Y. Epitaxial Growth of Single Crystalline Ge Films on GaAs Substrates for CMOS Device Integration Mrs Proceedings. 1068. DOI: 10.1557/PROC-1068-C07-02  0.38
2008 Yeo YC. Carbon- and tin- Incorporated source/drain stressors for CMOS transistors Ecs Transactions. 16: 39-46. DOI: 10.1149/1.2986751  0.312
2008 Chin H, Zhu M, Samudra GS, Yeo Y. n-Channel GaAs MOSFET with TaN∕HfAlO Gate Stack Formed Using In Situ Vacuum Anneal and Silane Passivation Journal of the Electrochemical Society. 155: H464. DOI: 10.1149/1.2907381  0.391
2008 Tan K, Liow T, Lee RTP, Zhu M, Hoe K, Tung C, Balasubramanian N, Samudra GS, Yeo Y. Novel Extended-Pi Shaped Silicon–Germanium Source/Drain Stressors for Strain and Performance Enhancement in p-Channel Tri-Gate Fin-Type Field-Effect Transistor Japanese Journal of Applied Physics. 47: 2589-2592. DOI: 10.1143/JJAP.47.2589  0.322
2008 Lim AE, Lee RTP, Koh ATY, Samudra GS, Kwong D, Yeo Y. Effectiveness of Aluminum Incorporation in Nickel Silicide and Nickel Germanide Metal Gates for Work Function Reduction Japanese Journal of Applied Physics. 47: 2383-2387. DOI: 10.1143/Jjap.47.2383  0.386
2008 Toh EH, Wang GH, Weeks D, Zhu M, Bauer M, Spear J, Chan L, Thomas SG, Samudra G, Yeo YC. P-channel I-MOS transistor featuring silicon nano-wire with multiple-gates, strained Si1-yCy I-region, in situ doped Si 1-yCy source, and sub-5 mV/decade subthreshold swing International Symposium On Vlsi Technology, Systems, and Applications, Proceedings. 24-25. DOI: 10.1109/VTSA.2008.4530781  0.38
2008 Liow TY, Tan KM, Lee RTP, Zhu M, Tan BLH, Samudra GS, Balasubramanian N, Yeo YC. 5 nm gate length nanowire-FETs and planar UTB-FETs with pure germanium source/drain stressors and laser-free Melt-Enhanced Dopant (MeltED) diffusion and activation technique Digest of Technical Papers - Symposium On Vlsi Technology. 36-37. DOI: 10.1109/VLSIT.2008.4588554  0.305
2008 Lim AE-, Lee RTP, Samudra GS, Kwong D, Yeo Y. Novel Rare-Earth Dielectric Interlayers for Wide NMOS Work-Function Tunability in Ni-FUSI Gates Ieee Transactions On Electron Devices. 55: 2370-2377. DOI: 10.1109/Ted.2008.927391  0.338
2008 Liow TY, Tan KM, Lee RTP, Zhu M, Tan BLH, Balasubramanian N, Yeo YC. Strained silicon nanowire transistors with germanium source and drain stressors Ieee Transactions On Electron Devices. 55: 3048-3055. DOI: 10.1109/TED.2008.2005153  0.303
2008 Tan K, Fang W, Yang M, Liow T, Lee RT, Balasubramanian N, Yeo Y. Diamond-Like Carbon (DLC) Liner: A New Stressor for P-Channel Multiple-Gate Field-Effect Transistors Ieee Electron Device Letters. 29: 750-752. DOI: 10.1109/LED.2008.923710  0.302
2008 Lee RT, Tan K, Lim AE, Liow T, Samudra GS, Chi D, Yeo Y. P-Channel Tri-Gate FinFETs Featuring $\hbox{Ni}_{1 - y}\hbox{Pt}_{y} \hbox{SiGe}$ Source/Drain Contacts for Enhanced Drive Current Performance Ieee Electron Device Letters. 29: 438-441. DOI: 10.1109/LED.2008.920755  0.306
2008 Liu F, Wong HS, Ang KW, Zhu M, Wang X, Lai DMY, Lim PC, Yeo YC. Laser annealing of amorphous germanium on silicon-germanium source/drain for strain and performance enhancement in pMOSFETs Ieee Electron Device Letters. 29: 885-888. DOI: 10.1109/LED.2008.2001029  0.302
2008 Lim AE, Lee RTP, Samudra GS, Kwong D, Yeo Y. Modification of Molybdenum Gate Electrode Work Function via (La-, Al-Induced) Dipole Effect at High-$k/\hbox{SiO}_{2}$ Interface Ieee Electron Device Letters. 29: 848-851. DOI: 10.1109/Led.2008.2000997  0.363
2008 Toh EH, Wang GH, Chan L, Weeks D, Bauer M, Spear J, Thomas SG, Samudra G, Yeo YC. Cointegration of in situ doped silicon-carbon source and silicon-carbon I-region in P-channel silicon nanowire impact-ionization transistor Ieee Electron Device Letters. 29: 731-733. DOI: 10.1109/LED.2008.2000611  0.3
2008 Toh E, Wang GH, Chan L, Samudra G, Yeo Y. A Double-Spacer I-MOS Transistor With Shallow Source Junction and Lightly Doped Drain for Reduced Operating Voltage and Enhanced Device Performance Ieee Electron Device Letters. 29: 189-191. DOI: 10.1109/LED.2007.914100  0.308
2008 Chin HC, Zhu M, Lee ZC, Liu X, Tan KM, Lee HK, Shi L, Tang LJ, Tung CH, Lo GQ, Tan LS, Yeo YC. A new silane-ammonia surface passivation technology for realizing inversion-type surface-channel aAs N-MOSFET with 160 nm gate length and high-quality metal-gate/high-k dielectric stack Technical Digest - International Electron Devices Meeting, Iedm. DOI: 10.1109/IEDM.2008.4796700  0.403
2008 Yeo YC. Towards ultimate CMOS performance with new stressor materials International Conference On Solid-State and Integrated Circuits Technology Proceedings, Icsict. 121-125. DOI: 10.1109/ICSICT.2008.4734488  0.31
2008 Zhu M, Chin H, Samudra GS, Yeo Y. Fabrication of gate stack with high gate work function for implantless enhancement-mode GaAs n-channel metal-oxide-semiconductor field effect transistor applications Applied Physics Letters. 92: 123513. DOI: 10.1063/1.2905259  0.457
2007 Lim AE-, Lee RTP, Koh ATY, Samudra GS, Kwong D, Yeo Y. Effectiveness of Aluminum Incorporation in Nickel Silicide and Nickel Germanide Metal Gates for Work Function Reduction The Japan Society of Applied Physics. 2007: 856-857. DOI: 10.7567/Ssdm.2007.A-9-2  0.387
2007 Lee RTP, Tan K, Liow T, Lim AE, Lo G, Samudra GS, Chi D, Yeo Y. Sub-30 nm FinFETs with Schottky-Barrier Source/Drain Featuring Complementary Metal Silicides and Fully-Silicided Gate for P-FinFETs Mrs Proceedings. 995. DOI: 10.1557/PROC-0995-G05-17  0.373
2007 Wang GH, Toh E, Hoe K, Tripathy S, Lo G, Samudra G, Yeo Y. Sub 50nm Strained n-FETs Formed on Silicon-Germanium-on-Insulator Substrates and the Integration of Silicon Source/Drain Stressors Mrs Proceedings. 995. DOI: 10.1557/PROC-0995-G03-04  0.383
2007 Yeo Y, Ang K, Lin J, Lam C. Strain-Transfer Structure Beneath the Transistor Channel for Increasing the Strain Effects of Lattice-Mismatched Source and Drain Stressors Mrs Proceedings. 995. DOI: 10.1557/PROC-0995-G01-03  0.302
2007 Wang GH, Toh E, Tung C, Foo Y, Tripathy S, Lo G, Samudra G, Yeo Y. Fabrication of Strain Relaxed Silicon-Germanium-on-Insulator (Si0.35Ge0.65OI) Wafers using Cyclical Thermal Oxidation and Annealing Mrs Proceedings. 994. DOI: 10.1557/PROC-0994-F09-03  0.324
2007 Zhu M, Chin H, Tung C, Yeo Y. In Situ Silane Passivation of Gallium Arsenide and Deposition of High-Permittivity Gate Dielectric for MOS Applications Journal of the Electrochemical Society. 154: H879. DOI: 10.1149/1.2768288  0.324
2007 Wang GH, Toh E, Tung C, Du A, Lo G, Samudra G, Yeo Y. Strained Silicon–Germanium-on-Insulator n-Channel Transistor with Silicon Source and Drain Regions for Performance Enhancement Japanese Journal of Applied Physics. 46: 2062-2066. DOI: 10.1143/JJAP.46.2062  0.339
2007 Wang XP, Lim AE, Yu HY, Li M, Ren C, Loh W, Zhu CX, Chin A, Trigg AD, Yeo Y, Biesemans S, Lo G, Kwong D. Work Function Tunability of Refractory Metal Nitrides by Lanthanum or Aluminum Doping for Advanced CMOS Devices Ieee Transactions On Electron Devices. 54: 2871-2877. DOI: 10.1109/Ted.2007.907130  0.443
2007 Ang K, Wan C, Balasubramanian N, Samudra GS, Yeo Y. Hot-Carrier Effects in Strained n-Channel Transistor With Silicon–Carbon $(\hbox{Si}_{1 - y}\hbox{C}_{y})$ Source/Drain Stressors and Its Orientation Dependence Ieee Electron Device Letters. 28: 996-999. DOI: 10.1109/LED.2007.906933  0.328
2007 Chen J, Wang XP, Li M, Lee SJ, Yu MB, Shen C, Yeo Y. NMOS Compatible Work Function of TaN Metal Gate With Erbium-Oxide-Doped Hafnium Oxide Gate Dielectric Ieee Electron Device Letters. 28: 862-864. DOI: 10.1109/LED.2007.904210  0.347
2007 Lim AE, Lee RTP, Wang XP, Hwang WS, Tung CH, Samudra GS, Kwong D, Yeo Y. Yttrium- and Terbium-Based Interlayer on $ \hbox{SiO}_{2}$ and $\hbox{HfO}_{2}$ Gate Dielectrics for Work Function Modulation of Nickel Fully Silicided Gate in nMOSFET Ieee Electron Device Letters. 28: 482-485. DOI: 10.1109/Led.2007.896892  0.436
2007 Wang XP, Yu HY, Li M, Zhu CX, Biesemans S, Chin A, Sun YY, Feng YP, Lim A, Yeo Y, Loh WY, Lo GQ, Kwong D. Wide $V_{\rm fb}$ and $V_{\rm th}$ Tunability for Metal-Gated MOS Devices With HfLaO Gate Dielectrics Ieee Electron Device Letters. 28: 258-260. DOI: 10.1109/Led.2007.891757  0.473
2007 Lee RTP, Lim AE, Tan K, Liow T, Lo G, Samudra GS, Chi DZ, Yeo Y. N-channel FinFETs With 25-nm Gate Length and Schottky-Barrier Source and Drain Featuring Ytterbium Silicide Ieee Electron Device Letters. 28: 164-167. DOI: 10.1109/LED.2006.889233  0.335
2007 Yeo YC. Planar and multiple-gate transistors with silicon-carbon source/drain Icsict-2006: 2006 8th International Conference On Solid-State and Integrated Circuit Technology, Proceedings. 39-42. DOI: 10.1109/ICSICT.2006.306050  0.391
2007 Toh E, Wang GH, Chan L, Samudra G, Yeo Y. Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction Applied Physics Letters. 91: 243505. DOI: 10.1063/1.2823606  0.33
2007 Toh E, Wang GH, Lo G, Chan L, Samudra G, Yeo Y. Performance enhancement of n-channel impact-ionization metal-oxide-semiconductor transistor by strain engineering Applied Physics Letters. 90: 023505. DOI: 10.1063/1.2430924  0.34
2007 Ang K, Chin H, Chui K, Li M, Samudra GS, Yeo Y. Carrier backscattering characteristics of strained silicon-on-insulator n-MOSFETs featuring silicon-carbon source/drain regions Solid-State Electronics. 51: 1444-1449. DOI: 10.1016/J.Sse.2007.09.013  0.456
2006 Yeo YC. Silicon-carbon source/drain: Selective epitaxy, process integration, and transistor strain engineering Ecs Transactions. 3: 1143-1150. DOI: 10.1149/1.2355908  0.409
2006 Lim AE, Lee RTP, Tung CH, Tripathy S, Kwong D, Yeo Y. Full Silicidation of Silicon Gate Electrodes Using Nickel-Terbium Alloy for MOSFET Applications Journal of the Electrochemical Society. 153: G337. DOI: 10.1149/1.2171827  0.358
2005 Yang T, Shen C, Li M, Ang C, Zhu C, Yeo Y, Samudra G, Kwong D. Interface trap passivation effect in NBTI measurement for p-MOSFET with SiON gate dielectric Ieee Electron Device Letters. 26: 758-760. DOI: 10.1109/LED.2005.855419  0.309
2005 Kang J, Yu H, Ren C, Wang X, Li M, Chan D, Yeo Y, Sa N, Yang H, Liu X, Han R, Kwong D. Improved electrical and reliability Characteristics of HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm EOT fabricated using a gate-first Process Ieee Electron Device Letters. 26: 237-239. DOI: 10.1109/LED.2005.845496  0.36
2005 Ren C, Chan DSH, Faizhal BB, Li MF, Yeo YC, Trigg AD, Agarwal A, Balasubramanian N, Pan JS, Lim PC, Kwong DL. Lanthanide-incorporated metal nitrides with tunable work function and good thermal stability for NMOS devices Digest of Technical Papers - Symposium On Vlsi Technology. 2005: 42-43. DOI: 10.1109/.2005.1469204  0.309
2005 Low T, Li MF, Yeo YC, Fan WJ, Ng ST, Kwong DL. Valence band structure of ultrathin silicon and germanium channels in metal-oxide-semiconductor field-effect transistors Journal of Applied Physics. 98: 024504. DOI: 10.1063/1.1948528  0.396
2005 Ren C, Chan DSH, Wang XP, Faizhal BB, Li MF, Yeo YC, Trigg AD, Agarwal A, Balasubramanian N, Pan JS, Lim PC, Huan ACH, Kwong DL. Physical and electrical properties of lanthanide-incorporated tantalum nitride for n -channel metal-oxide-semiconductor field-effect transistors Applied Physics Letters. 87. DOI: 10.1063/1.1947901  0.348
2005 Shen C, Li MF, Yu HY, Wang XP, Yeo Y, Chan DSH, Kwong D. Physical model for frequency-dependent dynamic charge trapping in metal-oxide-semiconductor field effect transistors with HfO2 gate dielectric Applied Physics Letters. 86: 093510. DOI: 10.1063/1.1874312  0.316
2005 Yeo YC, Sun J. Finite-element study of strain distribution in transistor with silicon-germanium source and drain regions Applied Physics Letters. 86. DOI: 10.1063/1.1846152  0.356
2004 Low T, Li MF, Shen C, Yeo Y, Hou YT, Zhu C, Chin A, Kwong DL. Electron mobility in Ge and strained-Si channel ultrathin-body metal-oxide semi conductor field-effect transistors Applied Physics Letters. 85: 2402-2404. DOI: 10.1063/1.1788888  0.396
2004 Yeo YC. Metal gate technology for nanoscale transistors - Material selection and process integration issues Thin Solid Films. 462: 34-41. DOI: 10.1016/j.tsf.2004.05.039  0.43
2003 Yeo Y, King T, Hu C. MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations Ieee Transactions On Electron Devices. 50: 1027-1035. DOI: 10.1109/Ted.2003.812504  0.621
2002 Lin C, Wang C, Ge C, Huang C, Chang T, Yao L, Chen S, Liang M, Yang F, Yeo Y, Hu C. Novel Strained-Si Substrate Technology for Transistor Performance Enhancement The Japan Society of Applied Physics. DOI: 10.7567/Ssdm.2002.A-1-3  0.499
2002 Chang L, Yang KJ, Yeo YC, Polishchuk I, King TJ, Hu C. Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs Ieee Transactions On Electron Devices. 49: 2288-2294. DOI: 10.1109/Ted.2002.807446  0.716
2002 Yeo Y, Ranade P, King T, Hu C. Effects of high-/spl kappa/ gate dielectric materials on metal and silicon gate workfunctions Ieee Electron Device Letters. 23: 342-344. DOI: 10.1109/Led.2002.1004229  0.614
2002 Polishchuk I, Yeo YC, King TJ, Hu C. Tunneling through multi-layer gate dielectrics - An analytical model Device Research Conference - Conference Digest, Drc. 2002: 105-106. DOI: 10.1109/DRC.2002.1029537  0.618
2002 Yeo YC, Subramanian V, Kedzierski J, Xuan P, King TJ, Bokor J, Hu C. Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel Ieee Transactions On Electron Devices. 49: 279-286. DOI: 10.1109/16.981218  0.61
2002 Yeo YC, King TJ, Hu C. Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology Journal of Applied Physics. 92: 7266-7271. DOI: 10.1063/1.1521517  0.575
2002 Yeo YC, King TJ, Hu C. Direct tunneling leakage current and scalability of alternative gate dielectrics Applied Physics Letters. 81: 2091-2093. DOI: 10.1063/1.1506941  0.566
2001 Ranade P, Lin R, Lu Q, Yeo Y, Takeuchi H, King T, Hu C. Molybdenum Gate Electrode Technology For Deep Sub-Micron CMOS Generations Mrs Proceedings. 670. DOI: 10.1557/Proc-670-K5.2  0.521
2001 Polishchuk I, Yeo YC, Lu Q, King TJ, Hu C. Hot-carrier reliability of p-MOSFET with ultra-thin silicon nitride gate dielectric Ieee International Reliability Physics Symposium Proceedings. 2001: 425-430. DOI: 10.1109/RELPHY.2001.922937  0.662
2001 Polishchuk I, Yeo YC, Lu Q, King TJ, Hu C. Hot-carrier reliability comparison for pmosfets with ultrathin silicon-nitride and silicon-oxide gate dielectrics Ieee Transactions On Device and Materials Reliability. 1: 158-162. DOI: 10.1109/7298.974831  0.709
2001 Polishchuk I, Lu Q, Yeo YC, King TJ, Hu C. Intrinsic reliability projections for a thin jvd silicon nitride gate dielectric in p-mosfet Ieee Transactions On Device and Materials Reliability. 1: 4-8. DOI: 10.1109/7298.946454  0.697
2001 Yeo YC, Lu Q, Ranade P, Takeuchi H, Yang KJ, Polishchuk I, King TJ, Hu C, Song SC, Luan HF, Kwong DL. Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric Ieee Electron Device Letters. 22: 227-229. DOI: 10.1109/55.919237  0.721
2001 Yeo Y, Lu Q, Hu C. MOSFET Gate Oxide Reliability: Anode Hole Injection Model and its Applications International Journal of High Speed Electronics and Systems. 11: 849-886. DOI: 10.1016/S0129-1564(01)00101-5  0.545
2000 Ranade P, Yeo Y, Lu Q, Takeuchi H, King T, Hu C. Molybdenum as a Gate Electrode for Deep Sub-Micron CMOS Technology Mrs Proceedings. 611. DOI: 10.1557/Proc-611-C3.2.1  0.596
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