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Arthur Abnous, Ph.D. - Publications

Affiliations: 
2001 University of California, Berkeley, Berkeley, CA, United States 
Area:
Communications & Networking (COMNET); Design, Modeling and Analysis (DMA); Energy (ENE); Integrated Circuits (INC); Signal Processing (SP); Computer architecture
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11 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2001 Wan M, Zhang H, George V, Benes M, Abnous A, Prabhu V, Rabaey J. Design methodology of a low-energy reconfigurable single-chip DSP system Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 28: 47-61. DOI: 10.1023/A:1008159121620  0.558
2000 Zhang H, Prabhu V, George V, Wan M, Benes M, Abnous A, Rabaey JM. 1-V heterogeneous reconfigurable DSP IC for wireless baseband digital signal processing Ieee Journal of Solid-State Circuits. 35: 1697-1704. DOI: 10.1109/4.881217  0.394
2000 Zhang H, Prabhu V, George V, Wan M, Benes M, Abnous A, Rabaey JM. A 1V heterogeneous reconfigurable processor IC for baseband wireless applications Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 68-69.  0.584
1998 Abnous A, Seno K, Ichikawa Y, Wan M, Rabaey J. Evaluation of a low-power reconfigurable DSP architecture Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1388: 55-60.  0.394
1997 Rabaey JM, Abnous A, Ichikawa Y, Seno K, Wan M. Heterogeneous reconfigurable systems Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 24-34.  0.392
1996 Abnous A, Rabaey J. Ultra-low-power domain-specific multimedia processors Ieee Workshop On Vlsi Signal Processing, Proceedings. 461-470.  0.394
1995 Abnous A, Bagherzadeh N. Architectural design and analysis of a VLIW processor Computers and Electrical Engineering. 21: 119-142. DOI: 10.1016/0045-7906(94)00017-B  0.317
1993 Gray J, Naylor A, Abnous A, Bagherzadeh N. VIPER: A VLIW Integer Microprocessor Ieee Journal of Solid-State Circuits. 28: 1377-1382. DOI: 10.1109/4.262015  0.428
1993 Gray J, Naylor A, Abnous A, Bagherzadeth N. VIPER: A 25-MHz, 100-MIPS peak VLIW microprocessor Proceedings of the Custom Integrated Circuits Conference. 4.1.1-4.1.5.  0.413
1992 Abnous A, Christensen C, Gray J, Lenell J, Naylor A, Bagherzadeh N. VLSI design of the Tiny RISC microprocessor Proceedings of the Custom Integrated Circuits Conference. 30.4.1-30.4.5. DOI: 10.1109/CICC.1992.591875  0.401
1992 Abnous A, Christensen C, Gray J, Lenell J, Naylor A, Bagherzadeh N. Design and implementation of the 'Tiny RISC' microprocessor Microprocessors and Microsystems. 16: 187-193. DOI: 10.1016/0141-9331(92)90021-K  0.37
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