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Kaushik Roy - Publications

Affiliations: 
1990- Electrical and Computer Engineering Purdue University, West Lafayette, IN, United States 
Area:
Electronics and Electrical Engineering
Website:
https://www.purdue.edu/uns/html3month/2005/050211.BOT.academic.html
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496 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2024 Yu E, K GK, Saxena U, Roy K. Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads. Scientific Reports. 14: 9426. PMID 38658597 DOI: 10.1038/s41598-024-59298-8  0.327
2020 Parsa M, Mitchell JP, Schuman CD, Patton RM, Potok TE, Roy K. Bayesian Multi-objective Hyperparameter Optimization for Accurate, Fast, and Efficient Neural Network Accelerator Design. Frontiers in Neuroscience. 14: 667. PMID 32848531 DOI: 10.3389/Fnins.2020.00667  0.327
2020 Xia Q, Berggren KK, Likharev K, Strukov DB, Jiang H, Mikolajick T, Querlioz D, Salinga M, Erickson J, Pi S, Xiong F, Lin P, Li C, Xiong S, Hoskins B, ... ... Roy K, et al. Roadmap on emerging hardware and technology for machine learning. Nanotechnology. PMID 32679577 DOI: 10.1088/1361-6528/Aba70F  0.6
2020 Chakraborty I, Agrawal A, Jaiswal A, Srinivasan G, Roy K. unsupervised learning using stochastic switching in magneto-electric magnetic tunnel junctions. Philosophical Transactions. Series a, Mathematical, Physical, and Engineering Sciences. 378: 20190157. PMID 31865881 DOI: 10.1098/Rsta.2019.0157  0.373
2020 Andrawis R, Roy K. Antiferroelectric Tunnel Junctions as Energy-Efficient Coupled Oscillators: Modeling, Analysis, and Application to Solving Combinatorial Optimization Problems Ieee Transactions On Electron Devices. 67: 2974-2980. DOI: 10.1109/Ted.2020.2993816  0.313
2020 Compagnoni CM, Kang J, Shih Y, Du PP, Kim T, Mouli C, Yang J, Roy K. Editorial Special Issue on “Memory Devices and Technologies for the Next Decade” Ieee Transactions On Electron Devices. 67: 1369-1372. DOI: 10.1109/Ted.2020.2976406  0.328
2020 Jaiswal A, Andrawis R, Agrawal A, Roy K. Functional Read Enabling In-Memory Computations in 1Transistor -1Resistor Memory Arrays Ieee Transactions On Circuits and Systems Ii-Express Briefs. 1-1. DOI: 10.1109/Tcsii.2020.2975658  0.313
2020 Ali MF, Andrawis R, Roy K. Dynamic Read Current Sensing With Amplified Bit-Line Voltage for STT-MRAMs Ieee Transactions On Circuits and Systems Ii-Express Briefs. 67: 551-555. DOI: 10.1109/Tcsii.2019.2915822  0.419
2020 Ali M, Jaiswal A, Kodge S, Agrawal A, Chakraborty I, Roy K. IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array Ieee Transactions On Circuits and Systems. 67: 2521-2531. DOI: 10.1109/Tcsi.2020.2981901  0.346
2020 Koo M, Srinivasan G, Shim Y, Roy K. sBSNN: Stochastic-Bits Enabled Binary Spiking Neural Network With On-Chip Learning for Energy Efficient Neuromorphic Computing at the Edge Ieee Transactions On Circuits and Systems. 67: 2546-2555. DOI: 10.1109/Tcsi.2020.2979826  0.314
2020 Ali MF, Jaiswal A, Roy K. In-Memory Low-Cost Bit-Serial Addition Using Commodity DRAM Technology Ieee Transactions On Circuits and Systems I-Regular Papers. 67: 155-165. DOI: 10.1109/Tcsi.2019.2945617  0.401
2020 Ankit A, Hajj IE, Chalamalasetti SR, Agarwal S, Marinella M, Foltin M, Strachan JP, Milojicic D, Hwu W, Roy K. PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM Ieee Transactions On Computers. 69: 1128-1142. DOI: 10.1109/Tc.2020.2998456  0.303
2020 Yu E, Cho S, Roy K, Park B. A Quantum-Well Charge-Trap Synaptic Transistor With Highly Linear Weight Tunability Ieee Journal of the Electron Devices Society. 8: 834-840. DOI: 10.1109/Jeds.2020.3011409  0.343
2020 Garg I, Panda P, Roy K. A Low Effort Approach to Structured CNN Design Using PCA Ieee Access. 8: 1347-1360. DOI: 10.1109/Access.2019.2961960  0.322
2020 Chakraborty I, Jaiswal A, Saha AK, Gupta SK, Roy K. Pathways to efficient neuromorphic computing with non-volatile memory technologies Applied Physics Reviews. 7: 021308. DOI: 10.1063/1.5113536  0.582
2020 Chakraborty I, Roy D, Garg I, Ankit A, Roy K. Constructing Energy-efficient Mixed-precision Neural Networks through Principal Component Analysis for Edge Intelligence Nature Machine Intelligence. 2: 43-55. DOI: 10.1038/S42256-019-0134-0  0.313
2019 Jain S, Ankit A, Chakraborty I, Gokmen T, Rasch M, Haensch W, Roy K, Raghunathan A. Neural network accelerator design with resistive crossbars: Opportunities and challenges Ibm Journal of Research and Development. 63: 10:1-10:13. DOI: 10.1147/Jrd.2019.2947011  0.397
2019 Jaiswal A, Chakraborty I, Agrawal A, Roy K. 8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing Ieee Transactions On Very Large Scale Integration Systems. 27: 2556-2567. DOI: 10.1109/Tvlsi.2019.2929245  0.385
2019 Ankit A, Koo M, Sen S, Roy K. Powerline Communication for Enhanced Connectivity in Neuromorphic Systems Ieee Transactions On Very Large Scale Integration Systems. 27: 1897-1906. DOI: 10.1109/Tvlsi.2019.2907096  0.344
2019 Chatterjee B, Panda P, Maity S, Biswas A, Roy K, Sen S. Exploiting Inherent Error Resiliency of Deep Neural Networks to Achieve Extreme Energy Efficiency Through Mixed-Signal Neurons Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 27: 1365-1377. DOI: 10.1109/Tvlsi.2019.2896611  0.362
2019 Chen M, Ranjan A, Raghunathan A, Roy K. Cache Memory Design With Magnetic Skyrmions in a Long Nanotrack Ieee Transactions On Magnetics. 55: 1-9. DOI: 10.1109/Tmag.2019.2909188  0.439
2019 Azim ZA, Ostler TA, Xu C, Roy K. Optical Receiver With Helicity-Dependent Magnetization Reversal Ieee Transactions On Magnetics. 55: 1-6. DOI: 10.1109/Tmag.2018.2878008  0.332
2019 Agrawal A, Jaiswal A, Roy D, Han B, Srinivasan G, Ankit A, Roy K. Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays Ieee Transactions On Circuits and Systems I-Regular Papers. 66: 3064-3076. DOI: 10.1109/Tcsi.2019.2907488  0.36
2019 Venkataramani S, Kozhikkottu V, Sabne A, Roy K, Raghunathan A. Logic Synthesis of Approximate Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2019.2940680  0.383
2019 Rathi N, Panda P, Roy K. STDP-Based Pruning of Connections and Weight Quantization in Spiking Neural Networks for Energy-Efficient Recognition Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 668-677. DOI: 10.1109/Tcad.2018.2819366  0.31
2019 Agrawal A, Ankit A, Roy K. SPARE: Spiking Neural Network Acceleration Using ROM-Embedded RAMs as In-Memory-Computation Primitives Ieee Transactions On Computers. 68: 1190-1200. DOI: 10.1109/Tc.2018.2867048  0.361
2019 Andrawis R, Roy K. Nonequilibrium Green's Function and First-Principles Approach to Modeling of Multiferroic Tunnel Junctions Physical Review Applied. 12: 14003. DOI: 10.1103/Physrevapplied.12.014003  0.341
2019 Chakraborty I, Saha G, Roy K. A Photonic In-Memory Computing primitive for Spiking Neural Networks using Phase-Change Materials Physical Review Applied. 11. DOI: 10.1103/Physrevapplied.11.014063  0.335
2019 Reza AK, Roy K. Fast switching in CoTb based ferrimagnetic tunnel junction Journal of Applied Physics. 126: 23901. DOI: 10.1063/1.5089756  0.344
2019 Reza AK, Roy K. Topological semi-metal Na3Bi as efficient spin injector in current driven magnetic tunnel junction Journal of Applied Physics. 126: 233901. DOI: 10.1063/1.5087077  0.326
2018 Wijesinghe P, Liyanagedera C, Roy K. Analog Approach to Constraint Satisfaction Enabled by Spin Orbit Torque Magnetic Tunnel Junctions. Scientific Reports. 8: 6940. PMID 29720596 DOI: 10.1038/S41598-018-24877-Z  0.311
2018 Jaiswal A, Agrawal A, Roy K. In-situ, In-Memory Stateful Vector Logic Operations based on Voltage Controlled Magnetic Anisotropy. Scientific Reports. 8: 5738. PMID 29636489 DOI: 10.1038/S41598-018-23886-2  0.415
2018 Sengupta A, Roy K. Neuromorphic computing enabled by physics of electron spins: Prospects and perspectives Applied Physics Express. 11: 30101. DOI: 10.7567/Apex.11.030101  0.37
2018 Sarwar SS, Venkataramani S, Ankit A, Raghunathan A, Roy K. Energy-Efficient Neural Computing with Approximate Multipliers Acm Journal On Emerging Technologies in Computing Systems. 14: 16. DOI: 10.1145/3097264  0.329
2018 Seo Y, Roy K. High-Density SOT-MRAM Based on Shared Bitline Structure Ieee Transactions On Very Large Scale Integration Systems. 26: 1600-1603. DOI: 10.1109/Tvlsi.2018.2822841  0.454
2018 Jain S, Ranjan A, Roy K, Raghunathan A. Computing in Memory With Spin-Transfer Torque Magnetic RAM Ieee Transactions On Very Large Scale Integration Systems. 26: 470-483. DOI: 10.1109/Tvlsi.2017.2776954  0.393
2018 Chen M, Sengupta A, Roy K. Magnetic Skyrmion as a Spintronic Deep Learning Spiking Neuron Processor Ieee Transactions On Magnetics. 54: 1-7. DOI: 10.1109/Tmag.2018.2845890  0.428
2018 Chakraborty I, Roy D, Roy K. Technology Aware Training in Memristive Neuromorphic Systems for Nonideal Synaptic Crossbars Arxiv: Emerging Technologies. 2: 335-344. DOI: 10.1109/Tetci.2018.2829919  0.306
2018 Andrawis R, Jaiswal A, Roy K. Design and Comparative Analysis of Spintronic Memories Based on Current and Voltage Driven Switching Ieee Transactions On Electron Devices. 65: 2682-2693. DOI: 10.1109/Ted.2018.2833039  0.449
2018 Shim Y, Sengupta A, Roy K. Biased Random Walk Using Stochastic Switching of Nanomagnets: Application to SAT Solver Ieee Transactions On Electron Devices. 65: 1617-1624. DOI: 10.1109/Ted.2018.2808232  0.329
2018 Agrawal A, Jaiswal A, Lee C, Roy K. X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories Ieee Transactions On Circuits and Systems I-Regular Papers. 65: 4219-4232. DOI: 10.1109/Tcsi.2018.2848999  0.373
2018 Pajouhi Z, Roy K. Image Edge Detection Based on Swarm Intelligence Using Memristive Networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1774-1787. DOI: 10.1109/Tcad.2017.2775227  0.352
2018 Chakraborty I, Agrawal A, Roy K. Design of a Low-Voltage Analog-to-Digital Converter Using Voltage-Controlled Stochastic Switching of Low Barrier Nanomagnets Ieee Magnetics Letters. 9: 1-5. DOI: 10.1109/Lmag.2018.2839097  0.444
2018 Jaiswal A, Andrawis R, Roy K. Area-Efficient Nonvolatile Flip-Flop Based on Spin Hall Effect Ieee Magnetics Letters. 9: 1-4. DOI: 10.1109/Lmag.2018.2829676  0.452
2018 Azim ZA, Jaiswal A, Chakraborty I, Roy K. Capacitively Driven Global Interconnect With Energy-Efficient Receiver Based on Magneto-Electric Switching Ieee Magnetics Letters. 9: 1-5. DOI: 10.1109/Lmag.2018.2826460  0.442
2018 Sharma A, Roy K. 1T Non-Volatile Memory Design Using Sub-10nm Ferroelectric FETs Ieee Electron Device Letters. 39: 359-362. DOI: 10.1109/Led.2018.2797887  0.37
2018 Sarwar SS, Srinivasan G, Han B, Wijesinghe P, Jaiswal A, Panda P, Raghunathan A, Roy K. Energy Efficient Neural Computing: A Study of Cross-Layer Approximations Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 8: 796-809. DOI: 10.1109/Jetcas.2018.2835809  0.308
2018 Roy K, Sengupta A, Shim Y. Perspective: Stochastic magnetic devices for cognitive computing Journal of Applied Physics. 123: 210901. DOI: 10.1063/1.5020168  0.326
2018 Patra D, Reza AK, Hassan MK, Katoozi M, Cannon EH, Roy K, Cao Y. Adaptive accelerated aging for 28 nm HKMG technology Microelectronics Reliability. 80: 149-154. DOI: 10.1016/J.Microrel.2017.12.002  0.367
2017 Shim Y, Chen S, Sengupta A, Roy K. Stochastic Spin-Orbit Torque Devices as Elements for Bayesian Inference. Scientific Reports. 7: 14101. PMID 29074891 DOI: 10.1038/S41598-017-14240-Z  0.335
2017 Sengupta A, Liyanagedera CM, Jung B, Roy K. Magnetic Tunnel Junction as an On-Chip Temperature Sensor. Scientific Reports. 7: 11764. PMID 28924221 DOI: 10.1038/S41598-017-11476-7  0.315
2017 Jaiswal A, Roy K. MESL: Proposal for a Non-volatile Cascadable Magneto-Electric Spin Logic. Scientific Reports. 7: 39793. PMID 28045074 DOI: 10.1038/Srep39793  0.448
2017 Goud AA, Venkatesan R, Raghunathan A, Roy K. Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes Acm Journal On Emerging Technologies in Computing Systems. 13: 23. DOI: 10.1145/2967615  0.416
2017 Pajouhi Z, Fong X, Raghunathan A, Roy K. Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC Acm Journal On Emerging Technologies in Computing Systems. 13: 1-20. DOI: 10.1145/2934685  0.726
2017 Raha A, Jaiswal A, Sarwar SS, Jayakumar H, Raghunathan V, Roy K. Designing Energy-Efficient Intermittently Powered Systems Using Spin-Hall-Effect-Based Nonvolatile SRAM Ieee Transactions On Very Large Scale Integration Systems. 26: 294-307. DOI: 10.1109/Tvlsi.2017.2767033  0.429
2017 Seo Y, Fong X, Roy K. Fast and Disturb-Free Nonvolatile Flip-Flop Using Complementary Polarizer MTJ Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 25: 1573-1577. DOI: 10.1109/Tvlsi.2016.2631981  0.707
2017 Radfar M, Yogendra K, Roy K. Stochastic Quantization Using Magnetic Tunnel Junction Devices: A Simulation Study Ieee Transactions On Magnetics. 53: 1-6. DOI: 10.1109/Tmag.2016.2635631  0.341
2017 Azim ZA, Chen M, Roy K. Skyrmion Sensor-Based Low-Power Global Interconnects Ieee Transactions On Magnetics. 53: 1-6. DOI: 10.1109/Tmag.2016.2603462  0.422
2017 Jaiswal A, Agrawal A, Roy K. Robust and Cascadable Nonvolatile Magnetoelectric Majority Logic Ieee Transactions On Electron Devices. 64: 5209-5216. DOI: 10.1109/Ted.2017.2766570  0.46
2017 Reza AK, Hassan MK, Roy K. Büttiker Probe-Based Modeling of TDDB: Application to Dielectric Breakdown in MTJs and MOS Devices Ieee Transactions On Electron Devices. 64: 3337-3345. DOI: 10.1109/Ted.2017.2715164  0.36
2017 Jaiswal A, Roy S, Srinivasan G, Roy K. Proposal for a Leaky-Integrate-Fire Spiking Neuron Based on Magnetoelectric Switching of Ferromagnets Ieee Transactions On Electron Devices. 64: 1818-1824. DOI: 10.1109/Ted.2017.2671353  0.332
2017 Jaiswal A, Chakraborty I, Roy K. Energy-Efficient Memory Using Magneto-Electric Switching of Ferromagnets Ieee Magnetics Letters. 8: 1-5. DOI: 10.1109/Lmag.2017.2712685  0.415
2017 Azim ZA, Sharma A, Roy K. Buffered Spin-Torque Sensors for Minimizing Delay and Energy Consumption in Global Interconnects Ieee Magnetics Letters. 8: 1-5. DOI: 10.1109/Lmag.2016.2620427  0.411
2017 Sharma A, Roy K. Design Space Exploration of Hysteresis-Free HfZrO x -Based Negative Capacitance FETs Ieee Electron Device Letters. 38: 1165-1167. DOI: 10.1109/Led.2017.2714659  0.365
2017 Sengupta A, Roy K. Encoding Neural and Synaptic Functionalities in Electron Spin: A Pathway to Efficient Neuromorphic Computing Applied Physics Reviews. 4: 41105. DOI: 10.1063/1.5012763  0.373
2017 Shim Y, Jaiswal A, Roy K. Ising computation based combinatorial optimization using spin-Hall effect (SHE) induced stochastic magnetization reversal Journal of Applied Physics. 121: 193902. DOI: 10.1063/1.4983636  0.334
2017 Hassan MK, Roy K. Investigation of dependence between time-zero and time-dependent variability in high-κ NMOS transistors Microelectronics Reliability. 70: 22-31. DOI: 10.1016/J.Microrel.2017.01.009  0.423
2016 Srinivasan G, Sengupta A, Roy K. Magnetic Tunnel Junction Based Long-Term Short-Term Stochastic Synapse for a Spiking Neural Network with On-Chip STDP Learning. Scientific Reports. 6: 29545. PMID 27405788 DOI: 10.1038/Srep29545  0.332
2016 Sengupta A, Shim Y, Roy K. Proposal for an All-Spin Artificial Neural Network: Emulating Neural and Synaptic Functionalities Through Domain Wall Motion in Ferromagnets. Ieee Transactions On Biomedical Circuits and Systems. PMID 27214912 DOI: 10.1109/Tbcas.2016.2525823  0.385
2016 Bajaj S, Alam SK, Roy KS, Datta A, Nath S, Roychoudhury S. E2 Ubiquitin-conjugating Enzyme, UBE2C Gene, Is Reciprocally Regulated by Wild-type and Gain-of-Function Mutant p53. The Journal of Biological Chemistry. 291: 14231-47. PMID 27129209 DOI: 10.1074/jbc.M116.731398  0.455
2016 Markandeya HS, Roy K. Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2521869  0.381
2016 Sharmin S, Jaiswal A, Roy K. Modeling and Design Space Exploration for Bit-Cells Based on Voltage-Assisted Switching of Magnetic Tunnel Junctions Ieee Transactions On Electron Devices. 63: 3493-3500. DOI: 10.1109/Ted.2016.2587734  0.467
2016 Sengupta A, Parsa M, Han B, Roy K. Probabilistic Deep Spiking Neural Systems Enabled by Magnetic Tunnel Junction Ieee Transactions On Electron Devices. 63: 2963-2970. DOI: 10.1109/Ted.2016.2568762  0.386
2016 Cho WS, Roy K. Device-Circuit Cosimulation for Energy Efficiency in Sub-10-nm Gate Length Logic and Memory Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2016.2567385  0.443
2016 Ho CH, Kim SY, Panagopoulos GD, Roy K. Statistical TDDB Degradation in Memory Circuits: Bit-Cells to Arrays Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2016.2557279  0.826
2016 Sharma A, Akkala AG, Kulkarni JP, Roy K. Source-Underlapped GaSb-InAs TFETs With Applications to Gain Cell Embedded DRAMs Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2016.2555627  0.721
2016 Sharma A, Reza AK, Roy K. Proposal of an Intrinsic-Source Broken-Gap Tunnel FET to Reduce Band-Tail Effects on Subthreshold Swing: A Simulation Study Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2016.2553086  0.32
2016 Mungan ES, Lu C, Ho CH, Roy K. Effects of deposition process on poly-Si microscale energy harvesting systems: A simulation study Ieee Transactions On Electron Devices. 63: 1650-1657. DOI: 10.1109/Ted.2016.2535275  0.62
2016 Reza AK, Fong X, Azim ZA, Roy K. Modeling and Evaluation of Topological Insulator/ Ferromagnet Heterostructure-Based Memory Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2016.2520941  0.675
2016 Akkala AG, Venkatesan R, Raghunathan A, Roy K. Asymmetric Underlapped Sub-10-nm n-FinFETs for High-Speed and Low-Leakage 6T SRAMs Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2015.2512227  0.412
2016 Al Azim Z, Sengupta A, Sarwar SS, Roy K. Spin-torque sensors for energy efficient high-speed long interconnects Ieee Transactions On Electron Devices. 63: 800-808. DOI: 10.1109/Ted.2015.2507126  0.424
2016 Sengupta A, Roy K. A Vision for All-Spin Neural Networks: A Device to System Perspective Ieee Transactions On Circuits and Systems I-Regular Papers. 63: 2267-2277. DOI: 10.1109/Tcsi.2016.2615312  0.367
2016 Fong X, Kim Y, Yogendra K, Fan D, Sengupta A, Raghunathan A, Roy K. Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1-22. DOI: 10.1109/Tcad.2015.2481793  0.716
2016 Venkatesan R, Kozhikkottu VJ, Sharad M, Augustine C, Raychowdhury A, Roy K, Raghunathan A. Cache Design with Domain Wall Memory Ieee Transactions On Computers. 65: 1010-1024. DOI: 10.1109/Tc.2015.2506581  0.77
2016 Roy K, Jung B, Peroulis D, Raghunathan A. Integrated Systems in the More-Than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components Ieee Design and Test. 33: 56-65. DOI: 10.1109/Mdt.2011.49  0.421
2016 Seo Y, Kwon KW, Roy K. Area-Efficient SOT-MRAM With a Schottky Diode Ieee Electron Device Letters. 37: 982-985. DOI: 10.1109/Led.2016.2578959  0.452
2016 Fong X, Kim Y, Venkatesan R, Choday SH, Raghunathan A, Roy K. Spin-Transfer Torque Memories: Devices, Circuits, and Systems Proceedings of the Ieee. DOI: 10.1109/JPROC.2016.2521712  0.826
2016 Seo Y, Kwon KW, Fong X, Roy K. High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM Ieee Journal On Emerging and Selected Topics in Circuits and Systems. DOI: 10.1109/Jetcas.2016.2547701  0.716
2016 Jaiswal A, Fong X, Roy K. Comprehensive Scaling Analysis of Current Induced Switching in Magnetic Memories Based on In-Plane and Perpendicular Anisotropies Ieee Journal On Emerging and Selected Topics in Circuits and Systems. DOI: 10.1109/Jetcas.2016.2547698  0.73
2016 Narasimman G, Roy S, Fong X, Roy K, Chang CH, Basu A. A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks Proceedings - Ieee International Symposium On Circuits and Systems. 2016: 914-917. DOI: 10.1109/ISCAS.2016.7527390  0.683
2016 Sengupta A, Banerjee A, Roy K. Hybrid Spintronic-CMOS Spiking Neural Network With On-Chip Learning: Devices, Circuits and Systems Physical Review Applied. 6: 64003. DOI: 10.1103/Physrevapplied.6.064003  0.335
2015 Fan D, Sharad M, Sengupta A, Roy K. Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing. Ieee Transactions On Neural Networks and Learning Systems. PMID 26285225 DOI: 10.1109/Tnnls.2015.2462731  0.39
2015 Kumar A, Samanta S, Singh A, Roy M, Singh S, Basu S, Chehimi MM, Roy K, Ramgir NS, Debnath AK, Aswal DK, Gupta SK, Navneethan M, Hayakawa Y. Fast Response and High Sensitivity of ZnO Nanowires - Cobalt Phthalocyanine Heterojunction based H2S Sensor. Acs Applied Materials & Interfaces. PMID 26225901 DOI: 10.1021/acsami.5b03652  0.394
2015 Roy K, Ghosh S, Kumar B, Ball S. Characteristic OCT Pattern in Waldenstrom Macroglobulinemia. Optometry and Vision Science : Official Publication of the American Academy of Optometry. 92: e106-9. PMID 25871872 DOI: 10.1097/OPX.0000000000000585  0.458
2015 Ranjan A, Venkataramani S, Fong X, Roy K, Raghunathan A. Approximate storage for energy efficient spintronic memories Proceedings - Design Automation Conference. 2015. DOI: 10.1145/2744769.2744799  0.624
2015 Venkatesan R, Sharad M, Roy K, Raghunathan A. Energy-efficient all-spin cache hierarchy using shift-based writes and multilevel storage Acm Journal On Emerging Technologies in Computing Systems. 12. DOI: 10.1145/2723165  0.409
2015 Fong X, Venkatesan R, Lee D, Raghunathan A, Roy K. Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2439733  0.771
2015 Markandeya HS, Irazoqui PP, Roy K. Low-energy two-stage algorithm for high efficacy epileptic seizure detection Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 208-212. DOI: 10.1109/Tvlsi.2014.2302798  0.323
2015 Fan D, Maji S, Yogendra K, Sharad M, Roy K. Injection-Locked Spin Hall-Induced Coupled-Oscillators for Energy Efficient Associative Computing Ieee Transactions On Nanotechnology. 14: 1083-1093. DOI: 10.1109/Tnano.2015.2471092  0.311
2015 Kwon KW, Fong X, Wijesinghe P, Panda P, Roy K. High-Density and Robust STT-MRAM Array Through Device/Circuit/Architecture Interactions Ieee Transactions On Nanotechnology. 14: 1024-1034. DOI: 10.1109/Tnano.2015.2456510  0.722
2015 Fan D, Shim Y, Raghunathan A, Roy K. STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks Ieee Transactions On Nanotechnology. 14: 1013-1023. DOI: 10.1109/Tnano.2015.2437902  0.39
2015 Panagopoulos G, Ho C, Kim SY, Roy K. Physics-Based Compact Modeling of Successive Breakdown in Ultrathin Oxides Ieee Transactions On Nanotechnology. 14: 7-9. DOI: 10.1109/Tnano.2014.2366379  0.805
2015 Yogendra K, Fan D, Roy K. Coupled Spin Torque Nano Oscillators for Low Power Neural Computation Ieee Transactions On Magnetics. 51. DOI: 10.1109/Tmag.2015.2443042  0.324
2015 Sharad M, Fan D, Roy K. Energy-Efficient and Robust Associative Computing with Injection-Locked Dual-Pillar Spin-Torque Oscillators Ieee Transactions On Magnetics. 51. DOI: 10.1109/Tmag.2015.2394379  0.36
2015 Zhang L, Fong X, Chang CH, Kong ZH, Roy K. Highly reliable spin-transfer torque magnetic ram-based physical unclonable function with multi-response-bits per cell Ieee Transactions On Information Forensics and Security. 10: 1630-1642. DOI: 10.1109/Tifs.2015.2421481  0.694
2015 Seo Y, Fong X, Roy K. Domain wall coupling-based STT-MRAM for on-chip cache applications Ieee Transactions On Electron Devices. 62: 554-560. DOI: 10.1109/Ted.2014.2377751  0.733
2015 Kim Y, Fong X, Kwon KW, Chen MC, Roy K. Multilevel spin-orbit torque MRAMs Ieee Transactions On Electron Devices. 62: 561-568. DOI: 10.1109/Ted.2014.2377721  0.719
2015 Zhang L, Fong X, Chang CH, Kong ZH, Roy K. Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 1176-1187. DOI: 10.1109/Tcad.2015.2427251  0.695
2015 Pajouhi Z, Venkataramani S, Yogendra K, Raghunathan A, Roy K. Exploring Spin-Transfer-Torque Devices for Logic Applications Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 1441-1454. DOI: 10.1109/Tcad.2015.2413852  0.485
2015 Kim Y, Fong X, Roy K. Spin-Orbit-Torque-Based Spin-Dice: A True Random-Number Generator Ieee Magnetics Letters. 6: 1-4. DOI: 10.1109/Lmag.2015.2496548  0.669
2015 Chen M, Kim Y, Yogendra K, Roy K. Domino-Style Spin–Orbit Torque-Based Spin Logic Ieee Magnetics Letters. 6: 1-4. DOI: 10.1109/Lmag.2015.2483598  0.33
2015 Seo Y, Fong X, Kwon K, Roy K. Spin-Hall Magnetic Random-Access Memory With Dual Read/Write Ports for On-Chip Caches Ieee Magnetics Letters. 6: 1-4. DOI: 10.1109/Lmag.2015.2422260  0.715
2015 Cho WS, Roy K. The effects of direct source-to-drain tunneling and variation in the body thickness on (100) and (110) sub-10-nm Si double-gate transistors Ieee Electron Device Letters. 36: 427-429. DOI: 10.1109/Led.2015.2413785  0.314
2015 Roy K, Fan D, Fong X, Kim Y, Sharad M, Paul S, Chatterjee S, Bhunia S, Mukhopadhyay S. Exploring Spin Transfer Torque Devices for Unconventional Computing Ieee Journal On Emerging and Selected Topics in Circuits and Systems. DOI: 10.1109/Jetcas.2015.2405171  0.786
2015 Mukhopadhyay S, Bhunia S, Hunter HC, Roy K. Guest editorial computing in emerging technologies (second issue) Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 5: 1-4. DOI: 10.1109/Jetcas.2015.2403551  0.653
2015 Choday SH, Kwon KW, Roy K. Workload dependent evaluation of thin-film thermoelectric devices for on-chip cooling and energy harvesting Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2015: 535-541. DOI: 10.1109/ICCAD.2014.7001402  0.772
2015 Sengupta A, Choday SH, Kim Y, Roy K. Spin orbit torque based electronic neuron Applied Physics Letters. 106: 143701. DOI: 10.1063/1.4917011  0.766
2015 Sengupta A, Al Azim Z, Fong X, Roy K. Spin-orbit torque induced spike-timing dependent plasticity Applied Physics Letters. 106. DOI: 10.1063/1.4914111  0.685
2015 Ho C, Kim SY, Roy K. Ultra-thin dielectric breakdown in devices and circuits: A brief review Microelectronics Reliability. 55: 308-317. DOI: 10.1016/J.Microrel.2014.10.019  0.641
2015 Fong X, Choday SH, Roy K. Design and optimization of spin-transfer torque MRAMs More Than Moore Technologies For Next Generation Computer Design. 49-72. DOI: 10.1007/978-1-4939-2163-8_3  0.84
2014 Das T, Roy KS, Chakrabarti T, Mukhopadhyay S, Roychoudhury S. Withaferin A modulates the Spindle assembly checkpoint by degradation of Mad2-Cdc20 complex in colorectal cancer cell lines. Biochemical Pharmacology. 91: 31-9. PMID 24995417 DOI: 10.1016/j.bcp.2014.06.022  0.398
2014 Nayak A, Chandra G, Hwang I, Kim K, Hou X, Kim HO, Sahu PK, Roy KK, Yoo J, Lee Y, Cui M, Choi S, Moss SM, Phan K, Gao ZG, et al. Synthesis and anti-renal fibrosis activity of conformationally locked truncated 2-hexynyl-N(6)-substituted-(N)-methanocarba-nucleosides as A3 adenosine receptor antagonists and partial agonists. Journal of Medicinal Chemistry. 57: 1344-54. PMID 24456490 DOI: 10.1021/Jm4015313  0.372
2014 Botman F, Bol D, Legat J, Roy K. Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits Ieee Transactions On Very Large Scale Integration Systems. 22: 2561-2570. DOI: 10.1109/Tvlsi.2013.2297176  0.455
2014 Chippa VK, Mohapatra D, Roy K, Chakradhar ST, Raghunathan A. Scalable effort hardware design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 2004-2016. DOI: 10.1109/Tvlsi.2013.2276759  0.592
2014 Kwon KW, Choday SH, Kim Y, Roy K. AWARE (Asymmetric Write Architecture with REdundant Blocks): A high write speed STT-MRAM cache architecture Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 712-720. DOI: 10.1109/Tvlsi.2013.2256945  0.796
2014 Fong X, Kim Y, Choday SH, Roy K. Failure mitigation techniques for 1T-1MTJ spin-transfer torque MRAM bit-cells Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 384-395. DOI: 10.1109/Tvlsi.2013.2239671  0.826
2014 Lee D, Roy K. Energy-Delay Optimization of the STT MRAM Write Operation Under Process Variations Ieee Transactions On Nanotechnology. 13: 714-723. DOI: 10.1109/Tnano.2014.2317073  0.603
2014 Fan D, Sharad M, Roy K. Design and Synthesis of Ultralow Energy Spin-Memristor Threshold Logic Ieee Transactions On Nanotechnology. 13: 574-583. DOI: 10.1109/Tnano.2014.2312177  0.437
2014 Venkatesan R, Chippa VK, Augustine C, Roy K, Raghunathan A. Domain-Specific Many-core Computing using Spin-based Memory Ieee Transactions On Nanotechnology. 13: 881-894. DOI: 10.1109/Tnano.2014.2306958  0.654
2014 Sharad M, Fan D, Aitken K, Roy K. Energy-Efficient Non-Boolean Computing With Spin Neurons and Resistive Memory Ieee Transactions On Nanotechnology. 13: 23-34. DOI: 10.1109/Tnano.2013.2286424  0.45
2014 Fong X, Venkatesan R, Raghunathan A, Roy K. Non-Volatile Complementary Polarizer Spin-Transfer Torque On-Chip Caches: A Device/Circuit/Systems Perspective Ieee Transactions On Magnetics. 50. DOI: 10.1109/Tmag.2014.2326858  0.738
2014 Cho W, Gupta SK, Roy K. Device-Circuit Analysis of Double-Gate MOSFETs and Schottky-Barrier FETs: A Comparison Study for Sub-10-nm Technologies Ieee Transactions On Electron Devices. 61: 4025-4031. DOI: 10.1109/Ted.2014.2364791  0.577
2014 Hassan MK, Ho CH, Roy K. Stochastic modeling of positive bias temperature instability in high-metal gate nMOSFETs Ieee Transactions On Electron Devices. 61: 2243-2249. DOI: 10.1109/Ted.2014.2321064  0.611
2014 Kim SY, Ho C, Roy K. Statistical SBD Modeling and Characterization and Its Impact on SRAM Cells Ieee Transactions On Electron Devices. 61: 54-59. DOI: 10.1109/Ted.2013.2292060  0.621
2014 Sharma A, Goud AA, Roy K. GaSb-InAs n-TFET With Doped Source Underlap Exhibiting Low Subthreshold Swing at Sub-10-nm Gate-Lengths Ieee Electron Device Letters. 35: 1221-1223. DOI: 10.1109/Led.2014.2365413  0.364
2014 Azim ZA, Fong X, Ostler T, Chantrell R, Roy K. Laser Induced Magnetization Reversal for Detection in Optical Interconnects Ieee Electron Device Letters. 35: 1317-1319. DOI: 10.1109/Led.2014.2364232  0.691
2014 Choday SH, Gupta SK, Roy K. Write-optimized STT-MRAM bit-cells using asymmetrically doped transistors Ieee Electron Device Letters. 35: 1100-1102. DOI: 10.1109/Led.2014.2358998  0.831
2014 Ho CH, Hassan MK, Kim SY, Roy K. Analysis of stability degradation of SRAMs using a physics-based PBTI model Ieee Electron Device Letters. 35: 951-953. DOI: 10.1109/Led.2014.2340373  0.609
2014 Kwon KW, Choday SH, Kim Y, Fong X, Park SP, Roy K. SHE-NVFF: Spin hall effect-based nonvolatile flip-flop for power gating architecture Ieee Electron Device Letters. 35: 488-490. DOI: 10.1109/Led.2014.2304683  0.828
2014 Mukhopadhyay S, Bhunia S, Hunter HC, Roy K. Guest editorial computing in emerging technologies (First issue) Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 4: 377-379. DOI: 10.1109/JETCAS.2014.2361417  0.432
2014 Kim SY, Roy K. A Low-Cost Low-Noise Amplifier in Poly-Si TFT Technology Ieee\/Osa Journal of Display Technology. 10: 1110-1114. DOI: 10.1109/Jdt.2014.2351617  0.367
2014 Ho C, Lu C, Roy K. An Enhanced Voltage Programming Pixel Circuit for Compensating GB-Induced Variations in Poly-Si TFTs for AMOLED Displays Ieee\/Osa Journal of Display Technology. 10: 345-351. DOI: 10.1109/Jdt.2014.2301020  0.59
2014 Sharad M, Roy K. Spintronic switches for ultra low energy global interconnects Journal of Applied Physics. 115. DOI: 10.1063/1.4868699  0.4
2014 Moradi F, Panagopoulos G, Karakonstantis G, Farkhani H, Wisland DT, Madsen JK, Mahmoodi H, Roy K. Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology Microelectronics Journal. 45: 23-34. DOI: 10.1016/J.Mejo.2013.09.009  0.824
2013 Gupta SK, Roy K. (Invited) Spacer Thickness Optimization for FinFET-based Logic and Memories: A Device-Circuit Co-Design Approach Ecs Transactions. 50: 187-192. DOI: 10.1149/05004.0187ecst  0.53
2013 Chippa VK, Roy K, Chakradhar ST, Raghunathan A. Managing the quality vs. efficiency trade-off using dynamic effort scaling Transactions On Embedded Computing Systems. 12. DOI: 10.1145/2465787.2465792  0.331
2013 Mojumder NN, Fong X, Augustine C, Gupta SK, Choday SH, Roy K. Dual pillar spin-transfer torque MRAMs for low power applications Acm Journal On Emerging Technologies in Computing Systems. 9. DOI: 10.1145/2463585.2463590  0.831
2013 Lee D, Roy K. Area Efficient ROM-Embedded SRAM Cache Ieee Transactions On Very Large Scale Integration Systems. 21: 1583-1595. DOI: 10.1109/Tvlsi.2012.2217514  0.59
2013 Mojumder NN, Roy K, Abraham DW. Thermoelectric spin-transfer torque MRAM with fast bidirectional writing using magnonic current Ieee Transactions On Magnetics. 49: 483-488. DOI: 10.1109/Tmag.2012.2205400  0.77
2013 Gupta SK, Kulkarni JP, Roy K. Tri-mode independent gate finfet-based sram with pass-gate feedback: Technology-circuit co-design for enhanced cell stability Ieee Transactions On Electron Devices. 60: 3696-3704. DOI: 10.1109/Ted.2013.2283235  0.777
2013 Panagopoulos GD, Augustine C, Roy K. Physics-based SPICE-compatible compact model for simulating hybrid MTJ/CMOS circuits Ieee Transactions On Electron Devices. 60: 2808-2814. DOI: 10.1109/Ted.2013.2275082  0.822
2013 Ho C, Panagopoulos G, Roy K. A Self-Consistent Electrothermal Model for Analyzing NBTI Effect in p-Type Poly-Si Thin-Film Transistors Ieee Transactions On Electron Devices. 60: 288-294. DOI: 10.1109/Ted.2012.2228657  0.8
2013 Choday SH, Lundstrom MS, Roy K. Prospects of thin-film thermoelectric devices for hot-spot cooling and on-chip energy harvesting Ieee Transactions On Components, Packaging and Manufacturing Technology. 3: 2059-2067. DOI: 10.1109/Tcpmt.2013.2273873  0.752
2013 Gupta V, Mohapatra D, Raghunathan A, Roy K. Low-Power Digital Signal Processing Using Approximate Adders Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 124-137. DOI: 10.1109/Tcad.2012.2217962  0.632
2013 Narasimhan S, Du D, Chakraborty RS, Paul S, Wolff FG, Papachristou CA, Roy K, Bhunia S. Hardware trojan detection by multiple-parameter side-channel analysis Ieee Transactions On Computers. 62: 2183-2195. DOI: 10.1109/Tc.2012.200  0.598
2013 Ho CH, Panagopoulos GD, Kim SY, Kim Y, Lee D, Roy K. A physics-based statistical model for reliability of STT-MRAM considering oxide variability International Conference On Simulation of Semiconductor Processes and Devices, Sispad. 29-32. DOI: 10.1109/SISPAD.2013.6650566  0.751
2013 Choday SH, Lu C, Raghunathan V, Roy K. On-chip energy harvesting using thin-film thermoelectric materials Annual Ieee Semiconductor Thermal Measurement and Management Symposium. 99-104. DOI: 10.1109/SEMI-THERM.2013.6526812  0.711
2013 Sharad M, Venkatesan R, Fong X, Raghunathan A, Roy K. Reading spin-torque memory with spin-torque sensors Proceedings of the 2013 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2013. 40-41. DOI: 10.1109/NanoArch.2013.6623040  0.681
2013 Park SP, Kang K, Roy K. Reliability Implications of NBTI in Digital Integrated Circuits Ieee Design & Test of Computers. 1-1. DOI: 10.1109/Mdt.2009.133  0.425
2013 Gupta SK, Roy K. Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs Ieee Design & Test. 30: 29-39. DOI: 10.1109/Mdat.2013.2266394  0.592
2013 Kim Y, Choday SH, Roy K. DSH-MRAM: Differential spin hall MRAM for on-chip memories Ieee Electron Device Letters. 34: 1259-1261. DOI: 10.1109/Led.2013.2279153  0.788
2013 Lee D, Fong X, Roy K. R-MRAM: A ROM-Embedded STT MRAM Cache Ieee Electron Device Letters. 34: 1256-1258. DOI: 10.1109/Led.2013.2279137  0.753
2013 Sharad M, Roy K. Spintronic Switches for Ultralow Energy On-Chip and Interchip Current-Mode Interconnects Ieee Electron Device Letters. 34: 1068-1070. DOI: 10.1109/Led.2013.2268152  0.427
2013 Fong X, Roy K. Correction to "Complimentary polarizers STT-MRAM (CPSTT) for on-chip caches" [Feb 13 232-234] Ieee Electron Device Letters. 34: 562-562. DOI: 10.1109/Led.2013.2249611  0.669
2013 Fong X, Roy K. Complimentary Polarizers STT-MRAM (CPSTT) for On-Chip Caches Ieee Electron Device Letters. 34: 232-234. DOI: 10.1109/Led.2012.2234079  0.737
2013 Sharad M, Venkatesan R, Fong X, Raghunathan A, Roy K. Energy-efficient MRAM access scheme using hybrid circuits based on spin-torque sensors Ieee Sensors 2013 - Proceedings. DOI: 10.1109/ICSENS.2013.6688182  0.713
2013 Ho CH, Panagopoulos GD, Kim SY, Kim Y, Lee D, Roy K. A physical model to predict STT-MRAM performance degradation induced by TDDB Device Research Conference - Conference Digest, Drc. 59-60. DOI: 10.1109/DRC.2013.6633792  0.714
2013 Goud AA, Gupta SK, Choday SH, Roy K. Atomistic tight-binding based evaluation of impact of gate underlap on source to drain tunneling in 5 nm gate length Si FinFETs Device Research Conference - Conference Digest, Drc. 51-52. DOI: 10.1109/DRC.2013.6633788  0.767
2013 Chippa VK, Jayakumar H, Mohapatra D, Roy K, Raghunathan A. Energy-efficient recognition and mining processor using scalable effort design Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2013.6658433  0.528
2013 Sharad M, Fan D, Roy K. Spin-neurons: A possible path to energy-efficient neuromorphic computers Journal of Applied Physics. 114: 234906. DOI: 10.1063/1.4838096  0.389
2013 Sharad M, Yogendra K, Roy K. Dual pillar spin torque nano-oscillator Applied Physics Letters. 103: 152403. DOI: 10.1063/1.4824419  0.316
2013 Choday SH, Roy K. Sensitivity analysis and optimization of thin-film thermoelectric coolers Journal of Applied Physics. 113. DOI: 10.1063/1.4807282  0.744
2012 Bansal A, Prasad M, Roy K, Kukreti S. A short GC-rich palindrome of human mannose receptor gene coding region displays a conformational switch. Biopolymers. 97: 950-62. PMID 22987586 DOI: 10.1002/bip.22111  0.395
2012 Venkatesan R, Kozhikkottu V, Augustine C, Raychowdhury A, Roy K, Raghunathan A. TapeCache: A high density, energy efficient cache based on domain wall memory Proceedings of the International Symposium On Low Power Electronics and Design. 185-190. DOI: 10.1145/2333660.2333707  0.732
2012 Sharad M, Augustine C, Panagopoulos G, Roy K. Cognitive computing with spin-based neural networks Proceedings - Design Automation Conference. 1262-1263. DOI: 10.1145/2228360.2228594  0.604
2012 Park SP, Gupta S, Mojumder N, Raghunathan A, Roy K. Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture Proceedings - Design Automation Conference. 492-497. DOI: 10.1145/2228360.2228447  0.816
2012 Sharad M, Gupta SK, Raghunathan S, Irazoqui PP, Roy K. Low-power architecture for epileptic seizure detection based on reduced complexity DWT Acm Journal On Emerging Technologies in Computing Systems. 8. DOI: 10.1145/2180878.2180882  0.564
2012 Lee J, Bhagavatula S, Bhunia S, Roy K, Jung B. Self-healing design in deep scaled CMOS technologies Journal of Circuits, Systems and Computers. 21. DOI: 10.1142/S0218126612400117  0.627
2012 Griffin WP, Raghunathan A, Roy K. CLIP: Circuit level IC protection through direct injection of process variations Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 791-803. DOI: 10.1109/Tvlsi.2011.2135868  0.413
2012 Kulkarni JP, Roy K. Ultralow-voltage process-variation-tolerant schmitt-trigger-based SRAM design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 319-332. DOI: 10.1109/Tvlsi.2010.2100834  0.725
2012 Park SP, Lee D, Roy K. Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code Ieee Transactions On Very Large Scale Integration Systems. 20: 248-256. DOI: 10.1109/Tvlsi.2010.2095435  0.553
2012 Sharad M, Augustine C, Panagopoulos G, Roy K. Spin-based neuron model with domain-wall magnets as synapse Ieee Transactions On Nanotechnology. 11: 843-853. DOI: 10.1109/Tnano.2012.2202125  0.821
2012 Fong X, Choday SH, Roy K. Bit-cell level optimization for non-volatile memories using magnetic tunnel junctions and spin-transfer torque switching Ieee Transactions On Nanotechnology. 11: 172-181. DOI: 10.1109/Tnano.2011.2169456  0.824
2012 Mojumder NN, Abraham DW, Roy K, Worledge DC. Magnonic spin-transfer torque MRAM with low power, high speed, and error-free switching Ieee Transactions On Magnetics. 48: 2016-2024. DOI: 10.1109/Tmag.2011.2179982  0.78
2012 Gupta SK, Kulkarni JP, Datta S, Roy K. Heterojunction intra-band tunnel FETs for low-voltage SRAMs Ieee Transactions On Electron Devices. 59: 3533-3542. DOI: 10.1109/Ted.2012.2221127  0.729
2012 Mojumder NN, Roy K. Proposal for switching current reduction using reference layer with tilted magnetic anisotropy in magnetic tunnel junctions for spin-transfer torque (STT) MRAM Ieee Transactions On Electron Devices. 59: 3054-3060. DOI: 10.1109/Ted.2012.2210226  0.758
2012 Gupta SK, Panagopoulos G, Roy K. NBTI in n-Type SOI Access FinFETs in SRAMs and Its Impact on Cell Stability and Performance Ieee Transactions On Electron Devices. 59: 2603-2609. DOI: 10.1109/Ted.2012.2209182  0.783
2012 Ho C, Panagopoulos G, Roy K. A Physical Model for Grain-Boundary-Induced Threshold Voltage Variation in Polysilicon Thin-Film Transistors Ieee Transactions On Electron Devices. 59: 2396-2402. DOI: 10.1109/Ted.2012.2205387  0.807
2012 Kim SY, Loke W, Jung B, Roy K. High-Frequency Modeling of Poly-Si Thin-Film Transistors for Low-Cost RF Applications Ieee Transactions On Electron Devices. 59: 2296-2301. DOI: 10.1109/Ted.2012.2202238  0.329
2012 Lee D, Roy K. Viterbi-Based Efficient Test Data Compression Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 610-619. DOI: 10.1109/Tcad.2011.2172609  0.564
2012 Augustine C, Mojumder N, Fong X, Choday H, Park SP, Roy K. STT-MRAMs for future universal memories: Perspective and prospective 2012 28th International Conference On Microelectronics - Proceedings, Miel 2012. 349-355. DOI: 10.1109/MIEL.2012.6222872  0.834
2012 Yadid-Pecht O, Fish A, Roy K. Editorial - Special Issue on Low-Power Arrays Ieee Sensors Journal. 12: 717-719. DOI: 10.1109/Jsen.2011.2166610  0.391
2012 Augustine C, Mojumder NN, Fong X, Choday SH, Park SP, Roy K. Spin-transfer torque MRAMs for low power memories: Perspective and prospective Ieee Sensors Journal. 12: 756-766. DOI: 10.1109/Jsen.2011.2124453  0.829
2012 Sharad M, Augustine C, Panagopoulos G, Roy K. Spin based neuron-synapse module for ultra low power programmable computational networks Proceedings of the International Joint Conference On Neural Networks. DOI: 10.1109/IJCNN.2012.6252609  0.625
2012 Sharad M, Augustine C, Roy K. Boolean and non-Boolean computation with spin devices Technical Digest - International Electron Devices Meeting, Iedm. 11.6.1-11.6.4. DOI: 10.1109/IEDM.2012.6479026  0.628
2012 Gupta SK, Kulkarni JP, Datta S, Roy K. Dopant straggle-free heterojunction intra-band tunnel (HIBT) FETs with low drain-induced barrier lowering/thinning (DIBL/T) and reduced variation in off current Device Research Conference - Conference Digest, Drc. 55-56. DOI: 10.1109/DRC.2012.6257027  0.727
2012 Panagopoulos G, Augustine C, Fong X, Roy K. Exploring variability and reliability of multi-level STT-MRAM cells Device Research Conference - Conference Digest, Drc. 139-140. DOI: 10.1109/DRC.2012.6257003  0.767
2012 Sharad M, Panagopoulos G, Augustine C, Roy K. NLSTT-MRAM: Robust spin transfer torque MRAM using non-local spin injection for write Device Research Conference - Conference Digest, Drc. 97-98. DOI: 10.1109/DRC.2012.6256957  0.612
2012 Karakonstantis G, Mohapatra D, Roy K. Logic and memory design based on unequal error protection for voltage-scalable, robust and adaptive DSP systems Journal of Signal Processing Systems. 68: 415-431. DOI: 10.1007/s11265-011-0631-9  0.68
2011 Bhunia SS, Roy KK, Saxena AK. Profiling the structural determinants for the selectivity of representative factor-Xa and thrombin inhibitors using combined ligand-based and structure-based approaches. Journal of Chemical Information and Modeling. 51: 1966-85. PMID 21761917 DOI: 10.1021/Ci200185Q  0.423
2011 Roy KK, Bhunia SS, Saxena AK. CoMFA, CoMSIA, and docking studies on thiolactone-class of potent anti-malarials: identification of essential structural features modulating anti-malarial activity. Chemical Biology & Drug Design. 78: 483-93. PMID 21672165 DOI: 10.1111/J.1747-0285.2011.01158.X  0.423
2011 Lee C, Srisungsitthisunti P, Park S, Kim S, Xu X, Roy K, Janes DB, Zhou C, Ju S, Qi M. Control of current saturation and threshold voltage shift in indium oxide nanowire transistors with femtosecond laser annealing. Acs Nano. 5: 1095-101. PMID 21222453 DOI: 10.1021/Nn102723W  0.397
2011 Raghunathan S, Gupta SK, Markandeya HS, Irazoqui PP, Roy K. Ultra low-power algorithm design for implantable devices: Application to epilepsy prostheses Journal of Low Power Electronics and Applications. 1: 175-203. DOI: 10.3390/Jlpea1010175  0.524
2011 Kulkarni JP, Goel A, Ndai P, Roy K. A read-disturb-free, differential sensing 1R/1W Port, 8T bitcell array Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1727-1730. DOI: 10.1109/Tvlsi.2010.2055169  0.807
2011 Chang IJ, Kim J, Kim K, Roy K. Robust Level Converter for Sub-Threshold/Super-Threshold Operation:100 mV to 2.5 V Ieee Transactions On Very Large Scale Integration Systems. 19: 1429-1437. DOI: 10.1109/Tvlsi.2010.2051240  0.811
2011 Ghosh S, Roy K. Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking Ieee Transactions On Very Large Scale Integration Systems. 19: 1504-1507. DOI: 10.1109/Tvlsi.2010.2051169  0.606
2011 Augustine C, Fong X, Behin-Aein B, Roy K. Ultra-low power nanomagnet-based computing: A system-level perspective Ieee Transactions On Nanotechnology. 10: 778-788. DOI: 10.1109/Tnano.2010.2079941  0.814
2011 Augustine C, Raychowdhury A, Somasekhar D, Tschanz J, De V, Roy K. Design space exploration of typical STT MTJ stacks in memory arrays in the presence of variability and disturbances Ieee Transactions On Electron Devices. 58: 4333-4343. DOI: 10.1109/Ted.2011.2169962  0.756
2011 Moradi F, Gupta SK, Panagopoulos G, Wisland DT, Mahmoodi H, Roy K. Asymmetrically Doped FinFETs for Low-Power Robust SRAMs Ieee Transactions On Electron Devices. 58: 4241-4249. DOI: 10.1109/Ted.2011.2169678  0.809
2011 Gupta SK, Park SP, Roy K. Tri-Mode Independent-Gate FinFETs for Dynamic Voltage/Frequency Scalable 6T SRAMs Ieee Transactions On Electron Devices. 58: 3837-3846. DOI: 10.1109/Ted.2011.2166117  0.611
2011 Panagopoulos GD, Roy K. A three-dimensional physical model for Vth variations considering the combined effect of NBTI and RDF Ieee Transactions On Electron Devices. 58: 2337-2346. DOI: 10.1109/Ted.2011.2148720  0.764
2011 Kim SY, Baytok S, Roy K. Thin-BOX Poly-Si Thin-Film Transistors for CMOS-Compatible Analog Operations Ieee Transactions On Electron Devices. 58: 1687-1695. DOI: 10.1109/Ted.2011.2127480  0.364
2011 Mojumder NN, Gupta SK, Choday SH, Nikonov DE, Roy K. A three-terminal dual-pillar STT-MRAM for high-performance robust memory applications Ieee Transactions On Electron Devices. 58: 1508-1516. DOI: 10.1109/Ted.2011.2116024  0.823
2011 Panagopoulos G, Roy K. A Physics-Based Three-Dimensional Analytical Model for RDF-Induced Threshold Voltage Variations Ieee Transactions On Electron Devices. 58: 392-403. DOI: 10.1109/Ted.2010.2093140  0.784
2011 Goel A, Gupta SK, Roy K. Asymmetric Drain Spacer Extension (ADSE) FinFETs for Low-Power and Robust SRAMs Ieee Transactions On Electron Devices. 58: 296-308. DOI: 10.1109/Ted.2010.2090421  0.695
2011 Chang IJ, Mohapatra D, Roy K. A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications Ieee Transactions On Circuits and Systems For Video Technology. 21: 101-112. DOI: 10.1109/Tcsvt.2011.2105550  0.793
2011 Fong X, Gupta SK, Mojumder NN, Choday SH, Augustine C, Roy K. KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells International Conference On Simulation of Semiconductor Processes and Devices, Sispad. 51-54. DOI: 10.1109/SISPAD.2011.6035047  0.808
2011 Augustine C, Panagopoulos G, Behin-Aein B, Srinivasan S, Sarkar A, Roy K. Low-power functionality enhanced computation architecture using spin-based devices Proceedings of the 2011 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2011. 129-136. DOI: 10.1109/NANOARCH.2011.5941494  0.602
2011 Venkatesan R, Chippa VK, Augustine C, Roy K, Raghunathan A. Energy efficient many-core processor for recognition and mining using spin-based memory Proceedings of the 2011 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2011. 122-128. DOI: 10.1109/NANOARCH.2011.5941493  0.609
2011 Macii E, Narayanan V, Roy K. Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue) Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 205-207. DOI: 10.1109/Jetcas.2011.2162865  0.391
2011 Lu C, Raghunathan V, Roy K. Efficient design of micro-scale energy harvesting systems Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 254-266. DOI: 10.1109/Jetcas.2011.2162161  0.352
2011 Karakonstantis G, Chatterjee A, Roy K. Containing the nanometer "pandora-box": Cross-layer design techniques for variation aware low power systems Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 19-29. DOI: 10.1109/Jetcas.2011.2135590  0.745
2011 Alam MA, Roy K, Augustine C. Reliability- and Process-variation aware design of integrated circuits - A broader perspective Ieee International Reliability Physics Symposium Proceedings. 4A.1.1-4A.1.11. DOI: 10.1109/IRPS.2011.5784500  0.64
2011 Gupta SK, Choday SH, Roy K. Exploration of device-circuit interactions in FinFET-based memories for sub-15nm technologies using a mixed mode quantum simulation framework: Atoms to systems Technical Digest - International Electron Devices Meeting, Iedm. 32.5.1-32.5.4. DOI: 10.1109/IEDM.2011.6131659  0.806
2011 Augustine C, Raychowdhury A, Behin-Aein B, Srinivasan S, Tschanz J, De VK, Roy K. Numerical analysis of domain wall propagation for dense memory arrays Technical Digest - International Electron Devices Meeting, Iedm. 17.6.1-17.6.4. DOI: 10.1109/IEDM.2011.6131575  0.687
2011 Moradi F, Panagopoulos G, Karakonstantis G, Wisland D, Mahmoodi H, Madsen JK, Roy K. Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 326-331. DOI: 10.1109/ICCD.2011.6081419  0.718
2011 Raychowdhury A, Augustine C, Somasekhar D, Tschanz J, Roy K, De V. Numerical analysis of a novel MTJ stack for high readability and writability European Solid-State Device Research Conference. 347-350. DOI: 10.1109/ESSDERC.2011.6044163  0.713
2011 Karakonstantis G, Roy K. Voltage over-scaling: A cross-layer design perspective for energy efficient systems 2011 20th European Conference On Circuit Theory and Design, Ecctd 2011. 548-551. DOI: 10.1109/ECCTD.2011.6043592  0.723
2011 Mojumder NN, Gupta SK, Roy K. Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations Device Research Conference - Conference Digest, Drc. 67-68. DOI: 10.1109/DRC.2011.5994466  0.797
2011 Panagopoulos G, Augustine C, Roy K. Modeling of dielectric breakdown-induced time-dependent STT-MRAM performance degradation Device Research Conference - Conference Digest, Drc. 125-126. DOI: 10.1109/DRC.2011.5994447  0.615
2011 Goel A, Ghosh S, Meterelliyoz M, Parkhurst J, Roy K. Integrated design & test: Conquering the conflicting requirements of low-power, variation-tolerance and test cost Proceedings of the Asian Test Symposium. 486-491. DOI: 10.1109/ATS.2011.100  0.77
2011 Karakonstantis G, Roy K. Low-power and variation-tolerant application-specific system design Low-Power Variation-Tolerant Design in Nanometer Silicon. 249-292. DOI: 10.1007/978-1-4419-7418-1_8  0.713
2010 Raghunathan S, Gupta SK, Markandeya HS, Roy K, Irazoqui PP. A hardware-algorithm co-design approach to optimize seizure detection algorithms for implantable applications. Journal of Neuroscience Methods. 193: 106-17. PMID 20713084 DOI: 10.1016/J.Jneumeth.2010.08.008  0.498
2010 Markandeya H, Karakonstantis G, Raghunathan S, Irazoqui P, Roy K. Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection Proceedings of the International Symposium On Low Power Electronics and Design. 301-306. DOI: 10.1145/1840845.1840907  0.641
2010 Karakonstantis G, Panagopoulos G, Roy K. HERQULES: System level cross-layer design exploration for efficient energy-quality trade-offs Proceedings of the International Symposium On Low Power Electronics and Design. 117-122. DOI: 10.1145/1840845.1840871  0.628
2010 Gao Y, Augustine C, Nikonov DE, Roy K, Lundstrom MS. Realistic spin-FET performance assessment for reconfigurable logic circuits Digest of Technical Papers - Symposium On Vlsi Technology. 117-118. DOI: 10.1109/VLSIT.2010.5556193  0.652
2010 Mojumder NN, Augustine C, Roy K. Self-consistent transport-magnetic simulation and benchmarking of hybrid spin-torque driven Magnetic Tunnel Junctions (MTJs) Biennial University/Government/Industry Microelectronics Symposium - Proceedings. DOI: 10.1109/UGIM.2010.5508921  0.788
2010 Li J, Ndai P, Goel A, Salahuddin S, Roy K. Design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1710-1723. DOI: 10.1109/Tvlsi.2009.2027907  0.834
2010 Chen Y, Li H, Koh C, Sun G, Li J, Xie Y, Roy K. Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance Ieee Transactions On Very Large Scale Integration Systems. 18: 1621-1624. DOI: 10.1109/Tvlsi.2009.2026280  0.534
2010 Karakonstantis G, Banerjee N, Roy K. Process-variation resilient and voltage-scalable dct architecture for robust low-power computing Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1461-1470. DOI: 10.1109/Tvlsi.2009.2025279  0.79
2010 Ndai P, Goel A, Roy K. A scalable circuit-architecture co-design to improve memory yield for high-performance processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1209-1219. DOI: 10.1109/Tvlsi.2009.2022628  0.825
2010 Ghosh S, Mohapatra D, Karakonstantis G, Roy K. Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1301-1309. DOI: 10.1109/Tvlsi.2009.2022531  0.819
2010 Park J, Choi JH, Roy K. Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 787-793. DOI: 10.1109/Tvlsi.2009.2016839  0.513
2010 Hwang ME, Roy K. ABRM: Adaptive β-ratio modulation for process-tolerant ultradynamic voltage scaling Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 281-290. DOI: 10.1109/Tvlsi.2008.2010767  0.629
2010 Kang K, Park SP, Kim K, Roy K. On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures Ieee Transactions On Very Large Scale Integration Systems. 18: 270-280. DOI: 10.1109/Tvlsi.2008.2010399  0.454
2010 Mojumder NN, Mukhopadhyay S, Kim JJ, Chuang CT, Roy K. Self-repairing SRAM using on-chip detection and compensation Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 75-84. DOI: 10.1109/Tvlsi.2008.2008808  0.809
2010 Ndai P, Rafique N, Thottethodi M, Ghosh S, Bhunia S, Roy K. Trifecta: A nonspeculative scheme to exploit common, data-dependent subcritical paths Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 53-65. DOI: 10.1109/Tvlsi.2008.2007491  0.798
2010 Kulkarni JP, Augustine C, Jung B, Roy K. Nano spiral inductors for low-power digital spintronic circuits Ieee Transactions On Magnetics. 46: 1898-1901. DOI: 10.1109/Tmag.2010.2046020  0.807
2010 Meterelliyoz M, Song P, Stellari F, Kulkarni JP, Roy K. Characterization of random process variations using ultralow-power, high-sensitivity, bias-free sub-threshold process sensor Ieee Transactions On Circuits and Systems I: Regular Papers. 57: 1838-1847. DOI: 10.1109/Tcsi.2009.2037449  0.806
2010 Meterelliyoz M, Kulkarni JP, Roy K. Analysis of SRAM and eDRAM cache memories under spatial temperature variations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 2-13. DOI: 10.1109/Tcad.2009.2035535  0.802
2010 Choi SH, Kang K, Dartu F, Roy K. Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 497-501. DOI: 10.1109/Tcad.2009.2035482  0.349
2010 Chang IJ, Park SP, Roy K. Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation Ieee Journal of Solid-State Circuits. 45: 401-410. DOI: 10.1109/Jssc.2009.2036764  0.748
2010 Gupta SK, Raychowdhury A, Roy K. Digital computation in subthreshold region for ultralow-power operation: A device-circuit-architecture codesign perspective Proceedings of the Ieee. 98: 160-190. DOI: 10.1109/JPROC.2009.2035060  0.734
2010 Meterelliyoz M, Goel A, Kulkarni JP, Roy K. Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 53: 186-187. DOI: 10.1109/ISSCC.2010.5433991  0.825
2010 Karakonstantis G, Augustine C, Roy K. A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique Proceedings of the 2010 Ieee 16th International On-Line Testing Symposium, Iolts 2010. 3-8. DOI: 10.1109/IOLTS.2010.5560240  0.792
2010 Augustine C, Raychowdhury A, Somasekhar D, Tschanz J, Roy K, De VK. Numerical analysis of typical STT-MTJ stacks for 1T-1R memory arrays Technical Digest - International Electron Devices Meeting, Iedm. 22.7.1-22.7.4. DOI: 10.1109/IEDM.2010.5703416  0.709
2010 Augustine C, Fong X, Roy K. Dual ferroelectric capacitor architecture and its application to TAG RAM 2010 Ieee International Conference On Integrated Circuit Design and Technology, Icicdt 2010. 24-28. DOI: 10.1109/ICICDT.2010.5510750  0.786
2010 Gupta V, Karakonstantis G, Mohapatra D, Roy K. VEDA: Variation-aware energy-efficient discrete Wavelet Transform architecture Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 260-265. DOI: 10.1109/ICCD.2010.5647753  0.683
2010 Mojumder NN, Augustine C, Nikonov DE, Roy K. Spin torques estimation and magnetization dynamics in dual barrier resonant tunneling penta-layer magnetic tunnel junctions Device Research Conference - Conference Digest, Drc. 93-94. DOI: 10.1109/DRC.2010.5551855  0.789
2010 Moradi F, Augustine C, Goel A, Karakonstantis G, Cao TV, Wisland D, Mahmoodi H, Roy K. Data-dependant sense-amplifier flip-flop for low power applications Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2010.5617468  0.811
2010 Mojumder NN, Augustine C, Nikonov DE, Roy K. Effect of quantum confinement on spin transport and magnetization dynamics in dual barrier spin transfer torque magnetic tunnel junctions Journal of Applied Physics. 108. DOI: 10.1063/1.3503882  0.792
2010 Chang I, Park J, Kang K, Roy K. Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling Iet Circuits, Devices & Systems. 4: 469. DOI: 10.1049/Iet-Cds.2010.0137  0.771
2010 Kulkarni JP, Roy K. Technology/circuit co-design for III-V FETs Fundamentals of Iii-V Semiconductor Mosfets. 423-441. DOI: 10.1007/978-1-4419-1547-4_14  0.697
2009 Raghunathan S, Gupta SK, Ward MP, Worth RM, Roy K, Irazoqui PP. The design and hardware implementation of a low-power real-time seizure detection algorithm. Journal of Neural Engineering. 6: 056005. PMID 19717893 DOI: 10.1088/1741-2560/6/5/056005  0.55
2009 Mohapatra D, Karakonstantis G, Roy K. Significance driven computation: A voltage-scalable, variation-aware, quality-tuning motion estimator Proceedings of the International Symposium On Low Power Electronics and Design. 195-200. DOI: 10.1145/1594233.1594282  0.637
2009 Mahmoodi H, Tirumalashetty V, Cooke M, Roy K. Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating Ieee Transactions On Very Large Scale Integration Systems. 17: 33-44. DOI: 10.1109/Tvlsi.2008.2008453  0.389
2009 Chen Y, Li H, Roy K, Koh CK. Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 1749-1752. DOI: 10.1109/Tvlsi.2008.2007843  0.557
2009 Mojumder NN, Roy K. Band-to-band tunneling ballistic nanowire FET: Circuit-compatible device modeling and design of ultra-low-power digital circuits and memories Ieee Transactions On Electron Devices. 56: 2193-2201. DOI: 10.1109/Ted.2009.2028394  0.81
2009 Raychowdhury A, De VK, Kurtin J, Borkar SY, Roy K, Keshavarzi A. Variation tolerance in a multichannel carbon-nanotube transistor for high-speed digital circuits Ieee Transactions On Electron Devices. 56: 383-392. DOI: 10.1109/Ted.2008.2010604  0.711
2009 Hwang ME, Jung SO, Roy K. Slope interconnect effort: Gate-interconnect interdependent delay modeling for early CMOS circuit simulation Ieee Transactions On Circuits and Systems I: Regular Papers. 56: 1428-1441. DOI: 10.1109/Tcsi.2008.2006217  0.604
2009 Banerjee N, Karakonstantis G, Choi JH, Chakrabarti C, Roy K. Design methodology for low power and arametric robustness through output-quality modulation: Application to color-interpolation filtering Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1127-1137. DOI: 10.1109/Tcad.2009.2022197  0.786
2009 Li J, Kang K, Roy K. Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 46-59. DOI: 10.1109/Tcad.2008.2009149  0.447
2009 Choi JH, Banerjee N, Roy K. Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 87-97. DOI: 10.1109/Tcad.2008.2009135  0.581
2009 Karakonstantis G, Mohapatra D, Roy K. System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 133-138. DOI: 10.1109/SIPS.2009.5336238  0.637
2009 Park SP, Kang K, Roy K. Reliability Implications of Bias-Temperature Instability in Digital ICs Ieee Design & Test of Computers. 26: 8-17. DOI: 10.1109/Mdt.2009.154  0.402
2009 Chang IJ, Kim J, Park SP, Roy K. A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS Ieee Journal of Solid-State Circuits. 44: 650-658. DOI: 10.1109/Jssc.2008.2011972  0.806
2009 Augustine C, Raychowdhury A, Gao Y, Lundstrom M, Roy K. PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 80-85. DOI: 10.1109/ISQED.2009.4810273  0.742
2009 Goel A, Ndai P, Kulkarni JP, Roy K. REad/access-preferred (REAP) SRAM - Architecture-aware bit cell design for improved yield and lower V MIN Proceedings of the Custom Integrated Circuits Conference. 503-506. DOI: 10.1109/CICC.2009.5280794  0.808
2009 Augustine C, Behin-Aein B, Fong X, Roy K. A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 847-852. DOI: 10.1109/ASPDAC.2009.4796586  0.8
2009 Li J, Ndai P, Goel A, Liu H, Roy K. An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 841-846. DOI: 10.1109/ASPDAC.2009.4796585  0.83
2009 Meterelliyoz M, Roy K. Design for burn-in test: A technique for burn-in thermal stability under die-to-die parameter variations Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 787-792. DOI: 10.1109/ASPDAC.2009.4796576  0.735
2009 Gupta SK, Raychowdhury A, Roy K. Compact models considering incomplete voltage swing in complementary metal oxide semiconductor circuits at ultralow voltages: A circuit perspective on limits of switching energy Journal of Applied Physics. 105. DOI: 10.1063/1.3123763  0.716
2009 Roy K, Kulkarni JP, Gupta SK. Device/circuit interactions at 22nm technology node Proceedings - Design Automation Conference. 97-102.  0.748
2008 Cao Q, Kim HS, Pimparkar N, Kulkarni JP, Wang C, Shim M, Roy K, Alam MA, Rogers JA. Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates. Nature. 454: 495-500. PMID 18650920 DOI: 10.1038/nature07110  0.751
2008 Kawasaki Y, Xu ZZ, Wang X, Park JY, Zhuang ZY, Tan PH, Gao YJ, Roy K, Corfas G, Lo EH, Ji RR. Distinct roles of matrix metalloproteases in the early- and late-phase development of neuropathic pain. Nature Medicine. 14: 331-6. PMID 18264108 DOI: 10.1038/nm1723  0.32
2008 Ghosh S, Choi JH, Ndai P, Roy K. O2C: Occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors Proceedings of the International Symposium On Low Power Electronics and Design. 189-192. DOI: 10.1145/1393921.1393971  0.756
2008 Meterelliyoz M, Kulkarni JP, Roy K. Thermal analysis of 8-T SRAM for nano-scaled technologies Proceedings of the International Symposium On Low Power Electronics and Design. 123-128. DOI: 10.1145/1393921.1393953  0.801
2008 Li J, Bansal A, Ghosh S, Roy K. An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs Acm Journal On Emerging Technologies in Computing Systems. 4: 13. DOI: 10.1145/1389089.1389093  0.619
2008 Mojumder NN, Mukhopadhyay S, Kim JJ, Chuang CT, Roy K. Design and analysis of a self-repairing SRAM with on-chip monitor and compensation circuitry Proceedings of the Ieee Vlsi Test Symposium. 101-106. DOI: 10.1109/VTS.2008.26  0.758
2008 Datta A, Bhunia S, Choi JH, Mukhopadhyay S, Roy K. Profit Aware Circuit Design Under Process Variations Considering Speed Binning Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 806-815. DOI: 10.1109/Tvlsi.2008.2000364  0.758
2008 Coker A, Taylor V, Bhaduri D, Shukla S, Raychowdhury A, Roy K. Multijunction fault-tolerance architecture for nanoscale crossbar memories Ieee Transactions On Nanotechnology. 7: 202-208. DOI: 10.1109/Tnano.2007.911319  0.572
2008 Bansal A, Kim J, Kim K, Mukhopadhyay S, Chuang C, Roy K. Optimal Dual-$V_{T}$ Design in Sub-100-nm PD/SOI and Double-Gate Technologies Ieee Transactions On Electron Devices. 55: 1161-1169. DOI: 10.1109/Ted.2008.918426  0.793
2008 Chen Q, Mojumder NN, Roy K. Modeling and analysis of the asymmetric source/drain extension CMOS transistors for nanoscale technologies Ieee Transactions On Electron Devices. 55: 1005-1012. DOI: 10.1109/Ted.2008.916685  0.817
2008 Kulkarni JP, Roy K. Technology circuit co-design for ultra fast InSb quantum well transistors Ieee Transactions On Electron Devices. 55: 2537-2545. DOI: 10.1109/Ted.2008.2003030  0.733
2008 Mukhopadhyay S, Mahmoodi H, Roy K. Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 174-183. DOI: 10.1109/Tcad.2007.906995  0.531
2008 Ndai P, Bhunia S, Agarwal A, Roy K. Within-die variation-aware scheduling in superscalar processors for improved throughput Ieee Transactions On Computers. 57: 940-951. DOI: 10.1109/Tc.2008.40  0.795
2008 Roy K, Kulkarni JP, Hwang ME. Process-tolerant ultralow voltage digital subthreshold design 2008 Ieee Topical Meeting On Silicon Monolithic Integrated Circuits in Rf Systms - Digest of Papers, Sirf. 42-45. DOI: 10.1109/SMIC.2008.17  0.71
2008 Mukhopadhyay S, Kim K, Jenkins KA, Chuang CT, Roy K. An on-chip test structure and digital measurement method for statistical characterization of local random variability in a process Ieee Journal of Solid-State Circuits. 43: 1951-1963. DOI: 10.1109/Jssc.2008.2001896  0.607
2008 Kim K, Mahmoodi H, Roy K. A Low-Power SRAM Using Bit-Line Charge-Recycling Ieee Journal of Solid-State Circuits. 43: 446-459. DOI: 10.1109/Jssc.2007.914294  0.393
2008 Kulkarni JP, Meterelliyoz M, Roy K, Murthy J. Nano-scaled SRAM thermal stability analysis using hierarchical compact thermal models 2008 11th Ieee Intersociety Conference On Thermal and Thermomechanical Phenomena in Electronic Systems, I-Therm. 999-1005. DOI: 10.1109/ITHERM.2008.4544375  0.803
2008 Raychowdhury A, Kurtin J, Borkar S, De V, Roy K, Keshavarzi A. Theory of multi-tube carbon nanotube transistors for high speed variation-tolerant circuits Device Research Conference - Conference Digest, Drc. 23-24. DOI: 10.1109/DRC.2008.4800719  0.685
2008 Banerjee N, Augustine C, Roy K. Fault-tolerance with graceful degradation in quality: A design methodology and its application to digital signal processing systems Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 323-331. DOI: 10.1109/DFT.2008.43  0.648
2008 Kulkarni JP, Kim K, Park SP, Roy K. Process variation tolerant SRAM array for ultra low voltage applications Proceedings - Design Automation Conference. 108-113. DOI: 10.1109/DAC.2008.4555791  0.7
2008 Li J, Liu H, Salahuddin S, Roy K. Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement Proceedings of the Custom Integrated Circuits Conference. 193-196. DOI: 10.1109/CICC.2008.4672056  0.324
2008 Meterelliyoz M, Song P, Stellari F, Kulkarni JP, Roy K. A high sensitivity process variation sensor utilizing sub-threshold operation Proceedings of the Custom Integrated Circuits Conference. 125-128. DOI: 10.1109/CICC.2008.4672037  0.816
2008 Budnik M, Wood J, Spagnuolo N, Roy K. An active suppression circuit for the reduction of di/dt event supply voltage variation Conference Proceedings - Ieee Applied Power Electronics Conference and Exposition - Apec. 893-896. DOI: 10.1109/APEC.2008.4522826  0.687
2008 Bhunia S, Mahmoodi H, Raychowdhury A, Roy K. Arbitrary two-pattern delay testing using a low-overhead supply gating technique Journal of Electronic Testing: Theory and Applications (Jetta). 24: 577-590. DOI: 10.1007/S10836-008-5072-4  0.697
2007 Raychowdhury A, Kurtin J, Roy K, De V, Keshavarzi A. Digital Circuits with Carbon Nanotube Transistors The Japan Society of Applied Physics. 2007: 1162-1163. DOI: 10.7567/Ssdm.2007.J-9-1  0.71
2007 Banerjee N, Roy K. Computation Partitioning and Reuse for Power Efficient High Performance Digital Signal Processing Journal of Low Power Electronics. 3: 254-270. DOI: 10.1166/Jolpe.2007.141  0.557
2007 Kulkarni JP, Kim K, Roy K. A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM Proceedings of the International Symposium On Low Power Electronics and Design. 171-176. DOI: 10.1145/1283780.1283818  0.699
2007 Mohapatra D, Karakonstantis G, Roy K. Low-power process-variation tolerant arithmetic units using input-based elastic clocking Proceedings of the International Symposium On Low Power Electronics and Design. 74-79. DOI: 10.1145/1283780.1283797  0.735
2007 Ghosh S, Bhunia S, Roy K. Low-Power and testable circuit synthesis using Shannon decomposition Acm Transactions On Design Automation of Electronic Systems. 12: 47. DOI: 10.1145/1278349.1278360  0.722
2007 Hwang ME, Raychowdhury A, Kim K, Roy K. A 85mV 40nW process-tolerant subthreshold 8×8 FIR filter in 13nm technology Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 154-155. DOI: 10.1109/VLSIC.2007.4342695  0.581
2007 Agarwal A, Kang K, Bhunia S, Gallagher JD, Roy K. Device-aware yield-centric dual-Vt design under parameter variations in nanoscale technologies Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 660-671. DOI: 10.1109/Tvlsi.2007.898683  0.705
2007 Wang Y, Muhammad K, Roy K. Design of Sigma–Delta Modulators With Arbitrary Transfer Functions Ieee Transactions On Signal Processing. 55: 677-683. DOI: 10.1109/Tsp.2006.885735  0.482
2007 Cakici RT, Roy K. Analysis of Options in Double-Gate MOS Technology: A Circuit Perspective Ieee Transactions On Electron Devices. 54: 3361-3368. DOI: 10.1109/Ted.2007.909057  0.459
2007 Li J, Bansal A, Roy K. Poly-Si Thin-Film Transistors: An Efficient and Low-Cost Option for Digital Operation Ieee Transactions On Electron Devices. 54: 2918-2929. DOI: 10.1109/Ted.2007.906940  0.582
2007 Bansal A, Roy K. Analytical Subthreshold Potential Distribution Model for Gate Underlap Double-Gate MOS Transistors Ieee Transactions On Electron Devices. 54: 1793-1798. DOI: 10.1109/Ted.2007.898042  0.556
2007 Bansal A, Mukhopadhyay S, Roy K. Device-Optimization Technique for Robust and Low-Power FinFET SRAM Design in NanoScale Era Ieee Transactions On Electron Devices. 54: 1409-1419. DOI: 10.1109/Ted.2007.895879  0.696
2007 Raychowdhury A, Roy K. Carbon nanotube electronics: Design of high-performance and low-power digital circuits Ieee Transactions On Circuits and Systems I: Regular Papers. 54: 2391-2401. DOI: 10.1109/Tcsi.2007.907799  0.649
2007 Suzuki H, Kim CH, Roy K. Fast Tag Comparator Using Diode Partitioned Domino for 64-bit Microprocessors Ieee Transactions On Circuits and Systems. 54: 322-328. DOI: 10.1109/Tcsi.2006.885998  0.474
2007 Choi JH, Bansal A, Meterelliyoz M, Murthy J, Roy K. Self-consistent approach to leakage power and temperature estimation to predict thermal runaway in FinFET circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 2059-2068. DOI: 10.1109/Tcad.2007.906470  0.793
2007 Datta A, Goel A, Cakici RT, Mahmoodi H, Lekshmanan D, Roy K. Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1957-1966. DOI: 10.1109/Tcad.2007.896320  0.753
2007 Kang K, Kufluoglu H, Roy K, Alam MA. Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1770-1781. DOI: 10.1109/Tcad.2007.896317  0.554
2007 Ghosh S, Bhunia S, Roy K. CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1947-1956. DOI: 10.1109/Tcad.2007.896305  0.764
2007 Paul BC, Kang K, Kufluoglu H, Alam MA, Roy K. Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 743-751. DOI: 10.1109/Tcad.2006.884870  0.561
2007 Cakici T, Jung B, Roy K. High Q and high tuning range FinFET based varactors for low cost SoC integration Proceedings - Ieee International Soi Conference. 67-68. DOI: 10.1109/SOI.2006.284436  0.777
2007 Mukhopadhyay S, Kim K, Mahmoodi H, Roy K. Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS Ieee Journal of Solid-State Circuits. 42: 1370-1382. DOI: 10.1109/Jssc.2007.897161  0.578
2007 Kulkarni JP, Kim K, Roy K. A 160 mV robust schmitt trigger based subthreshold SRAM Ieee Journal of Solid-State Circuits. 42: 2303-2313. DOI: 10.1109/Jssc.2007.897148  0.725
2007 Cakici T, Keejong K, Roy K. FinFET based SRAM design for low standby power application Proceedings - Eighth International Symposium On Quality Electronic Design, Isqed 2007. 127-132. DOI: 10.1109/ISQED.2007.76  0.833
2007 Ndai P, Lu SL, Somesekhar D, Roy K. Fine-grained redundancy in adders Proceedings - Eighth International Symposium On Quality Electronic Design, Isqed 2007. 317-321. DOI: 10.1109/ISQED.2007.75  0.766
2007 Kulkarni JP, Roy K. A high performance, scalable multiplexed keeper technique Proceedings - Eighth International Symposium On Quality Electronic Design, Isqed 2007. 545-549. DOI: 10.1109/ISQED.2007.14  0.666
2007 Ghosh S, NDai P, Bhunia S, Roy K. Tolerance to small delay defects by adaptive clock stretching Proceedings - Iolts 2007 13th Ieee International On-Line Testing Symposium. 244-249. DOI: 10.1109/IOLTS.2007.67  0.832
2007 Karakonstantis G, Banerjee N, Roy K, Chakrabarti C. Design methodology to trade off power, output quality and error resiliency: Application to color interpolation filtering Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 199-204. DOI: 10.1109/ICCAD.2007.4397266  0.724
2007 Karakonstantis G, Roy K. An optimal algorithm for low power multiplierless fir filter design using chebychev criterion Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 2: II49-II52. DOI: 10.1109/ICASSP.2007.366169  0.669
2007 Banerjee N, Karakonstantis G, Roy K. Process variation tolerant low power DCT architecture Proceedings -Design, Automation and Test in Europe, Date. 630-635. DOI: 10.1109/DATE.2007.364664  0.74
2007 Hwang ME, Cakici T, Roy K. Process tolerant β-ratio modulation for ultra-dynamic voltage scaling Proceedings -Design, Automation and Test in Europe, Date. 1550-1555. DOI: 10.1109/DATE.2007.364521  0.783
2007 Suzuki H, Jeong W, Roy K. Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders Ieice Transactions On Electronics. 90: 865-876. DOI: 10.1093/Ietele/E90-C.4.865  0.585
2007 Mukhopadhyay S, Kim K, Kim J, Lo S, Joshi RV, Chuang C, Roy K. Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices Microelectronics Journal. 38: 931-941. DOI: 10.1016/J.Mejo.2006.03.010  0.701
2006 Kang K, Paul BC, Roy K. Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters Acm Transactions On Design Automation of Electronic Systems. 11: 848-879. DOI: 10.1145/1179461.1179464  0.508
2006 Raychowdhury A, Xuanyao F, Qikai C, Roy K. Analysis of super cut-off transistors for ultralow power digital logic circuits Proceedings of the International Symposium On Low Power Electronics and Design. 2006: 2-7. DOI: 10.1145/1165573.1165577  0.605
2006 Budnik M, Raychowdhury A, Bansal A, Roy K. A high density, carbon nanotube capacitor for decoupling applications Proceedings - Design Automation Conference. 935-938. DOI: 10.1145/1146909.1147146  0.733
2006 Choi J, Bansal A, Meterelliyoz M, Roy K, Murthy JY. Concurrent electro-thermal design of VLSI circuits American Society of Mechanical Engineers, Heat Transfer Division, (Publication) Htd. DOI: 10.1115/IMECE2006-13803  0.752
2006 Roy K, Mahmoodi H, Mukhopadhyay S, Ananthan H, Bansal A, Cakici T. Double-gate SOI devices for low-power and high-performance applications Proceedings of the Ieee International Conference On Vlsi Design. 2006: 445-452. DOI: 10.1109/VLSID.2006.74  0.834
2006 Budnik MM, Roy K. A power delivery and decoupling network minimizing ohmic loss and supply voltage variation in silicon nanoscale technologies Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 1336-1346. DOI: 10.1109/Tvlsi.2006.887810  0.702
2006 Banerjee N, Raychowdhury A, Roy K, Bhunia S, Mahmoodi H. Novel low-overhead operand isolation techniques for low-power datapath synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 1034-1039. DOI: 10.1109/Tvlsi.2006.884054  0.778
2006 Kim CH, Roy K, Hsu S, Krishnamurthy R, Borkar S. A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits Ieee Transactions On Very Large Scale Integration Systems. 14: 646-649. DOI: 10.1109/Tvlsi.2006.878226  0.39
2006 Kim J, Roy K. A leakage-tolerant low-swing circuit style in partially depleted silicon-on-insulator CMOS technologies Ieee Transactions On Very Large Scale Integration Systems. 14: 549-552. DOI: 10.1109/Tvlsi.2006.876110  0.667
2006 Mukhopadhyay S, Mahmoodi H, Roy K. A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET Ieee Transactions On Very Large Scale Integration Systems. 14: 183-192. DOI: 10.1109/Tvlsi.2005.863743  0.633
2006 Kang D, Choo H, Muhammad K, Roy K. Layout-driven architecture synthesis for high-speed digital filters Ieee Transactions On Very Large Scale Integration Systems. 14: 203-207. DOI: 10.1109/Tvlsi.2005.863741  0.555
2006 Raychowdhury A, Keshavarzi A, Kurtin J, De V, Roy K. Carbon nanotube field-effect transistors for high-performance digital circuits - DC analysis and modeling toward optimum transistor structure Ieee Transactions On Electron Devices. 53: 2711-2717. DOI: 10.1109/Ted.2006.883816  0.749
2006 Keshavarzi A, Raychowdhury A, Kurtin J, Roy K, De V. Carbon nanotube field-effect transistors for high-performance digital circuits - Transient analysis, parasitics, and scalability Ieee Transactions On Electron Devices. 53: 2718-2726. DOI: 10.1109/Ted.2006.883813  0.76
2006 Paul BC, Bansal A, Roy K. Underlap DGMOS for digital-subthreshold operation Ieee Transactions On Electron Devices. 53: 910-913. DOI: 10.1109/Ted.2006.870271  0.626
2006 Ananthan H, Roy K. Technology and circuit design considerations in quasi-planar double-gate SRAM Ieee Transactions On Electron Devices. 53: 242-250. DOI: 10.1109/Ted.2005.862697  0.389
2006 Ghosh S, Bhunia S, Raychowdhury A, Roy K. A novel delay fault testing methodology using low-overhead built-in delay sensor Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2934-2943. DOI: 10.1109/Tcad.2006.882523  0.751
2006 Bansal A, Paul BC, Roy K. An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2765-2774. DOI: 10.1109/Tcad.2006.882489  0.526
2006 Mukhopadhyay S, Kim K, Chuang C, Roy K. Modeling and Analysis of Leakage Currents in Double-Gate Technologies Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2052-2061. DOI: 10.1109/Tcad.2006.873892  0.595
2006 Datta A, Bhunia S, Mukhopadhyay S, Roy K. Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2427-2436. DOI: 10.1109/Tcad.2006.873886  0.758
2006 Mukhopadhyay S, Bhunia S, Roy K. Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1486-1495. DOI: 10.1109/Tcad.2005.855934  0.717
2006 Raychowdhury A, Roy K. Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 58-65. DOI: 10.1109/Tcad.2005.853702  0.605
2006 Agarwal A, Mukhopadhyay S, Raychowdhury A, Roy K, Kim CH. Leakage power analysis and reduction for nanoscale circuits Ieee Micro. 26: 68-80. DOI: 10.1109/Mm.2006.39  0.739
2006 Mukhopadhyay S, Kim K, Wang X, Frank DJ, Oldiges P, Chuang CT, Roy K. Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design Ieee Electron Device Letters. 27: 284-287. DOI: 10.1109/Led.2006.871540  0.573
2006 Singh S, Bansal A, Meterelliyoz M, Choi JH, Roy K, Murthy JY. Compact thermal models for thermally aware design of VLSI circuits Thermomechanical Phenomena in Electronic Systems -Proceedings of the Intersociety Conference. 2006: 671-677. DOI: 10.1109/ITHERM.2006.1645410  0.752
2006 Budnik MM, Roy K. Minimizing ohmic loss in future processor IR events Proceedings - International Symposium On Quality Electronic Design, Isqed. 650-658. DOI: 10.1109/ISQED.2006.88  0.65
2006 Chen Q, Meterelliyoz M, Roy K. A CMOS thermal sensor and its applications in temperature adaptive design Proceedings - International Symposium On Quality Electronic Design, Isqed. 243-248. DOI: 10.1109/ISQED.2006.6  0.753
2006 Ghosh S, Bhunia S, Raychowdhury A, Roy K. Delay fault localization in test-per-scan BIST using built-in delay sensor Proceedings - Iolts 2006: 12th Ieee International On-Line Testing Symposium. 2006: 31-36. DOI: 10.1109/IOLTS.2006.19  0.645
2006 Choi JH, Bansal A, Meterelliyoz M, Murthy J, Roy K. Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 583-586. DOI: 10.1109/ICCAD.2006.320104  0.744
2006 Raychowdhury A, Kim JI, Peroulis D, Roy K. Integrated MEMS switches for leakage control of battery operated systems Proceedings of the Custom Integrated Circuits Conference. 457-460. DOI: 10.1109/CICC.2006.320821  0.605
2006 Keshavarzi A, Raychowdhury A, Kurtin J, Roy K, De V. Scalability of carbon nanotube FET-based circuits 2006 Ieee Asian Solid-State Circuits Conference, Asscc 2006. 415-418. DOI: 10.1109/ASSCC.2006.357939  0.724
2006 Paul BC, Agarwal A, Roy K. Low-power design techniques for scaled technologies Integration. 39: 64-89. DOI: 10.1016/J.Vlsi.2005.12.001  0.426
2006 Paul BC, Roy K. Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits Journal of Electronic Testing. 22: 115-124. DOI: 10.1007/S10836-006-7427-Z  0.371
2005 Cao A, Sirisantana N, Koh CK, Roy K. Synthesis of skewed logic circuits Acm Transactions On Design Automation of Electronic Systems. 10: 205-228. DOI: 10.1145/1059876.1059878  0.827
2005 Chiou L, Bhunia S, Roy K. Synthesis of application-specific highly efficient multi-mode cores for embedded systems Acm Transactions On Embedded Computing Systems (Tecs). 4: 168-188. DOI: 10.1145/1053271.1053278  0.73
2005 Raychowdhury A, Paul BC, Bhunia S, Roy K. Computing with subthreshold leakage: Device/circuit/architecture co-design for ultralow-power subthreshold operation Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 1213-1223. DOI: 10.1109/Tvlsi.2005.859590  0.738
2005 Chen Q, Mahmoodi H, Bhunia S, Roy K. Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations Ieee Transactions On Very Large Scale Integration Systems. 13: 1286-1295. DOI: 10.1109/Tvlsi.2005.859565  0.67
2005 Li H, Cher CY, Roy K, Vijaykumar TN. Combined circuit and architectural level variable supply-voltage scaling for low power Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 564-575. DOI: 10.1109/Tvlsi.2005.844295  0.55
2005 Kim CH, Kim J, Mukhopadhyay S, Roy K. A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations Ieee Transactions On Very Large Scale Integration Systems. 13: 349-357. DOI: 10.1109/Tvlsi.2004.842903  0.756
2005 Bhunia S, Mahmoodi H, Ghosh D, Mukhopadhyay S, Roy K. Low-power scan design using first-level supply gating Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 384-395. DOI: 10.1109/Tvlsi.2004.842885  0.714
2005 Bhunia S, Roy K. A novel wavelet transform-based transient current analysis for fault detection and localization Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 503-507. DOI: 10.1109/Tvlsi.2004.842880  0.549
2005 Agarwal A, Paul B, Mahmoodi H, Datta A, Roy K. A process-tolerant cache architecture for improved yield in nanoscale technologies Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 27-38. DOI: 10.1109/Tvlsi.2004.840407  0.633
2005 Chen Y, Roy K, Koh CK. Current demand balancing: A technique for minimization of current surge in high performance clock-gated microprocessors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 75-85. DOI: 10.1109/Tvlsi.2004.840404  0.384
2005 Raychowdhury A, Roy K. Carbon-nanotube-based voltage-mode multiple-valued logic design Ieee Transactions On Nanotechnology. 4: 168-179. DOI: 10.1109/Tnano.2004.842068  0.666
2005 Meterelliyoz M, Mahmoodi H, Roy K. A leakage control system for thermal stability during burn-in test Proceedings - International Test Conference. 2005: 982-991. DOI: 10.1109/TEST.2005.1584064  0.73
2005 Bansal A, Roy K. Asymmetric halo CMOSFET to reduce static power dissipation with improved performance Ieee Transactions On Electron Devices. 52: 397-405. DOI: 10.1109/Ted.2005.843969  0.622
2005 Bansal A, Paul BC, Roy K. Modeling and optimization of fringe capacitance of nanoscale DGMOS devices Ieee Transactions On Electron Devices. 52: 256-262. DOI: 10.1109/Ted.2004.842713  0.604
2005 Paul BC, Raychowdhury A, Roy K. Device optimization for digital subthreshold logic operation Ieee Transactions On Electron Devices. 52: 237-247. DOI: 10.1109/Ted.2004.842538  0.687
2005 Hwang ME, Raychowdhury A, Roy K. Energy-recovery techniques to reduce on-chip power density in molecular nanotechnologies Ieee Transactions On Circuits and Systems I: Regular Papers. 52: 1580-1589. DOI: 10.1109/Tcsi.2005.851692  0.722
2005 Mukhopadhyay S, Mahmoodi H, Roy K. Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1859-1880. DOI: 10.1109/Tcad.2005.852295  0.561
2005 Mukhopadhyay S, Raychowdhury A, Roy K. Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 363-381. DOI: 10.1109/Tcad.2004.842810  0.742
2005 Bhunia S, Datta A, Banerjee N, Roy K. GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks Ieee Transactions On Computers. 54: 752-766. DOI: 10.1109/Tc.2005.99  0.771
2005 Cakici T, Mahmoodi H, Mukhopadhyay S, Roy K. Independent gate skewed logic in double-gate SOI technology Proceedings - Ieee International Soi Conference. 2005: 83-84. DOI: 10.1109/SOI.2005.1563543  0.806
2005 Raychowdhury A, Guo J, Roy K, Lundstrom M. Design of a novel three-valued static memory using schottky barrier carbon nanotube FETs 2005 5th Ieee Conference On Nanotechnology. 2: 695-698. DOI: 10.1109/NANO.2005.1500812  0.593
2005 Paul BC, Kang K, Kufluoglu H, Alam MA, Roy K. Impact of NBTI on the temporal performance degradation of digital circuits Ieee Electron Device Letters. 26: 560-562. DOI: 10.1109/Led.2005.852523  0.563
2005 Mahmoodi H, Mukhopadhyay S, Roy K. Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits Ieee Journal of Solid-State Circuits. 40: 1787-1796. DOI: 10.1109/Jssc.2005.852164  0.613
2005 Agarwal A, Paul BC, Mukhopadhyay S, Roy K. Process variation in embedded memories: failure analysis and variation aware architecture Ieee Journal of Solid-State Circuits. 40: 1804-1814. DOI: 10.1109/Jssc.2005.852159  0.629
2005 Jeong W, Roy K. High-performance low-power dual transition preferentially sized (DTPS) logic Ieee Journal of Solid-State Circuits. 40: 480-483. DOI: 10.1109/Jssc.2004.841040  0.573
2005 Raychowdhury A, Ghosh S, Roy K. A novel on-chip delay measurement hardware for efficient speed-binning Proceedings - 11th Ieee International On-Line Testing Symposium, Iolts 2005. 2005: 287-292. DOI: 10.1109/IOLTS.2005.10  0.645
2005 Raychowdhury A, Mukhopadhyay S, Roy K. A feasibility study of subthreshold SRAM across technology generations Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 417-422. DOI: 10.1109/ICCD.2005.7  0.612
2005 Ndai P, Agarwal A, Chen Q, Roy K. A soft error monitor using switching current detection Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 185-190. DOI: 10.1109/ICCD.2005.15  0.781
2005 Raychowdhury A, Ghosh S, Bhunia S, Ghosh D, Roy K. A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points Proceedings of the 10th Ieee European Test Symposium, Ets 2005. 2005: 108-113. DOI: 10.1109/ETS.2005.2  0.647
2005 Bhunia S, Mahmoodi H, Raychowdhury A, Roy K. A novel low-overhead delay testing technique for arbitrary two-pattern test application Proceedings -Design, Automation and Test in Europe, Date '05. 1136-1141. DOI: 10.1109/DATE.2005.27  0.698
2005 Mukhopadhyay S, Raychowdhury A, Mahmoodi H, Roy K. Leakage current based stabilization scheme for robust sense-amplifier design for yield enhancement in nano-scale SRAM Proceedings of the Asian Test Symposium. 2005: 176-181. DOI: 10.1109/ATS.2005.73  0.622
2005 Agarwal A, Mukhopadhyay S, Kim CH, Raychowdhury A, Roy K. Leakage power analysis and reduction: Models, estimation and tools Iee Proceedings: Computers and Digital Techniques. 152: 353-368. DOI: 10.1049/ip-cdt:20045084  0.643
2005 Bhunia S, Raychowdhury A, Roy K. Frequency specification testing of analog filters using wavelet transform of dynamic supply current Journal of Electronic Testing: Theory and Applications (Jetta). 21: 243-255. DOI: 10.1007/s10836-005-6354-8  0.637
2005 Bhunia S, Raychowdhury A, Roy K. Defect oriented testing of analog circuits using wavelet analysis of dynamic supply current Journal of Electronic Testing: Theory and Applications (Jetta). 21: 147-159. DOI: 10.1007/S10836-005-6144-3  0.693
2004 Dasmahapatra GP, Didolkar P, Alley MC, Ghosh S, Sausville EA, Roy KK. In vitro combination treatment with perifosine and UCN-01 demonstrates synergism against prostate (PC-3) and lung (A549) epithelial adenocarcinoma cell lines. Clinical Cancer Research : An Official Journal of the American Association For Cancer Research. 10: 5242-52. PMID 15297428 DOI: 10.1158/1078-0432.CCR-03-0534  0.486
2004 Li H, Bhunia S, Chen Y, Roy K, Vijaykumar TN. DCG: Deterministic Clock-Gating for Low-Power Microprocessor Design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 245-254. DOI: 10.1109/TVLSI.2004.824307  0.584
2004 Choo H, Muhammad K, Roy K. Complexity reduction of digital filters using shift inclusive differential coefficients Ieee Transactions On Signal Processing. 52: 1760-1772. DOI: 10.1109/Tsp.2004.827177  0.464
2004 Kim J, Roy K. Double gate-MOSFET subthreshold circuit for ultralow power applications Ieee Transactions On Electron Devices. 51: 1468-1474. DOI: 10.1109/Ted.2004.833965  0.668
2004 Mahmoodi-Meimand H, Roy K. Diode-footed domino: A leakage-tolerant high fan-in dynamic circuit design style Ieee Transactions On Circuits and Systems I: Regular Papers. 51: 495-503. DOI: 10.1109/Tcsi.2004.823665  0.812
2004 Raychowdhury A, Mukhopadhyay S, Roy K. A circuit-compatible model of ballistic carbon nanotube field-effect transistors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1411-1420. DOI: 10.1109/Tcad.2004.835135  0.72
2004 Sirisantana N, Paul BC, Roy K. Enhancing yield at the end of the technology roadmap Ieee Design and Test of Computers. 21: 563-571. DOI: 10.1109/Mdt.2004.86  0.82
2004 Sirisantana N, Roy K. Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses Ieee Design and Test of Computers. 21: 56-63. DOI: 10.1109/Mdt.2004.1261850  0.821
2004 Park J, Jeong W, Mahmoodi-Meimand H, Wang Y, Choo H, Roy K. Computation sharing programmable FIR filter for low-power and high-performance applications Ieee Journal of Solid-State Circuits. 39: 348-357. DOI: 10.1109/Jssc.2003.821785  0.816
2004 Raychowdhury A, Roy K. A circuit model for carbon nanotube interconnects: Comparative study with Cu interconnects for scaled technologies Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 237-240. DOI: 10.1109/ICCAD.2004.1382578  0.569
2004 Bhunia S, Raychowdhury A, Roy K. Trim bit setting of analog filters using wavelet-based supply current analysis Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 708-709. DOI: 10.1109/DATE.2004.1268941  0.646
2003 Ray K, Mukhopadhyay S, Dutt D, Chatterjee PK, Roychowdhury PK, Roy K, Banerjee SN. Cross-sectional study of consumption, compliance and awareness about antibiotic utilisation amongst the urban community in Kolkata. Journal of the Indian Medical Association. 101: 7, 9-10. PMID 12841499  0.379
2003 Deka D, Malhotra N, Sinha A, Banerjee N, Kashyap R, Roy KK. Pregnancy associated aplastic anemia: maternal and fetal outcome. The Journal of Obstetrics and Gynaecology Research. 29: 67-72. PMID 12755524  0.388
2003 Roy K, Mahmoodi-Meimand H, Mukhopadhyay S. Leakage control for deep-submicron circuits Proceedings of Spie - the International Society For Optical Engineering. 5117: 135-146. DOI: 10.1117/12.498181  0.828
2003 Mukhopadhyay S, Mahmoodi-Meimand H, Neau C, Roy K. Leakage in nanometer scale CMOS circuits International Symposium On Vlsi Technology, Systems, and Applications, Proceedings. 2003: 307-312. DOI: 10.1109/VTSA.2003.1252615  0.808
2003 Kim CHI, Soeleman H, Roy K. Ultra-low-power DLMS adaptive filter for hearing aid applications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 1058-1067. DOI: 10.1109/Tvlsi.2003.819573  0.822
2003 Mukhopadhyay S, Neau C, Cakici RT, Agarwal A, Kim CH, Roy K. Gate leakage reduction for scaled devices using transistor stacking Ieee Transactions On Very Large Scale Integration Systems. 11: 716-730. DOI: 10.1109/Tvlsi.2003.816145  0.596
2003 Keshavarzi A, Roy K, Hawkins CF, De V. Multiple-Parameter CMOS IC Testing with Increased Sensitivity for I DDQ Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 863-870. DOI: 10.1109/Tvlsi.2003.812298  0.602
2003 Park J, Muhammad K, Roy K. High-performance FIR filter design based on sharing multiplication Ieee Transactions On Very Large Scale Integration Systems. 11: 244-253. DOI: 10.1109/Tvlsi.2002.800529  0.514
2003 Choo H, Muhammad K, Roy K. Two's complement computation sharing multiplier and its applications to high performance DFE Ieee Transactions On Signal Processing. 51: 458-469. DOI: 10.1109/Tsp.2002.806984  0.572
2003 Zhong G, Koh CK, Roy K. On-chip interconnect modeling by wire duplication Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1521-1532. DOI: 10.1109/Tcad.2003.818303  0.558
2003 Mahmoodi-Meimand H, Roy K. A leakage-tolerant high fan-in dynamic circuit design style [logic circuits] Proceedings - Ieee International Soc Conference, Socc 2003. 117-120. DOI: 10.1109/SOC.2003.1241475  0.798
2003 Raychowdhury A, Mukhopadhyay S, Roy K. Circuit-compatible modeling of carbon nanotube FETs in the ballistic limit of performance Proceedings of the Ieee Conference On Nanotechnology. 1: 343-346. DOI: 10.1109/NANO.2003.1231788  0.605
2003 Li H, Cher CY, Vijaykumar TN, Roy K. VSV: L2-miss-driven variable supply-voltage scaling for low power Proceedings of the Annual International Symposium On Microarchitecture, Micro. 2003: 19-28. DOI: 10.1109/MICRO.2003.1253180  0.324
2003 Agarwal A, Li H, Roy K. A single-V/sub t/ low-leakage gated-ground cache for deep submicron Ieee Journal of Solid-State Circuits. 38: 319-328. DOI: 10.1109/Jssc.2002.807414  0.559
2003 Roy K, Mukhopadhyay S, Mahmoodi-Meimand H. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits Proceedings of the Ieee. 91: 305-327. DOI: 10.1109/JPROC.2002.808156  0.801
2003 Li H, Bhunia S, Chen Y, Vijaykumar TN, Roy K. Deterministic clock gating for microprocessor power reduction Proceedings - International Symposium On High-Performance Computer Architecture. 12: 113-122. DOI: 10.1109/HPCA.2003.1183529  0.593
2003 Sirisantana N, Roy K. A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologies European Solid-State Circuits Conference. 181-184. DOI: 10.1109/ESSCIRC.2003.1257102  0.836
2003 Sirisantana N, Roy K. Selectively clocked CMOS logic style for low-power noise-immune operations in scaled technologies Proceedings -Design, Automation and Test in Europe, Date. 1160-1161. DOI: 10.1109/DATE.2003.1253781  0.834
2003 Agarwal A, Roy K, Vijaykumar TN. Exploring high bandwidth pipelined cache architecture for scaled technology Proceedings -Design, Automation and Test in Europe, Date. 778-783. DOI: 10.1109/DATE.2003.1253701  0.313
2003 Cao A, Sirisantana N, Koh CK, Roy K. Integer linear programming-based synthesis of skewed logic circuits Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2003: 820-823. DOI: 10.1109/ASPDAC.2003.1195131  0.816
2003 Jeong W, Roy K. Robust high-performance low-power carry select adder Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2003: 503-506. DOI: 10.1109/ASPDAC.2003.1195068  0.319
2002 Roy K, Mukhopadhyay S, Mahmoodi-Meimand H. Leakage current in deep-submicron CMOS circuits Journal of Circuits, Systems and Computers. 11: 575-600. DOI: 10.1142/S021812660200063X  0.83
2002 Solomatnikov A, Somasekhar D, Sirisantana N, Roy K. Skewed CMOS: Noise-tolerant high-performance low-power static circuit family Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 469-476. DOI: 10.1109/Tvlsi.2002.800519  0.833
2002 Wei L, Zhang R, Roy K, Chen Z, Janes DB. Vertically integrated SOI circuits for low-power and high-performance applications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 351-362. DOI: 10.1109/Tvlsi.2002.1043338  0.692
2002 Muhammad K, Roy K. Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling Ieee Transactions On Very Large Scale Integration Systems. 10: 292-300. DOI: 10.1109/Tvlsi.2002.1043332  0.33
2002 Im Y, Roy K. O/sup 2/ABA: a novel high-performance predictable circuit architecture for the deep submicron era Ieee Transactions On Very Large Scale Integration Systems. 10: 221-229. DOI: 10.1109/Tvlsi.2002.1043325  0.386
2002 Keshavarzi A, Tschanz JW, Narendra S, De V, Roy K, Hawkins CF, Daasch WR, Sachdev M. Leakage and process variation effects in current testing on future CMOS circuits Ieee Design and Test of Computers. 19: 36-43. DOI: 10.1109/Mdt.2002.1033790  0.629
2002 Cao A, Sirisantana N, Koh CK, Roy K. Synthesis of selectively clocked skewed logic circuits Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 229-234. DOI: 10.1109/ISQED.2002.996737  0.828
2002 Johnson MC, Somasekhar D, Chiou L, Roy K. Leakage control with efficient use of transistor stacks in single threshold CMOS Ieee Transactions On Very Large Scale Integration Systems. 10: 1-5. DOI: 10.1109/92.988724  0.676
2002 Chen Z, Wei L, Keshavarzi A, Roy K. I DDQ testing for deep-submicron ICs: Challenges and solutions Ieee Design and Test of Computers. 19: 24-33. DOI: 10.1109/54.990439  0.647
2002 Zhao S, Roy K, Koh CK. Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 81-92. DOI: 10.1109/43.974140  0.537
2002 Zhang R, Roy K. Low-power high-performance double-gate fully depleted SOI circuit design Ieee Transactions On Electron Devices. 49: 852-862. DOI: 10.1109/16.998595  0.697
2002 Zhang R, Roy K, Koh CK, Janes DB. Exploring SOI device structures and interconnect architectures for low-power high-performance circuits Iee Proceedings: Computers and Digital Techniques. 149: 137-145. DOI: 10.1049/ip-cdt:20020451  0.345
2002 Choi SH, Somasekhar D, Roy K. Dynamic noise model and its application to high speed circuit design Microelectronics Journal. 33: 835-846. DOI: 10.1016/S0026-2692(02)00094-0  0.328
2001 Kriplani A, Abbi M, Banerjee N, Roy KK, Takkar D. Indomethacin therapy in the treatment of polyhydramnios due to placental chorioangioma. The Journal of Obstetrics and Gynaecology Research. 27: 245-8. PMID 11776505  0.4
2001 Banerjee N, Sinha A, Kriplani A, Roy KK, Takkar D. Factors determining the occurrence of unwanted pregnancies. The National Medical Journal of India. 14: 211-4. PMID 11547527  0.391
2001 Roy KK, Banerjee N, Sinha A. Diffuse peritoneal calcification--a rare manifestation of abdominal tuberculosis. International Journal of Gynaecology and Obstetrics: the Official Organ of the International Federation of Gynaecology and Obstetrics. 73: 269-70. PMID 11376677  0.375
2001 Mao HQ, Roy K, Troung-Le VL, Janes KA, Lin KY, Wang Y, August JT, Leong KW. Chitosan-DNA nanoparticles as gene carriers: synthesis, characterization and transfection efficiency. Journal of Controlled Release : Official Journal of the Controlled Release Society. 70: 399-421. PMID 11182210 DOI: 10.1016/S0168-3659(00)00361-8  0.359
2001 Deka D, Banerjee N, Roy KK, Choudhary VP, Kashyap R, Takkar D. Aplastic anaemia during pregnancy: variable clinical course and outcome. European Journal of Obstetrics, Gynecology, and Reproductive Biology. 94: 152-4. PMID 11134842  0.388
2001 Chiou L, Muhammand K, Roy K. Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications Vlsi Design. 12: 233-243. DOI: 10.1155/2001/35832  0.635
2001 Chen Z, Wei L, Roy K. On effective I/sub DDQ/ testing of low-voltage CMOS circuits using leakage control techniques Ieee Transactions On Very Large Scale Integration Systems. 9: 718-725. DOI: 10.1109/92.953504  0.41
2001 Soeleman H, Roy K, Paul BC. Robust subthreshold logic for ultra-low power operation Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 90-99. DOI: 10.1109/92.920822  0.836
2001 Powell M, Yang SH, Falsafi B, Roy K, Vijaykumar TN. Reducing leakage in a high-performance deep-submicron instruction cache Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 77-89. DOI: 10.1109/92.920821  0.373
2001 Ye Y, Roy K. QSERL: quasi-static energy recovery logic Ieee Journal of Solid-State Circuits. 36: 239-248. DOI: 10.1109/4.902764  0.416
2001 Zhang R, Roy K, Koh CK, Janes DB. Stochastic interconnect modeling, power trends, and performance characterization of 3-D circuits Ieee Transactions On Electron Devices. 48: 638-652. DOI: 10.1109/16.915671  0.631
2001 Yang SH, Powell MD, Falsafi B, Roy K, Vijaykumar TN. Integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance i-caches Ieee High-Performance Computer Architecture Symposium Proceedings. 147-157.  0.372
2000 Banerjee N, Roy KK, Takkar D. Pregnancy with unilateral lung agenesis. Acta Obstetricia Et Gynecologica Scandinavica. 79: 896-7. PMID 11304979  0.378
2000 Roy KK, Banerjee N, Sinha A. Laparoscopic removal of translocated retroperitoneal IUD. International Journal of Gynaecology and Obstetrics: the Official Organ of the International Federation of Gynaecology and Obstetrics. 71: 241-3. PMID 11102613  0.391
2000 Banerjee N, Roy KK, Takkar D. Premenstrual dysphoric disorder--a study from India. International Journal of Fertility and Women's Medicine. 45: 342-4. PMID 11092706  0.391
2000 Banerjee N, Deka D, Roy KK, Takkar D. Vesicocervical fistula: an unusual presentation. The Australian & New Zealand Journal of Obstetrics & Gynaecology. 40: 219-20. PMID 10925916  0.394
2000 Banerjee N, Deka D, Roy KK, Takkar D. Inversion of uterus during cesarean section. European Journal of Obstetrics, Gynecology, and Reproductive Biology. 91: 75-7. PMID 10817883  0.406
2000 Roy KK, Banerjee N, Takkar D. Pregnancy following tubal sterilization: an 11-year survey. International Journal of Gynaecology and Obstetrics: the Official Organ of the International Federation of Gynaecology and Obstetrics. 68: 53-4. PMID 10687839  0.378
2000 Roy K, Lee DT. Guest editorial: low-power electronics and design Ieee Transactions On Very Large Scale Integration Systems. 8: 233-234. DOI: 10.1109/Tvlsi.2000.845890  0.314
2000 Keshavarzi A, Roy K, Hawkins CF. Intrinsic leakage in deep submicron CMOS ICs - measurement-based test solutions Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 717-723. DOI: 10.1109/92.902266  0.571
2000 Soeleman H, Roy K, Chou TL. Estimating Circuit Activity in Combinational CMOS Digital Circuits Ieee Design and Test of Computers. 17: 112-119. DOI: 10.1109/54.844340  0.81
2000 Zhang X, Shan W, Roy K. Low-power weighted random pattern testing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 1389-1398. DOI: 10.1109/43.892863  0.381
2000 Chen Z, Roy K, Chong EK. Estimation of power dissipation using a novel power macromodeling technique Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 13631369. DOI: 10.1109/43.892859  0.376
2000 Powell M, Yang SH, Falsafi B, Roy K, Vijaykumar TN. Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories Proceedings of the International Symposium On Low Power Electronics and Design. 90-95.  0.374
1999 Wei L, Chen Z, Roy K, Johnson MC, Ye Y, De VK. Design and optimization of dual-threshold circuits for low-voltage low-power applications Ieee Transactions On Very Large Scale Integration Systems. 7: 16-24. DOI: 10.1109/92.748196  0.437
1999 Johnson MC, Somasekhar D, Roy K. Models and algorithms for bounds on leakage in CMOS circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 714-725. DOI: 10.1109/43.766723  0.428
1998 Kriplani A, Banerjee N, Kriplani AK, Roy KK, Takkar D. Uterovaginal prolapse associated with rectal prolapse. The Australian & New Zealand Journal of Obstetrics & Gynaecology. 38: 325-6. PMID 9761164  0.392
1998 Banerjee N, Kriplani A, Roy KK, Bal S, Takkar D. Retrieval of lost Copper-T from the rectum. European Journal of Obstetrics, Gynecology, and Reproductive Biology. 79: 211-2. PMID 9720843  0.437
1998 Chou T, Roy K. Power Estimation Under Uncertain Delays Computer-Aided Engineering. 5: 107-116. DOI: 10.3233/Ica-1998-5202  0.375
1998 Nag S, Roy K. Performance and Wirability Driven Layout for Row-Based FPGAs Vlsi Design. 7: 353-364. DOI: 10.1155/1998/57380  0.345
1998 Roy K. Leakage power reduction in low-voltage CMOS designs Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 2: 167-173. DOI: 10.1109/ICECS.1998.814856  0.337
1998 Somasekhar D, Roy K. LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family Ieee Transactions On Very Large Scale Integration Systems. 6: 573-577. DOI: 10.1109/92.736130  0.461
1998 Chen Z, Roy K, Chou T. Efficient statistical approach to estimate power considering uncertain properties of primary inputs Ieee Transactions On Very Large Scale Integration Systems. 6: 484-492. DOI: 10.1109/92.711319  0.346
1998 Wang C, Roy K. Maximum power estimation for CMOS circuits using deterministic and statistical approaches Ieee Transactions On Very Large Scale Integration Systems. 6: 134-140. DOI: 10.1109/92.661255  0.415
1997 Johnson MC, Roy K. Datapath scheduling with multiple supply voltages and level converters Acm Transactions On Design Automation of Electronic Systems. 2: 227-248. DOI: 10.1145/264995.264997  0.39
1996 Sardar S, Chatterjee M, Ghosh S, Roy K. Role of vitamin D3 on the activity patterns of hepatic drug metabolizing enzymes in transplantable murine lymphoma. Cancer Investigation. 14: 328-34. PMID 8689427  0.463
1996 Prasad SC, Roy K. Transistor reordering for power minimization under delay constraint Acm Transactions On Design Automation of Electronic Systems. 1: 280-300. DOI: 10.1145/233539.233543  0.422
1996 Chou T, Roy K. Accurate power estimation of CMOS sequential circuits Ieee Transactions On Very Large Scale Integration Systems. 4: 369-380. DOI: 10.1109/92.532037  0.358
1996 Ye Y, Roy K. Energy recovery circuits using reversible and partially reversible logic Ieee Transactions On Circuits and Systems I-Regular Papers. 43: 769-778. DOI: 10.1109/81.536746  0.406
1996 Chou T, Roy K. Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 1257-1265. DOI: 10.1109/43.541445  0.398
1996 Somasekhar D, Roy K. Differential current switch logic: a low power DCVS logic family Ieee Journal of Solid-State Circuits. 31: 981-991. DOI: 10.1109/4.508212  0.467
1995 Chakraborty A, Ghosh R, Roy K, Ghosh S, Chowdhury P, Chatterjee M. Vanadium: a modifier of drug-metabolizing enzyme patterns and its critical role in cellular proliferation in transplantable murine lymphoma. Oncology. 52: 310-4. PMID 7777245 DOI: 10.1159/000227480  0.461
1995 Roy K, Prasad S. Logic synthesis for reliability: an early start to controlling electromigration and hot-carrier effects Ieee Transactions On Reliability. 44: 251-255. DOI: 10.1109/24.387379  0.39
1994 Levitt ME, Roy K, Abraham JA. BiCMOS logic testing Ieee Transactions On Very Large Scale Integration Systems. 2: 241-248. DOI: 10.1109/92.285749  0.357
1993 Roy K, Prasad SC. Circuit Activity Based Logic Synthesis for Low Power Reliable Operations Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 1: 503-513. DOI: 10.1109/92.250198  0.435
1991 Roy K, Abraham JA. The Use of RTL Descriptions in Accurate Timing Verification and Test Generation Ieee Journal of Solid-State Circuits. 26: 1230-1239. DOI: 10.1109/4.84939  0.364
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