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Jaydeep P. Kulkarni, Ph.D. - Publications

Affiliations: 
2009 Electrical and Computer Engineering Purdue University, West Lafayette, IN, United States 
Area:
Electronics and Electrical Engineering
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45 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Sayal A, Ajay P, McDermott MW, Sreenivasan SV, Kulkarni JP. M2A2: Microscale Modular Assembled ASICs for High-Mix, Low-Volume, Heterogeneously Integrated Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2020.2982621  0.436
2020 Sayal A, Nibhanupudi SST, Fathima S, Kulkarni JP. A 12.08-TOPS/W All-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efficient Edge Computing Ieee Journal of Solid-State Circuits. 55: 60-75. DOI: 10.1109/Jssc.2019.2939888  0.413
2019 Meinerzhagen PA, Tokunaga C, Malavasi A, Vaidya V, Mendon A, Mathaikutty D, Kulkarni J, Augustine C, Cho M, Kim ST, Matthew GE, Jain R, Ryan J, Peng C, Paul S, et al. An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization Ieee Journal of Solid-State Circuits. 54: 144-157. DOI: 10.1109/Jssc.2018.2875097  0.645
2018 Motaman S, Ghosh S, Kulkarni J. Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing Acm Journal On Emerging Technologies in Computing Systems. 14: 1-17. DOI: 10.1145/3132577  0.632
2018 Motaman S, Ghosh S, Kulkarni JP. VFAB: A Novel 2-Stage STTRAM Sensing Using Voltage Feedback and Boosting Ieee Transactions On Circuits and Systems I: Regular Papers. 65: 1919-1928. DOI: 10.1109/Tcsi.2017.2766058  0.673
2018 Kulkarni J, Wenisch TF. Report on the 2018 IEEE/ACM International Symposium on Low Power Electronics and Design Ieee Design & Test. 35: 94-95. DOI: 10.1109/Mdat.2018.2873454  0.326
2017 Cho M, Kim ST, Tokunaga C, Augustine C, Kulkarni JP, Ravichandran K, Tschanz JW, Khellah MM, De V. Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating Ieee Journal of Solid-State Circuits. 52: 50-63. DOI: 10.1109/Jssc.2016.2601319  0.66
2016 Srinivasa S, Aziz A, Shukla N, Li X, Sampson J, Datta S, Kulkarni JP, Narayanan V, Gupta SK. Correlated Material Enhanced SRAMs With Robust Low Power Operation Ieee Transactions On Electron Devices. 63: 4744-4752. DOI: 10.1109/Ted.2016.2621125  0.581
2016 Sharma A, Akkala AG, Kulkarni JP, Roy K. Source-Underlapped GaSb-InAs TFETs With Applications to Gain Cell Embedded DRAMs Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2016.2555627  0.582
2016 Kulkarni JP, Keane J, Koo KH, Nalam S, Guo Z, Karl E, Zhang K. 5.6 Mb/mm² 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology Ieee Journal of Solid-State Circuits. DOI: 10.1109/Jssc.2016.2607219  0.526
2016 Kulkarni JP, Tokunaga C, Aseron PA, Nguyen T, Augustine C, Tschanz JW, De V. A 409 GOPS/W adaptive and resilient domino register file in 22 nm tri-Gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging Ieee Journal of Solid-State Circuits. 51: 117-129. DOI: 10.1109/Jssc.2015.2463083  0.659
2016 Keane J, Kulkarni J, Koo KH, Nalam S, Guo Z, Karl E, Zhang K. 17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 59: 308-309. DOI: 10.1109/ISSCC.2016.7418030  0.38
2016 Cho M, Kim S, Tokunaga C, Augustine C, Kulkarni J, Ravichandran K, Tschanz J, Khellah M, De V. 8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 59: 152-153. DOI: 10.1109/ISSCC.2016.7417952  0.655
2015 Kim ST, Shih YC, Mazumdar K, Jain R, Ryan JF, Tokunaga C, Augustine C, Kulkarni JP, Ravichandran K, Tschanz JW, Khellah MM, De V. Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator Ieee Journal of Solid-State Circuits. DOI: 10.1109/Jssc.2015.2457920  0.659
2015 Kim ST, Shih YC, Mazumdar K, Jain R, Ryan JF, Tokunaga C, Augustine C, Kulkarni JP, Ravichandran K, Tschanz JW, Khellah MM, De V. Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 58: 154-155. DOI: 10.1109/ISSCC.2015.7062972  0.581
2015 Kulkarni JP, Tokunaga C, Aseron P, Nguyen T, Augustine C, Tschanz J, De V. A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 58: 82-83. DOI: 10.1109/ISSCC.2015.7062936  0.651
2014 Pandey R, Saripalli V, Kulkarni JP, Narayanan V, Datta S. Impact of single trap random telegraph noise on heterojunction TFET SRAM stability Ieee Electron Device Letters. 35: 393-395. DOI: 10.1109/Led.2014.2300193  0.408
2014 Jain R, Geuskens BM, Kim ST, Khellah MM, Kulkarni J, Tschanz JW, De V. A 0.45–1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS Ieee Journal of Solid-State Circuits. 49: 917-927. DOI: 10.1109/Jssc.2013.2297402  0.447
2014 Tokunaga C, Ryan JF, Augustine C, Kulkarni JP, Shih YC, Kim ST, Jain R, Bowman K, Raychowdhury A, Khellah MM, Tschanz JW, De V. 5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 57: 108-109. DOI: 10.1109/ISSCC.2014.6757359  0.655
2013 Gupta SK, Kulkarni JP, Roy K. Tri-mode independent gate finfet-based sram with pass-gate feedback: Technology-circuit co-design for enhanced cell stability Ieee Transactions On Electron Devices. 60: 3696-3704. DOI: 10.1109/Ted.2013.2283235  0.675
2013 Khan SM, Alameldeen AR, Wilkerson C, Kulkarni J, Jimenez DA. Improving multi-core performance using mixed-cell cache architecture Proceedings - International Symposium On High-Performance Computer Architecture. 119-130. DOI: 10.1109/HPCA.2013.6522312  0.304
2012 Kulkarni JP, Roy K. Ultralow-voltage process-variation-tolerant schmitt-trigger-based SRAM design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 319-332. DOI: 10.1109/Tvlsi.2010.2100834  0.644
2012 Gupta SK, Kulkarni JP, Datta S, Roy K. Heterojunction intra-band tunnel FETs for low-voltage SRAMs Ieee Transactions On Electron Devices. 59: 3533-3542. DOI: 10.1109/Ted.2012.2221127  0.624
2012 Gupta SK, Kulkarni JP, Datta S, Roy K. Dopant straggle-free heterojunction intra-band tunnel (HIBT) FETs with low drain-induced barrier lowering/thinning (DIBL/T) and reduced variation in off current Device Research Conference - Conference Digest, Drc. 55-56. DOI: 10.1109/DRC.2012.6257027  0.617
2011 Kulkarni JP, Goel A, Ndai P, Roy K. A read-disturb-free, differential sensing 1R/1W Port, 8T bitcell array Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1727-1730. DOI: 10.1109/Tvlsi.2010.2055169  0.772
2011 Saripalli V, Datta S, Narayanan V, Kulkarni JP. Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design Proceedings of the 2011 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2011. 45-52. DOI: 10.1109/NANOARCH.2011.5941482  0.407
2010 Kulkarni JP, Augustine C, Jung B, Roy K. Nano spiral inductors for low-power digital spintronic circuits Ieee Transactions On Magnetics. 46: 1898-1901. DOI: 10.1109/Tmag.2010.2046020  0.698
2010 Meterelliyoz M, Song P, Stellari F, Kulkarni JP, Roy K. Characterization of random process variations using ultralow-power, high-sensitivity, bias-free sub-threshold process sensor Ieee Transactions On Circuits and Systems I: Regular Papers. 57: 1838-1847. DOI: 10.1109/Tcsi.2009.2037449  0.766
2010 Meterelliyoz M, Kulkarni JP, Roy K. Analysis of SRAM and eDRAM cache memories under spatial temperature variations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 2-13. DOI: 10.1109/Tcad.2009.2035535  0.75
2010 Meterelliyoz M, Goel A, Kulkarni JP, Roy K. Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 53: 186-187. DOI: 10.1109/ISSCC.2010.5433991  0.783
2010 Raychowdhury A, Geuskens B, Kulkarni J, Tschanz J, Bowman K, Karnik T, Lu SL, De V, Khellah MM. PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 53: 352-353. DOI: 10.1109/ISSCC.2010.5433815  0.584
2010 Tschanz J, Bowman K, Khellah M, Wilkerson C, Geuskens B, Somasekhar D, Raychowdhury A, Kulkarni J, Tokunaga C, Lu SL, Karnik T, De V. Resilient design in scaled CMOS for energy efficiency Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 625. DOI: 10.1109/ASPDAC.2010.5419812  0.524
2010 Kulkarni JP, Roy K. Technology/circuit co-design for III-V FETs Fundamentals of Iii-V Semiconductor Mosfets. 423-441. DOI: 10.1007/978-1-4419-1547-4_14  0.5
2009 Goel A, Ndai P, Kulkarni JP, Roy K. REad/access-preferred (REAP) SRAM - Architecture-aware bit cell design for improved yield and lower V MIN Proceedings of the Custom Integrated Circuits Conference. 503-506. DOI: 10.1109/CICC.2009.5280794  0.762
2009 Roy K, Kulkarni JP, Gupta SK. Device/circuit interactions at 22nm technology node Proceedings - Design Automation Conference. 97-102.  0.611
2008 Cao Q, Kim HS, Pimparkar N, Kulkarni JP, Wang C, Shim M, Roy K, Alam MA, Rogers JA. Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates. Nature. 454: 495-500. PMID 18650920 DOI: 10.1038/nature07110  0.614
2008 Meterelliyoz M, Kulkarni JP, Roy K. Thermal analysis of 8-T SRAM for nano-scaled technologies Proceedings of the International Symposium On Low Power Electronics and Design. 123-128. DOI: 10.1145/1393921.1393953  0.758
2008 Kulkarni JP, Roy K. Technology circuit co-design for ultra fast InSb quantum well transistors Ieee Transactions On Electron Devices. 55: 2537-2545. DOI: 10.1109/Ted.2008.2003030  0.569
2008 Roy K, Kulkarni JP, Hwang ME. Process-tolerant ultralow voltage digital subthreshold design 2008 Ieee Topical Meeting On Silicon Monolithic Integrated Circuits in Rf Systms - Digest of Papers, Sirf. 42-45. DOI: 10.1109/SMIC.2008.17  0.533
2008 Kulkarni JP, Meterelliyoz M, Roy K, Murthy J. Nano-scaled SRAM thermal stability analysis using hierarchical compact thermal models 2008 11th Ieee Intersociety Conference On Thermal and Thermomechanical Phenomena in Electronic Systems, I-Therm. 999-1005. DOI: 10.1109/ITHERM.2008.4544375  0.751
2008 Kulkarni JP, Kim K, Park SP, Roy K. Process variation tolerant SRAM array for ultra low voltage applications Proceedings - Design Automation Conference. 108-113. DOI: 10.1109/DAC.2008.4555791  0.593
2008 Meterelliyoz M, Song P, Stellari F, Kulkarni JP, Roy K. A high sensitivity process variation sensor utilizing sub-threshold operation Proceedings of the Custom Integrated Circuits Conference. 125-128. DOI: 10.1109/CICC.2008.4672037  0.771
2007 Kulkarni JP, Kim K, Roy K. A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM Proceedings of the International Symposium On Low Power Electronics and Design. 171-176. DOI: 10.1145/1283780.1283818  0.557
2007 Kulkarni JP, Kim K, Roy K. A 160 mV robust schmitt trigger based subthreshold SRAM Ieee Journal of Solid-State Circuits. 42: 2303-2313. DOI: 10.1109/Jssc.2007.897148  0.611
2007 Kulkarni JP, Roy K. A high performance, scalable multiplexed keeper technique Proceedings - Eighth International Symposium On Quality Electronic Design, Isqed 2007. 545-549. DOI: 10.1109/ISQED.2007.14  0.437
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