Malgorzata Marek-Sadowska - Publications

Affiliations: 
Electrical & Computer Engineering University of California, Santa Barbara, Santa Barbara, CA, United States 
Area:
Electronics and Electrical Engineering

196 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2018 Yang P, Marek-Sadowska M. High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators Ieee Transactions On Very Large Scale Integration Systems. 26: 1209-1222. DOI: 10.1109/Tvlsi.2018.2814627  0.76
2016 Guan Z, Marek-Sadowska M. AFD-based method for signal line em reliability evaluation Proceedings - International Symposium On Quality Electronic Design, Isqed. 2016: 443-449. DOI: 10.1109/ISQED.2016.7479241  0.56
2015 Guan Z, Marek-Sadowska M. Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2501900  0.56
2015 Li DA, Marek-Sadowska M, Nassif SR. T-VEMA: A Temperature-and Variation-Aware Electromigration Power Grid Analysis Tool Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 2327-2331. DOI: 10.1109/Tvlsi.2014.2358678  1
2015 Qiu X, Marek-Sadowska M, Maly WP. Three-dimensional chips can be cool: Thermal study of VeSFET-based 3-D chips Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 869-878. DOI: 10.1109/Tvlsi.2014.2325551  1
2015 Li DA, Marek-Sadowska M, Nassif SR. A method for improving power grid resilience to electromigration-caused via failures Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 118-130. DOI: 10.1109/Tvlsi.2014.2301458  1
2015 Yang PL, Marek-Sadowska M, Maly W. Performance assessment of VeSFET-based SRAM Proceedings of the 2015 Ieee International Conference On Electron Devices and Solid-State Circuits, Edssc 2015. 79-82. DOI: 10.1109/EDSSC.2015.7285054  1
2015 Guan Z, Marek-Sadowska M. Atomic flux divergence-based AC electromigration model for signal line reliability assessment Proceedings - Electronic Components and Technology Conference. 2015: 2155-2161. DOI: 10.1109/ECTC.2015.7159901  1
2015 Li DA, Marek-Sadowska M, Nassif SR. Layout aware electromigration analysis of power/ground networks Circuit Design For Reliability. 145-173. DOI: 10.1007/978-1-4614-4078-9_8  1
2014 Nandakumar VS, Marek-Sadowska M. System-level floorplan-aware analysis of integrated CPU-GPUs Proceedings - Design Automation Conference. DOI: 10.1145/2593069.2593225  1
2014 Qiu X, Marek-Sadowska M, Maly WP. Characterizing VeSFET-based ICs with CMOS-Oriented EDA infrastructure Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 495-506. DOI: 10.1109/Tcad.2013.2293539  1
2014 Nandakumar VS, Marek-Sadowska M. On Optimal Kernel Size for Integrated CPU-GPUS - A Case Study Ieee Computer Architecture Letters. 13: 81-84. DOI: 10.1109/L-Ca.2013.27  1
2014 Li DA, Marek-Sadowska M. Estimating true worst currents for power grid electromigration analysis Proceedings - International Symposium On Quality Electronic Design, Isqed. 708-714. DOI: 10.1109/ISQED.2014.6783396  1
2014 Guan Z, Marek-Sadowska M, Nassif S. Statistical analysis of process variation induced SRAM electromigration degradation Proceedings - International Symposium On Quality Electronic Design, Isqed. 700-707. DOI: 10.1109/ISQED.2014.6783395  1
2014 Guan Z, Marek-Sadowska M, Nassif S, Li B. Atomic flux divergence based current conversion scheme for signal line electromigration reliability assessment 2014 Ieee International Interconnect Technology Conference / Advanced Metallization Conference, Iitc/Amc 2014. 245-248. DOI: 10.1109/IITC.2014.6831886  1
2013 Qiu X, Marek-Sadowska M, Maly W. Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure Proceedings of the International Symposium On Physical Design. 130-136. DOI: 10.1145/2451916.2451949  1
2013 Qiu X, Marek-Sadowska M. Routing challenges for designs with super high pin density Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1357-1368. DOI: 10.1109/Tcad.2013.2256462  1
2013 Guan Z, Marek-Sadowska M, Nassif S. SRAM bit-line electromigration mechanism and its prevention scheme Proceedings - International Symposium On Quality Electronic Design, Isqed. 287-293. DOI: 10.1109/ISQED.2013.6523624  1
2013 Qiu X, Marek-Sadowska M, Maly W. 3D Chips can be cool: Thermal study of VeSFET-based ICs Proceedings - Electronic Components and Technology Conference. 2349-2355. DOI: 10.1109/ECTC.2013.6575912  1
2012 Qiu X, Marek-Sadowska M. Can pin access limit the footprint scaling? Proceedings - Design Automation Conference. 1100-1106. DOI: 10.1145/2228360.2228560  1
2012 Wuu JY, Simmons M, Marek-Sadowska M. Layout optimization through robust pattern learning and prediction in SADP gridded designs Proceedings of Spie - the International Society For Optical Engineering. 8327. DOI: 10.1117/12.916583  1
2012 Nandakumar VS, Marek-Sadowska M. A low energy network-on-chip fabric for 3-D multi-core architectures Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 2: 266-277. DOI: 10.1109/Jetcas.2012.2193834  1
2012 Qiu X, Marek-Sadowska M, Maly W. Vertical slit field effect transistor in ultra-low power applications Proceedings - International Symposium On Quality Electronic Design, Isqed. 384-390. DOI: 10.1109/ISQED.2012.6187522  1
2012 Wuu JY, Simmons M, Marek-Sadowska M. Post-placement lithographic hotspot detection and removal in one-dimensional gridded designs Proceedings - International Symposium On Quality Electronic Design, Isqed. 193-199. DOI: 10.1109/ISQED.2012.6187494  1
2011 Marek-Sadowska M. On old and new routing problems Proceedings of the International Symposium On Physical Design. 13-20. DOI: 10.1145/1960397.1960404  1
2011 Wuu JY, Pikus FG, Marek-Sadowska M. Efficient approach to early detection of lithographic hotspots using machine learning systems and pattern matching Proceedings of Spie - the International Society For Optical Engineering. 7974. DOI: 10.1117/12.879546  1
2011 Todri A, Marek-Sadowska M. Power delivery for multicore systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 2243-2255. DOI: 10.1109/Tvlsi.2010.2080694  1
2011 Su YS, Wang DC, Chang SC, Marek-Sadowska M. Performance optimization using variable-latency design style Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1874-1883. DOI: 10.1109/Tvlsi.2010.2058874  1
2011 Todri A, Marek-Sadowska M. Reliability analysis and optimization of power-gated ICs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 457-468. DOI: 10.1109/Tvlsi.2009.2036267  1
2011 Lin YW, Marek-Sadowska M, Maly WP. On cell layout-performance relationships in VeSFET-based, high-density regular circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 229-241. DOI: 10.1109/Tcad.2010.2097191  1
2011 Wuu JY, Pikus FG, Marek-Sadowska M. Metrics for characterizing machine learning-based hotspot detection methods Proceedings of the 12th International Symposium On Quality Electronic Design, Isqed 2011. 116-121. DOI: 10.1109/ISQED.2011.5770713  1
2011 Nandakumar VS, Marek-Sadowska M. Low power, high throughput network-on-chip fabric for 3D multicore processors Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 453-454. DOI: 10.1109/ICCD.2011.6081458  1
2011 Li DA, Marek-Sadowska M. Variation-aware electromigration analysis of power/ground networks Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 571-576. DOI: 10.1109/ICCAD.2011.6105387  1
2011 Wuu JY, Pikus FG, Torres A, Marek-Sadowska M. Rapid layout pattern classification Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 781-786. DOI: 10.1109/ASPDAC.2011.5722295  1
2011 Marek-Sadowska M, Qiu X. A study on cell-level routing for VeSFET circuits Proceedings of the 18th International Conference - Mixed Design of Integrated Circuits and Systems, Mixdes 2011. 127-132.  1
2011 Nandakumar VS, Marek-Sadowska M. Layout effects in fine grain 3D integrated regular microprocessor blocks Proceedings - Design Automation Conference. 639-644.  1
2011 Wuu JY, Pikus FG, Torres A, Marek-Sadowska M. Using machine learning systems for early lithographic hotspot prediction Designcon 2011. 2: 982-1002.  1
2011 Maly W, Singh N, Chen Z, Shen N, Li X, Pfitzner A, Kasprowicz D, Kuzmicz W, Lin YW, Marek-Sadowska M. Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration Proceedings of the 18th International Conference - Mixed Design of Integrated Circuits and Systems, Mixdes 2011. 145-150.  1
2010 Li DA, Marek-Sadowska M, Lee B. On-chip EM-sensitive interconnect structures International Workshop On System Level Interconnect Prediction, Slip. 43-50. DOI: 10.1145/1811100.1811112  1
2010 Lin YW, Marek-Sadowska M, Maly W. Performance study of VeSFET-based, high-density regular circuits Proceedings of the International Symposium On Physical Design. 161-168. DOI: 10.1145/1735023.1735062  1
2010 Lin YW, Marek-Sadowska M, Maly WP. Layout generator for transistor-level high-density regular circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 197-210. DOI: 10.1109/Tcad.2009.2035580  1
2010 Nandakumar VS, Newmark D, Zhan Y, Marek-Sadowska M. Statistical static timing analysis flow for transistor level macros in a microprocessor Proceedings of the 11th International Symposium On Quality Electronic Design, Isqed 2010. 163-170. DOI: 10.1109/ISQED.2010.5450412  1
2009 Todri A, Marek-Sadowska M. Electromigration study of power-gated grids Proceedings of the International Symposium On Low Power Electronics and Design. 311-314. DOI: 10.1145/1594233.1594311  1
2009 Lin YW, Marek-Sadowska M, Maly W. Transistor-level layout of high-density regular circuits Proceedings of the International Symposium On Physical Design. 83-90. DOI: 10.1145/1514932.1514954  1
2009 Wuu JY, Pikus FG, Torres A, Marek-Sadowska M. Detecting context sensitive hot spots in standard cell libraries Proceedings of Spie - the International Society For Optical Engineering. 7275. DOI: 10.1117/12.814316  1
2009 Kuo YM, Chang YT, Chang SC, Marek-Sadowska M. Spare cells with constant insertion for engineering change Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 456-460. DOI: 10.1109/Tcad.2009.2013537  1
2009 Mehta VJ, Marek-Sadowska M, Tsai KH, Rajski J. Timing-aware multiple-delay-fault diagnosis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 245-258. DOI: 10.1109/Tcad.2008.2009164  1
2009 Mehta VJ, Marek-Sadowska M, Tsai KH, Rajski J. Timing-aware multiple-delay-fault diagnosis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 245-258. DOI: 10.1109/TCAD.2008.2009164  1
2009 Todri A, Marek-Sadowska M, Maire F, Matheron C. A study of decoupling capacitor effectiveness in power and ground grid networks Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 653-658. DOI: 10.1109/ISQED.2009.4810371  1
2008 Wuu JY, Pikus FG, Marek-Sadowska M. Fast and simple modeling of non-rectangular transistors Proceedings of Spie - the International Society For Optical Engineering. 7122. DOI: 10.1117/12.801541  1
2008 Mehta VJ, Marek-Sadowska M, Tsai KH, Rajski J. Improving the resolution of single-delay-fault diagnosis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 932-945. DOI: 10.1109/Tcad.2008.917588  1
2008 Modi NA, Marek-Sadowska M. ECO-Map: Technology remapping for post-mask ECO using simulated annealing 26th Ieee International Conference On Computer Design 2008, Iccd. 652-657. DOI: 10.1109/ICCD.2008.4751930  1
2008 Lin YW, Marek-Sadowska M, Maly W, Pfitzner A, Kasprowicz D. Is there always performance overhead for regular fabric? 26th Ieee International Conference On Computer Design 2008, Iccd. 557-562. DOI: 10.1109/ICCD.2008.4751916  1
2008 Weng SH, Kuo YM, Chang SC, Marek-Sadowska M. Timing analysis considering IR drop waveforms in power gating designs 26th Ieee International Conference On Computer Design 2008, Iccd. 532-537. DOI: 10.1109/ICCD.2008.4751912  1
2008 Todri A, Marek-Sadowska M. A study of reliability issues in clock distribution networks 26th Ieee International Conference On Computer Design 2008, Iccd. 101-106. DOI: 10.1109/ICCD.2008.4751847  1
2008 Todri A, Marek-Sadowska M, Kozhaya J. Power supply noise aware workload assignment for multi-core systems Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 330-337. DOI: 10.1109/ICCAD.2008.4681594  1
2008 Jiang H, Marek-Sadowska M. Power gating scheduling for power/ground noise reduction Proceedings - Design Automation Conference. 980-985. DOI: 10.1109/DAC.2008.4555962  1
2007 Todri A, Chang SC, Marek-Sadowska M. Electromigration and voltage drop aware power grid optimization for power gated ICs Proceedings of the International Symposium On Low Power Electronics and Design. 391-394. DOI: 10.1145/1283780.1283866  1
2007 Mehta VJ, Marek-Sadowska M, Tsai KH, Rajski J. Timing defect diagnosis in presence of crosstalk for nanometer technology Proceedings - International Test Conference. DOI: 10.1109/TEST.2006.297626  1
2007 Jiang H, Marek-Sadowska M. Power-gating aware floorplanning Proceedings - Eighth International Symposium On Quality Electronic Design, Isqed 2007. 853-858. DOI: 10.1109/ISQED.2007.123  1
2007 Todri A, Marek-Sadowska M, Chang SC. Analysis and optimization of power-gated ICs with multiple power gating configurations Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 783-790. DOI: 10.1109/ICCAD.2007.4397361  1
2007 Kuo YM, Chang YT, Chang SC, Marek-Sadowska M. Engineering change using spare cells with constant insertion Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 544-547. DOI: 10.1109/ICCAD.2007.4397321  1
2007 Su YS, Wang DC, Chang SC, Marek-Sadowska M. An efficient mechanism for performance optimization of variable-latency designs Proceedings - Design Automation Conference. 976-981. DOI: 10.1109/DAC.2007.375307  1
2007 Maly W, Lin YW, Marek-Sadowska M. OPC-free and minimally irregular IC design style Proceedings - Design Automation Conference. 954-957. DOI: 10.1109/DAC.2007.375302  1
2007 Chang CW(), Marek-Sadowska M. Theory of wire addition and removal in combinational Boolean networks Microelectronic Engineering. 84: 229-243. DOI: 10.1016/J.Mee.2006.02.017  1
2006 Ran Y, Marek-Sadowska M. Via-configurable routing architectures and fast design mappability estimation for regular fabrics Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 998-1009. DOI: 10.1109/Tvlsi.2006.884051  1
2006 Ran Y, Marek-Sadowska M. Designing via-configurable logic blocks for regular fabric Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 1-14. DOI: 10.1109/Tvlsi.2005.863196  1
2006 Liu Q, Marek-Sadowska M. Semi-individual wire-length prediction with application to logic synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 611-624. DOI: 10.1109/Tcad.2005.859487  1
2006 Wang Z, Tsai KH, Rajski J. Analysis and methodology for multiple-fault diagnosis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 558-575. DOI: 10.1109/Tcad.2005.854624  0.52
2006 Mehta VJ, Wang Z, Marek-Sadowska M, Tsai KH, Rajski J. Delay fault diagnosis for nonrobust test Proceedings - International Symposium On Quality Electronic Design, Isqed. 463-472. DOI: 10.1109/ISQED.2006.45  1
2006 Tsai CK, Marek-Sadowska M. Analysis of process variation's effect on SRAM's read stability Proceedings - International Symposium On Quality Electronic Design, Isqed. 603-610. DOI: 10.1109/ISQED.2006.26  1
2006 Jiang H, Marek-Sadowska M. Power/ground supply network optimization for power-gating Ieee International Conference On Computer Design, Iccd 2006. 332-337. DOI: 10.1109/ICCD.2006.4380837  1
2005 Wang Z, Marek-Sadowska MM, Tsai KH, Rajski J. Delay-fault diagnosis using timing information Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1315-1325. DOI: 10.1109/Tcad.2005.852062  1
2005 Ran Y, Kondratyev A, Tseng KH, Watanabe Y, Marek-Sadowska M. Eliminating false positives in crosstalk noise analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1406-1419. DOI: 10.1109/Tcad.2005.850829  1
2005 Hu B, Marek-Sadowska M. Multilevel fixed-point-addition-based VLSI placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1188-1203. DOI: 10.1109/Tcad.2005.850802  1
2005 Liu Q, Marek-Sadowska M. A study of netlist structure and placement efficiency Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 762-772. DOI: 10.1109/Tcad.2005.846364  1
2005 Wang K, Ran Y, Jiang H, Marek-Sadowska M. General skew constrained clock network sizing based on sequential linear programming Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 773-781. DOI: 10.1109/Tcad.2005.846362  1
2005 Wang K, Marek-Sadowska M. On-chip power-supply network optimization using multigrid-based technique Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 407-417. DOI: 10.1109/Tcad.2004.842802  1
2005 Tsai CK, Marek-Sadowska M. An interconnect insensitive linear time-varying driver model for static timing analysis Proceedings - International Symposium On Quality Electronic Design, Isqed. 654-661. DOI: 10.1109/ISQED.2005.16  1
2005 Liu Q, Marek-Sadowska M. Pre-layout physical connectivity prediction with application in clustering-based placement Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 31-37. DOI: 10.1109/ICCD.2005.86  1
2005 Jiang H, Marek-Sadowska M, Nassif SR. Benefits and costs of power-gating technique Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 559-566. DOI: 10.1109/ICCD.2005.34  1
2005 Yeh CY, Marek-Sadowska M. Timing-aware power noise reduction in layout Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 626-633. DOI: 10.1109/ICCAD.2005.1560143  1
2005 Yeh CY, Marek-Sadowska M. Skew-programmable clock design for FPGA and skew-aware placement Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 33-40.  1
2005 Liu Q, Marek-Sadowska M. A congestion-driven placement framework with local congestion prediction Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 488-493.  1
2005 Liu Q, Marek-Sadowska M. Wire length prediction-based technology mapping and fanout optimization Proceedings of the International Symposium On Physical Design. 145-151.  1
2005 Hu B, Zeng V, Marek-Sadowska M. MFAR: Fixed-points-addition-based VLSI placement algorithm Proceedings of the International Symposium On Physical Design. 239-241.  1
2005 Jiang H, Wang K, Marek-Sadowska M. Clock skew bounds estimation under power supply and process variations Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 332-336.  1
2004 Liu Q, Hu B, Marek-Sadowska M. Individual wire-length prediction with application to timing-driven placement Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 1004-1014. DOI: 10.1109/Tvlsi.2004.834234  1
2004 Yeh CY, Marek-Sadowska M. Sequential delay budgeting with interconnect prediction Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 1028-1037. DOI: 10.1109/Tvlsi.2004.827563  1
2004 Hu B, Marek-Sadowska M. Fine Granularity Clustering-Based Placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 527-536. DOI: 10.1109/Tcad.2004.825868  1
2004 Chang CW, Hsiao MF, Hu B, Wang K, Marek-Sadowska M, Cheng CK, Chen SJ. Fast Postplacement Optimization Using Functional Symmetries Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 102-118. DOI: 10.1109/Tcad.2003.819904  1
2004 Macchiarulo L, Shu SM, Marek-Sadowska M. Pipelining sequential circuits with wave steering Ieee Transactions On Computers. 53: 1205-1210. DOI: 10.1109/Tc.2004.65  1
2004 Ran Y, Marek-Sadowska M. An integrated design flow for a via-configurable gate array Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 582-589. DOI: 10.1109/ICCAD.2004.1382644  1
2004 Ran Y, Marek-Sadowska M. On designing via-configurable cell blocks for regular fabrics Proceedings - Design Automation Conference. 198-203. DOI: 10.1109/DAC.2004.240257  1
2004 Ran Y, Marek-Sadowska M. The magic of a via-configurable regular fabric Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 338-343.  1
2004 Ran Y, Marek-Sadowska M. Designing a via-configurable regular fabric Proceedings of the Custom Integrated Circuits Conference. 423-426.  1
2004 Wang K, Marek-Sadowska M. Buffer sizing for clock power minimization subject to general skew constraints Proceedings - Design Automation Conference. 159-164.  1
2004 Wang K, Marek-Sadowska M. Potential slack budgeting with clock skew optimization Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 265-271.  1
2004 Wang K, Marek-Sadowska M. Clock network sizing via sequential linear programming with time-domain analysis Proceedings of the International Symposium On Physical Design. 182-189.  1
2004 Hu B, Marek-Sadowska M. Multilevel expansion-based VLSI placement with blockages Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 558-564.  1
2004 Liu Q, Marek-Sadowska M. Pre-layout wire length and congestion estimation Proceedings - Design Automation Conference. 582-587.  1
2004 Wang Z, Marek-Sadowska M, Tsai KH, Rajski J. Delay fault diagnosis using timing information Proceedings - 5th International Symposium On Quality Electronic Design, Isqued 2004. 485-490.  1
2004 Wang Z, Marek-Sadowska M, Tsai KH, Rajski J. Diagnosis of hold time defects Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 192-199.  1
2003 Chen LH, Marek-Sadowska M, Brewer F. Buffer delay change in the presence of power and ground noise Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 461-473. DOI: 10.1109/Tvlsi.2003.812310  1
2003 Mukherjee A, Marek-Sadowska M. Wave steering to integrate logic and physical syntheses Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 105-120. DOI: 10.1109/Tvlsi.2003.811100  1
2003 Singh A, Mukherjee A, Macchiarulo L, Marek-Sadowska M. PITIA: An FPGA for throughput-intensive applications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 354-363. DOI: 10.1109/Tvlsi.2003.810780  1
2003 Chang CWJ, Hsiao MF, Marek-Sadowska M. A new reasoning scheme for efficient redundancy addition and removal Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 945-952. DOI: 10.1109/Tcad.2003.814239  1
2003 Mukherjee A, Marek-Sadowska M. Clock and power gating with timing closure Ieee Design and Test of Computers. 20: 32-39. DOI: 10.1109/Mdt.2003.1198683  1
2003 Hsiao MF, Marek-Sadowska M, Chen SJ. Minimizing inter-clock coupling jitter Proceedings - International Symposium On Quality Electronic Design, Isqed. 2003: 333-338. DOI: 10.1109/ISQED.2003.1194754  1
2003 Tsai CK, Marek-Sadowska M. Modeling crosstalk induced delay Proceedings - International Symposium On Quality Electronic Design, Isqed. 2003: 189-194. DOI: 10.1109/ISQED.2003.1194730  1
2003 Wang K, Marek-Sadowska M. Power/ground mesh area optimization using multigrid-based technique [IC design] Proceedings -Design, Automation and Test in Europe, Date. 850-855. DOI: 10.1109/DATE.2003.1253712  1
2003 Chen LH, Marek-Sadowska M. Closed-form crosstalk noise delay metrics Analog Integrated Circuits and Signal Processing. 35: 143-156. DOI: 10.1023/A:1024126531872  1
2003 Yeh CY, Marek-Sadowska M. Minimum-Area Sequential Budgeting for FPGA Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 813-817.  1
2003 Yeh CY, Marek-Sadowska M. Delay budgeting in sequential circuit with application on FPGA placement Proceedings - Design Automation Conference. 202-207.  1
2003 Hu B, Marek-Sadowska M. Fine granularity clustering for large scale placement problems Proceedings of the International Symposium On Physical Design. 67-74.  1
2003 Ran Y, Marek-Sadowska M. Crosstalk noise in FPGAs Proceedings - Design Automation Conference. 944-949.  1
2003 Wang K, Marek-Sadowska M. On-chip power supply network optimization using multigrid-based technique Proceedings - Design Automation Conference. 113-118.  1
2003 Hu B, Marek-Sadowska M. Wire length prediction based clustering and its application in placement Proceedings - Design Automation Conference. 800-805.  1
2003 Hsiao MF, Marek-Sadowska M, Chen SJ. Minimizing coupling jitter by buffer resizing for coupled clock networks Proceedings - Ieee International Symposium On Circuits and Systems. 5: V509-V512.  1
2003 Hsiao MF, Marek-Sadowska M, Chen SJ. A crosstalk aware two-pin net router Proceedings - Ieee International Symposium On Circuits and Systems. 5: V485-V488.  1
2003 Wang Z, Tsai KH, Marek-Sadowska M, Rajski J. An Efficient and Effective Methodology on the Multiple Fault Diagnosis Ieee International Test Conference (Tc). 329-338.  1
2003 Liu Q, Hu B, Marek-Sadowska M. Wire Length Prediction in Constraint Driven Placement International Workshop On System Level Interconnect Prediction. 99-105.  1
2003 Hu B, Jiang H, Liu Q, Marek-Sadowska M. Synthesis and placement flow for gain-based programmable regular fabrics Proceedings of the International Symposium On Physical Design. 197-203.  1
2003 Hu B, Watanabe Y, Kondratyev A, Marek-Sadowska M. Gain-based technology mapping for discrete-size cell libraries Proceedings - Design Automation Conference. 574-579.  1
2003 Wang Z, Marek-Sadowska M, Tsai KH, Rajski J. Multiple fault diagnosis using n-detection tests Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 198-201.  1
2003 Chai D, Kondratyev A, Ran Y, Tseng KH, Watanabe Y, Marek-Sadowska M. Temporofunctional crosstalk noise analysis Proceedings - Design Automation Conference. 860-863.  1
2002 Chang CWJ, Marek-Sadowska M. ATPG-based logic synthesis: An overview Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 786-789. DOI: 10.1145/774572.774688  1
2002 Hu B, Marek-Sadowska M. Congestion minimization during placement without estimation Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 739-745. DOI: 10.1145/774572.774681  1
2002 Singh A, Parthasarathy G, Marek-Sadowska M. Efficient circuit clustering for area and power reduction in FPGAs Acm Transactions On Design Automation of Electronic Systems. 7: 643-663. DOI: 10.1145/605440.605448  1
2002 Chen LH, Marek-Sadowska M. Efficient closed-form crosstalk delay metrics Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 431-436. DOI: 10.1109/ISQED.2002.996784  1
2002 Chen LH, Marek-Sadowska M. Closed-form crosstalk noise metrics for physical design applications Proceedings -Design, Automation and Test in Europe, Date. 812-819. DOI: 10.1109/DATE.2002.998392  1
2002 Mukherjee A, Wang K, Hui Chen L, Marek-Sadowska M. Sizing power/ground meshes for clocking and computing circuit components Proceedings -Design, Automation and Test in Europe, Date. 176-183. DOI: 10.1109/DATE.2002.998267  1
2002 Xiao T, Marek-Sadowska M. Using temporal and functional information in crosstalk aware static timing analysis Vlsi Design. 15: 647-666. DOI: 10.1080/1065514021000012264  1
2002 Hu B, Marek-Sadowska M. FAR: Fixed-points addition & relaxation based placement Proceedings of the International Symposium On Physical Design. 161-166.  1
2002 Singh A, Marek-Sadowska M. Efficient circuit clustering for area and power reduction in FPGAs Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 59-66.  1
2002 Chen LH, Marek-Sadowska M. Incremental delay change due to crosstalk noise Proceedings of the International Symposium On Physical Design. 120-125.  1
2002 Chen LH, Marek-Sadowska M, Brewer F. Coping with buffer delay change due to power and ground noise Proceedings - Design Automation Conference. 860-865.  1
2002 Singh A, Marek-Sadowska M. FPGA Interconnect Planning International Workshop On System Level Interconnect Prediction. 23-30.  1
2002 Hsiao MF, Marek-Sadowska M, Chen SJ. Crosstalk minimization for multiple clock tree routing Midwest Symposium On Circuits and Systems. 1: I152-I155.  1
2001 Funabiki N, Singh A, Mukherjee A, Marek-Sadowska M. A global routing technique for wave-steered design methodology Proceedings - Euromicro Symposium On Digital Systems Design: Architectures, Methods and Tools, Dsd 2001. 430-436. DOI: 10.1109/DSD.2001.952358  1
2001 Chang CW, Hu B, Marek-Sadowska M. In-place delay constrained power optimization using functional symmetries Proceedings -Design, Automation and Test in Europe, Date. 377-382. DOI: 10.1109/DATE.2001.915052  1
2001 Chen LH, Marek-Sadowska M. Aggressor alignment for worst-case crosstalk noise Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 612-621. DOI: 10.1109/43.920689  1
2001 Xiao T, Marek-Sadowska M. Functional correlation analysis in crosstalk induced critical paths identification Proceedings - Design Automation Conference. 653-656.  1
2001 Xiao T, Marek-Sadowska M. Gate sizing to eliminate crosstalk induced timing violation Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 186-191.  1
2001 Chang CW, Marek-Sadowska M. Single-pass redundancy addition and removal Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 606-609.  1
2001 Chang CW, Marek-Sadowska M. Who are the alternative wires in your neighborhood? (Alternative wires identification without search) Proceedings of the Ieee Great Lakes Symposium On Vlsi. 103-108.  1
2001 Chang CW, Wang K, Marek-Sadowska M. Layout-driven hot-carrier degradation minimization using logic restructuring techniques Proceedings - Design Automation Conference. 97-102.  1
2001 Singh A, Mukherjee A, Marek-Sadowska M. Latency and latch count minimization in Wave Steered circuits Proceedings - Design Automation Conference. 383-388.  1
2001 Singh A, Parthasarathy G, Marek-Sadowska M. Interconnect resource-aware placement for hierarchical FPGAs Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 132-136.  1
2001 Singh A, Mukherjee A, Marek-Sadowska M. Interconnect pipelining in a throughput-intensive FPGA architecture Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 153-160.  1
2001 Parthasarathy G, Marek-Sadowska M, Mukherjee A, Singh A. Interconnect complexity-aware FPGA placement using Rent's rule 2001 International Workshop On System-Level Interconnect Prediction (Slip 2001). 115-121.  1
2000 Xiao T, Marek-Sadowska M. Efficient delay calculation in presence of crosstalk Proceedings - International Symposium On Quality Electronic Design, Isqed. 2000: 491-498. DOI: 10.1109/ISQED.2000.838932  1
2000 Macchiarulo L, Shu SM, Marek-Sadowska M. Wave steered FSMs Proceedings -Design, Automation and Test in Europe, Date. 270-276. DOI: 10.1109/DATE.2000.840283  1
2000 Tsai K, Rajski J, Marek-Sadowska M. Star test: the theory and its applications Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 1052-1064. DOI: 10.1109/43.863645  0.68
2000 Wu YL, Fan H, Marek-Sadowska M, Wong CK. OBDD minimization based on two-level representation of Boolean functions Ieee Transactions On Computers. 49: 1371-1379. DOI: 10.1109/12.895868  1
1999 Vittal A, Chen LH, Marek-Sadowska M, Wang KP, Yang S. Crosstalk in VLSI interconnections Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1817-1824. DOI: 10.1109/43.811330  1
1999 Lin CC, Chen KC, Marek-Sadowska M. Logic synthesis for engineering change Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 282-292. DOI: 10.1109/43.748158  1
1999 Chang SC, Van Ginneken LPPP, Marek-Sadowska M. Circuit optimization by rewiring Ieee Transactions On Computers. 48: 962-970. DOI: 10.1109/12.795224  1
1999 Chang D, Marek-Sadowska M. Partitioning sequential circuits on dynamically reconfigurable FPGAs Ieee Transactions On Computers. 48: 565-578. DOI: 10.1109/12.773794  1
1999 Mukherjee A, Marek-Sadowska M, Long SI. Wave pipelining YADDs - a feasibility study Proceedings of the Custom Integrated Circuits Conference. 559-562.  1
1999 Tsai KH, Tompson R, Rajski J, Marek-Sadowska M. STAR-ATPG: a high speed test pattern generator for large scan designs Ieee International Test Conference (Tc). 1021-1030.  1
1998 Vittal A, Marek-Sadowska M. Power distribution synthesis for VLSI Vlsi Design. 7: 59-72. DOI: 10.1155/1998/76525  1
1998 Chang D, Lee MTC, Cheng KT, Marek-Sadowska M. Functional scan chain testing Proceedings -Design, Automation and Test in Europe, Date. 278-283. DOI: 10.1109/DATE.1998.655868  1
1998 Lin CC, Marek-Sadowska M, Lee MTC, Chen KC. Cost-free scan: a low-overhead scan path design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 852-861. DOI: 10.1109/43.720320  1
1998 Lin CC, Marek-Sadowska M, Cheng KT, Lee MTC. Test-point insertion: scan paths through functional logic Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 838-851. DOI: 10.1109/43.720319  1
1998 Cheng DI, Cheng KT, Wang DC, Marek-Sadowska M. A hybrid methodology for switching activities estimation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 357-366. DOI: 10.1109/43.703825  1
1998 Wu Yu-Liang, Chang D, Marek-Sadowska M, Tsukiyama S. On improved fpga greedy routing architectures Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 2485-2491.  1
1997 Vittal A, Marek-Sadowska M. Low-power buffered clock tree design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 965-975. DOI: 10.1109/43.658565  1
1997 Chang SC, Cheng KT, Woo NS, Marek-Sadowska M. Postlayout logic restructuring using alternative wires Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 587-596. DOI: 10.1109/43.640617  1
1997 Lin CC, Marek-Sadowska M, Fellow, Gatlin D. On designing universal logic blocks and their application to FPGA design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 519-527. DOI: 10.1109/43.631214  1
1997 Wu YL, Marek-Sadowska M. Routing for array-type FPGA's Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 506-518. DOI: 10.1109/43.631213  1
1997 Vittal A, Marek-Sadowska M. Crosstalk reduction for VLSI Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 290-298. DOI: 10.1109/43.594834  1
1997 Tsai CC, Marek-Sadowska M. Boolean functions classification via fixed polarity Reed-Muller forms Ieee Transactions On Computers. 46: 173-186. DOI: 10.1109/12.565592  1
1997 Wu YL, Marek-Sadowska M. On regular segmented 2-D FPGA routing Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 1871-1876.  1
1997 Tsai KH, Hellebrand S, Rajski J, Marek-Sadowska M. STARBIST: scan autocorrelated random pattern generation Proceedings - Design Automation Conference. 472-477.  1
1997 Grygiel S, Perkowski M, Marek-Sadowska M, Luba T, Jozwiak L. Cube diagram bundles: a new representation of strongly unspecified multiple-valued functions and relations Proceedings of the International Symposium On Multiple-Valued Logic. 287-292.  1
1996 Chang SC, Marek-Sadowska M, Cheng KT. Perturb and simplify: multilevel boolean network optimizer Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 1494-1504. DOI: 10.1109/43.552082  1
1996 Chang SC, Marek-Sadowska M, Hwang T. Technology mapping for TLU FPGA's based on decomposition of binary decision diagrams Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 1226-1236. DOI: 10.1109/43.541442  1
1996 Wu YL, Tsukiyama S, Marek-Sadowska M. Graph based analysis of 2-D FPGA routing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 33-44. DOI: 10.1109/43.486270  1
1996 Tsai CC, Marek-Sadowska M. Generalized Reed-Muller forms as a tool to detect symmetries Ieee Transactions On Computers. 45: 33-40. DOI: 10.1109/12.481484  1
1996 Tsai CC, Marek-Sadowska M. Logic synthesis for testability Proceedings of the Ieee Great Lakes Symposium On Vlsi. 118-121.  1
1995 Marek-Sadowska M, Sarrafzadeh M. The Crossing Distribution Problem Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 423-433. DOI: 10.1109/43.372368  1
1994 Cheng DI, Marek-Sadowska M. On The Verification Of Function Equivalence With Unknown Input Correspondence Journal of Circuits, Systems, and Computers. 4: 223-241. DOI: 10.1142/S0218126694000132  1
1994 Tsai CC, Marek-Sadowska M. Minimization of fixed-polarity AND/XOR canonical networks Iee Proceedings: Computers and Digital Techniques. 141: 369-374. DOI: 10.1049/ip-cdt:19941505  1
1993 Lin S, Kuh ES, Marek-Sadowska M. Stepwise Equivalent Conductance Circuit Simulation Technique Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 672-683. DOI: 10.1109/43.277612  1
1992 Marek-Sadowska M. Switch box routing: a retrospective Integration, the Vlsi Journal. 13: 39-65. DOI: 10.1016/0167-9260(92)90017-S  1
1992 Lin S, Marek-Sadowska M, Kuh ES. SWEC: A step wise equivalent conductance timing simulator for CMOS VLSI circuits . 142-148.  1
1990 Lin S, Marek-Sadowska M, Kuh ES. Delay and area optimization in standard-cell design 27th Acm/Ieee Design Automation Conference. Proceedings 1990. 349-352.  1
1987 Marek-Sadowska M. Pad Assignment for Power Nets in VLSI Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 6: 550-560. DOI: 10.1109/Tcad.1987.1270302  1
1987 Jackson MAB, Kuh ES, Marek-Sadowska M. TIMING-DRIVEN ROUTING FOR BUILDING BLOCK LAYOUT Proceedings - Ieee International Symposium On Circuits and Systems. 518-519.  1
1984 Li JT, Marek-Sadowska M. Global Routing for Gate Array Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 3: 298-307. DOI: 10.1109/Tcad.1984.1270088  1
1984 Marek-Sadowska M. An Unconstrained Topological Via Minimization Problem for Two-Layer Routing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 3: 184-190. DOI: 10.1109/Tcad.1984.1270074  1
1984 Tarng TTK, Marek-Sadowska M, Kuh ES. An Efficient Single-Row Routing Algorithm Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 3: 178-183. DOI: 10.1109/Tcad.1984.1270073  1
1983 Marek-Sadowska M, Tarng TTK. Single-Layer Routing for VLSI: Analysis and Algorithms Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 2: 246-259. DOI: 10.1109/Tcad.1983.1270042  0.56
1983 Kuzmicz W, Maly W, Marek-Sadowska M, Kozminski K. CAD SYSTEM FOR AUTOMATED THICK FILM HYBRID IC LAYOUT DESIGN . 44-45.  0.32
1981 Marek-Sadowska M, Kuh ES. NEW APPROACH TO ROUTING OF TWO-LAYER PRINTED CIRCUIT BOARD International Journal of Circuit Theory and Applications. 9: 331-341. DOI: 10.1002/Cta.4490090307  1
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