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Alex Orailoglu - Publications

Affiliations: 
Computer Science and Engineering University of California, San Diego, La Jolla, CA 
Area:
Computer Science
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146 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Badawi D, Ayhan T, Ozev S, Yang C, Orailoglu A, Çetin AE. Detecting Gas Vapor Leaks Using Uncalibrated Sensors Ieee Access. 7: 155701-155710. DOI: 10.1109/Access.2019.2949740  0.594
2016 Arslan B, Orailoglu A. Aggressive Test Cost Reductions Through Continuous Test Effectiveness Assessment Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 2093-2103. DOI: 10.1109/Tcad.2016.2535902  0.663
2016 Arslan B, Orailoglu A. Power-Aware Delay Test Quality Optimization for Multiple Frequency Domains Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 141-154. DOI: 10.1109/Tcad.2015.2448689  0.665
2015 Zhao M, Orailoglu A, Xue CJ. Joint profit and process variation aware high level synthesis with speed binning Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 1640-1650. DOI: 10.1109/Tvlsi.2014.2349493  0.353
2015 Bournoutian G, Orailoglu A. Mobile ecosystem driven application-specific low-power control microarchitecture Proceedings of the 33rd Ieee International Conference On Computer Design, Iccd 2015. 720-727. DOI: 10.1109/ICCD.2015.7357186  0.8
2015 Bournoutian G, Orailoglu A. Mobile ecosystem driven dynamic pipeline adaptation for low power Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 9017: 83-95. DOI: 10.1007/978-3-319-16086-3_7  0.809
2014 Bournoutian G, Orailoglu A. On-device objective-C application optimization framework for high-performance mobile processors Proceedings -Design, Automation and Test in Europe, Date. DOI: 10.7873/DATE2014.098  0.781
2014 Chen M, Orailoglu A. Examining timing path robustness under wide-bandwidth power supply noise through multi-functional-cycle delay test Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 734-746. DOI: 10.1109/Tvlsi.2013.2256810  0.421
2013 Qiu K, Zhao M, Xue CJ, Orailoglu A. Branch Prediction directed Dynamic instruction Cache Locking for embedded systems 2013 Ieee 19th International Conference On Embedded and Real-Time Computing Systems and Applications, Rtcsa 2013. 209-216. DOI: 10.1145/2660492  0.362
2013 Bournoutian G, Orailoglu A. Application-aware adaptive cache architecture for power-sensitive mobile processors Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2539036.2539037  0.807
2013 Paseman R, Orailoglu A. Towards a cost-effective hardware trojan detection methodology Proceedings of the Ieee Vlsi Test Symposium. DOI: 10.1109/VTS.2013.6548926  0.307
2013 Arslan B, Orailoglu A. Tracing the best test mix through multi-variate quality tracking Proceedings of the Ieee Vlsi Test Symposium. DOI: 10.1109/VTS.2013.6548886  0.654
2013 Arslan B, Orailoglu A. Full exploitation of process variation space for continuous delivery of optimal delay test quality Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 552-557. DOI: 10.1109/ASPDAC.2013.6509654  0.631
2012 Bournoutian G, Orailoglu A. Dynamic transient fault detection and recovery for embedded processor datapaths Codes+Isss'12 - Proceedings of the 10th Acm International Conference On Hardware/Software-Codesign and System Synthesis, Co-Located With Esweek. 43-52. DOI: 10.1145/2380445.2380459  0.807
2012 Arslan B, Orailoglu A. Delay test resource allocation and scheduling for multiple frequency domains Proceedings of the Ieee Vlsi Test Symposium. 114-119. DOI: 10.1109/VTS.2012.6231089  0.594
2012 Chen M, Orailoglu A. Scan power reduction for linear test compression schemes through seed selection Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 2170-2183. DOI: 10.1109/Tvlsi.2011.2173509  0.634
2012 Chen M, Orailoglu A. On diagnosis of timing failures in scan architecture Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1102-1115. DOI: 10.1109/Tcad.2012.2186298  0.609
2012 Yang C, Orailoglu A. Tackling resource variations through adaptive multicore execution frameworks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 132-145. DOI: 10.1109/Tcad.2011.2166829  0.491
2011 Bournoutian G, Orailoglu A. Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors Embedded Systems Week 2011, Esweek 2011 - Proceedings of the 9th Ieee/Acm/Ifip International Conference On Hardware/Software Codesign and System Synthesis, Codes+Isss'11. 89-97. DOI: 10.1145/2039370.2039387  0.81
2011 Yang C, Orailoglu A. Full fault resilience and relaxed synchronization requirements at the cache-memory interface Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1996-2009. DOI: 10.1109/Tvlsi.2010.2067230  0.46
2011 Rao W, Yang C, Karri R, Orailoglu A. Toward Future Systems with Nanoscale Devices: Overcoming the Reliability Challenge Computer. 44: 46-53. DOI: 10.1109/Mc.2011.1  0.688
2011 Arslan B, Orailoglu A. Adaptive test framework for achieving target test quality at minimal cost Proceedings of the Asian Test Symposium. 323-328. DOI: 10.1109/ATS.2011.91  0.624
2011 Zhang Y, Xue CJ, Yang C, Orailoglu A. Migration-aware adaptive MPSoC static schedules with dynamic reconfigurability Journal of Parallel and Distributed Computing. 71: 1400-1410. DOI: 10.1016/J.Jpdc.2011.06.006  0.465
2011 Arslan B, Orailoglu A. Adaptive test optimization through real time learning of test effectiveness Proceedings -Design, Automation and Test in Europe, Date. 1430-1435.  0.64
2011 Chen M, Orailoglu A. Diagnosing scan chain timing faults through statistical feature analysis of scan images Proceedings -Design, Automation and Test in Europe, Date. 185-190.  0.302
2011 Chen M, Orailoglu A. Diagnosing scan clock delay faults through statistical timing pruning Proceedings - Design Automation Conference. 423-428.  0.341
2010 Bournoutian G, Orailoglu A. Dynamic, non-linear cache architecture for power-sensitive mobile processors 2010 Ieee/Acm/Ifip International Conference On Hardware/Software Codesign and System Synthesis, Codes+Isss 2010. 187-194. DOI: 10.1145/1878961.1878997  0.804
2010 Chen M, Orailoglu A. VDDmin test optimization for overscreening minimization through adaptive scan chain masking Proceedings of the Ieee Vlsi Test Symposium. 313-318. DOI: 10.1109/VTS.2010.5469544  0.359
2010 Chun S, Orailoglu A. DiSC: A new diagnosis method for multiple scan chain failures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 2051-2055. DOI: 10.1109/Tcad.2010.2061110  0.381
2010 Arslan B, Orailoglu A. Delay test quality maximization through process-aware selection of test set size Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 390-395. DOI: 10.1109/ICCD.2010.5647687  0.623
2010 Bournoutian G, Orailoglu A. Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions Design Automation For Embedded Systems. 14: 309-326. DOI: 10.1007/S10617-010-9058-Y  0.798
2010 Yang C, Chen M, Orailoglu A. Squashing code size in microcoded IPs while delivering high decompression speed Design Automation For Embedded Systems. 14: 265-284. DOI: 10.1007/S10617-010-9057-Z  0.565
2010 Chen M, Orailoglu A. Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme Proceedings -Design, Automation and Test in Europe, Date. 63-68.  0.307
2009 Orailoglu A, Pozzi L. Guest editorial special section on the IEEE symposium on application specific processors 2008 Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1786-1787. DOI: 10.1109/Tcad.2009.2035481  0.303
2009 Xiang D, Hu D, Xu Q, Orailoglu A. Low-power scan testing for test data compression using a routing-driven scan architecture Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1101-1105. DOI: 10.1109/Tcad.2009.2018775  0.501
2009 Rao W, Orailoglu A, Karri R. Logic Mapping in Crossbar-Based Nanoarchitectures Ieee Design & Test of Computers. 26: 68-77. DOI: 10.1109/Mdt.2009.14  0.648
2009 Chen M, Orailoglu A. Flip-flop hardening and selection for soft error and delay fault resilience Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 49-57. DOI: 10.1109/DFT.2009.50  0.337
2009 Sinanoglu O, Al-Mulla M, Shunaiber NA, Orailoglu A. Scan Cell Positioning for Boosting the Compression of Fan-Out Networks Journal of Computer Science and Technology. 24: 939-948. DOI: 10.1007/S11390-009-9268-6  0.687
2009 Chen M, Orailoglu A. Scan power reduction in linear test data compression scheme Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 78-82.  0.377
2009 Sinanoglu O, Orailoglu A. Application of serial transformations in scan-based SOC test for test cost reduction Kuwait Journal of Science and Engineering. 36: 167-195.  0.668
2008 Yang C, Orailoglu A. A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization Embedded Systems Week 2008 - Proceedings of the 2008 International Conference On Compilers, Architecture and Synthesis For Embedded Systems, Cases'08. 11-20. DOI: 10.1145/1450095.1450100  0.32
2008 Orailoglu A, Maxwell P, Metra C. Proceedings of the IEEE VLSI Test Symposium: Foreword Proceedings of the Ieee Vlsi Test Symposium. DOI: 10.1109/VTS.2008.4  0.365
2008 Rao W, Orailoglu A, Marzullo K. Locality aware redundancy allocation in nanoelectronic systems 2008 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2008. 24-31. DOI: 10.1109/NANOARCH.2008.4585788  0.311
2008 Kim K, Karri R, Orailoglu A. Design automation for hybrid CMOS-nanoelectronics crossbars 2007 Ieee International Symposium On Nanoscale Architectures, Nanoarch. 27-32. DOI: 10.1109/NANOARCH.2007.4400854  0.573
2008 Chen M, Orailoglu A. Test cost minimization through adaptive test development 26th Ieee International Conference On Computer Design 2008, Iccd. 234-239. DOI: 10.1109/ICCD.2008.4751867  0.401
2008 Rao W, Orailoglu A. Towards fault tolerant parallel prefix adders in nanoelectronic systems Proceedings -Design, Automation and Test in Europe, Date. 360-365. DOI: 10.1109/DATE.2008.4484706  0.56
2008 Bournoutian G, Orailoglu A. Miss reduction in embedded processors through dynamic, power-friendly cache design Proceedings - Design Automation Conference. 304-309. DOI: 10.1109/DAC.2008.4555828  0.807
2007 Bahar RI, Hammerstrom D, Harlow J, Joyner WH, Lau C, Marculescu D, Orailoglu A, Pedram M. Architectures for silicon nanoelectronics and beyond Computer. 40: 25-33. DOI: 10.1109/Mc.2007.7  0.328
2007 Rao W, Orailoglu A, Karri R. Fault tolerant approaches to nanoelectronic programmable logic arrays Proceedings of the International Conference On Dependable Systems and Networks. 216-223. DOI: 10.1109/DSN.2007.49  0.605
2007 Wenjing R, Orailoglu A, Karri R. Logic level fault tolerance approaches targeting nanoelectronics PLAs Proceedings -Design, Automation and Test in Europe, Date. 865-869. DOI: 10.1109/DATE.2007.364401  0.612
2007 Hussin FA, Yoneda T, Orailoglu A, Fujiwara H. Core-based testing of multiprocessor system-on-chips utilizing hierarchical functional buses Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 720-725. DOI: 10.1109/ASPDAC.2007.358072  0.393
2007 Makris Y, Orailoglu A. On the identification of modular test requirements for low cost hierarchical test path construction Integration, the Vlsi Journal. 40: 315-325. DOI: 10.1016/J.Vlsi.2006.01.002  0.682
2007 Rao W, Orailoglu A, Karri R. Towards nanoelectronics processor architectures Journal of Electronic Testing: Theory and Applications (Jetta). 23: 235-254. DOI: 10.1007/S10836-006-0555-7  0.743
2007 Petrov P, Orailoglu A. Dynamic tag reduction for low-power caches in embedded systems with virtual memory International Journal of Parallel Programming. 35: 157-177. DOI: 10.1007/S10766-006-0030-1  0.382
2006 Chengmo Y, Orailoglu A. Power-efficient instruction delivery through trace reuse Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 2006: 192-201. DOI: 10.1145/1152154.1152185  0.323
2006 Rao W, Orailoglu A, Karri R. Topology aware mapping of logic functions onto nanowire-based crossbar architectures Proceedings - Design Automation Conference. 723-726. DOI: 10.1145/1146909.1147093  0.546
2006 Rao W, Orailoglu A, Karri R. Nanofabric topologies and reconfiguration algorithms to support dynamically adaptive fault tolerance Proceedings of the Ieee Vlsi Test Symposium. 2006: 214-219. DOI: 10.1109/VTS.2006.50  0.601
2006 Rao W, Orailoglu A, Karri R. Fault identification in reconfigurable carry lookahead adders targeting nanoelectronic fabrics Proceedings - Eleventh Ieee European Test Symposium, Ets 2006. 2006: 63-68. DOI: 10.1109/ETS.2006.23  0.614
2005 Petrov P, Orailoglu A. A reprogrammable customization framework for efficient branch resolution in embedded processors Acm Transactions in Embedded Computing Systems. 4: 452-468. DOI: 10.1145/1067915.1067924  0.381
2005 Sinanoglu O, Orailoglu A. Test power reductions through computationally efficient, decoupled scan chain modifications Ieee Transactions On Reliability. 54: 215-223. DOI: 10.1109/Tr.2005.847276  0.715
2005 Bayraktaroglu I, Orailoglu A. The construction of optimal deterministic partitionings in scan-based BIST fault diagnosis: Mathematical foundations and cost-effective implementations Ieee Transactions On Computers. 54: 61-75. DOI: 10.1109/Tc.2005.14  0.765
2005 Rao W, Orailoglu A, Karri R. Architectural-level fault tolerant computation in nanoelectronic processors Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 533-539. DOI: 10.1109/ICCD.2005.27  0.639
2005 Topaloglu RO, Orailoglu A. A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs Proceedings - Design Automation Conference. 851-856.  0.42
2005 Rao W, Orailoglu A, Karri R. Fault tolerant nanoelectronic processor architectures Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 1: 311-316.  0.31
2004 Petrov P, Orailoglu A. Low-power instruction bus encoding for embedded processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 812-826. DOI: 10.1109/Tvlsi.2004.831468  0.382
2004 Ozev S, Orailoglu A. Design of concurrent test hardware for linear analog circuits with constrained hardware overhead Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 756-765. DOI: 10.1109/Tvlsi.2004.827597  0.632
2004 Makris Y, Bayraktaroglu I, Orailoglu A. Enhancing reliability of RTL controller-datapath circuits via invariant-based concurrent test Ieee Transactions On Reliability. 53: 269-278. DOI: 10.1109/Tr.2004.829175  0.833
2004 Petrov P, Orailoglu A. Tag compression for low power in dynamically customizable embedded processors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1031-1047. DOI: 10.1109/Tcad.2004.829823  0.425
2004 Petrov P, Orailoglu A. Transforming binary code for low-power embedded processors Ieee Micro. 24: 21-33. DOI: 10.1109/Mm.2004.18  0.381
2004 Ozev S, Bayraktaroglu I, Orailoglu A. Seamless Test of Digital Components in Mixed-Signal Paths Ieee Design and Test of Computers. 21: 44-55. DOI: 10.1109/Mdt.2004.1261849  0.824
2004 Ozev S, Orailoglu A. End-to-end testability analysis and DfT insertion for mixed-signal paths Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 72-77. DOI: 10.1109/ICCD.2004.1347902  0.581
2004 Sinanoglu O, Orailoglu A. Pipelined test of SOC cores through test data transformations Proceedings - Ninth Ieee European Test Symposium, Ets 2004. 86-91. DOI: 10.1109/ETSYM.2004.1347612  0.661
2004 Arslan B, Orailoglu A. Circularscan: A scan architecture for test cost reduction Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 2: 1290-1295. DOI: 10.1109/DATE.2004.1269073  0.657
2004 Sinanoglu O, Orailoglu A. Scan power minimization through stimulus and response transformations Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 404-409. DOI: 10.1109/DATE.2004.1268880  0.67
2004 Cota É, Carro L, Lubaszewski M, Orailoğlu A. Searching for Global Test Costs Optimization in Core-Based Systems Journal of Electronic Testing. 20: 357-373. DOI: 10.1023/B:Jett.0000039604.64927.0F  0.477
2004 Sinanoglu O, Orailoglu A. Fast and energy-frugal deterministic test through efficient compression and compaction techniques Journal of Systems Architecture. 50: 257-266. DOI: 10.1016/J.Sysarc.2003.08.005  0.706
2004 Sinanoglu O, Orailoglu A. Efficient RT-level fault diagnosis methodology Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 212-217. DOI: 10.1007/S11390-005-0166-2  0.638
2004 Sinanoglu O, Orailoglu A. Autonomous yet deterministic test of SOC cores Proceedings - International Test Conference. 1359-1368.  0.67
2004 Arslan B, Orailoglu A. Test cost reduction through a reconfigurable scan architecture Proceedings - International Test Conference. 945-952.  0.65
2004 Arslan B, Orailoglu A. Design space exploration for aggressive test cost reduction in Circular Scan architectures Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 726-731.  0.675
2004 Rao W, Orailoglu A, Su G. Frugal linear network-based test decompression for drastic test cost reductions Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 721-725.  0.374
2004 Arslan B, Sinanoglu O, Orailoglu A. Extending the applicability of parallel-serial scan designs Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 200-203.  0.659
2004 Ayoub R, Petrov P, Orailoglu A. Application specific instruction memory transformations for power efficient, fault resilient embedded processors Proceedings - Ieee International Soc Conference. 195-198.  0.342
2003 Bayraktaroglu I, Orailoglu A. Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression Proceedings of the Ieee Vlsi Test Symposium. 2003: 113-118. DOI: 10.1109/VTEST.2003.1197641  0.801
2003 Bayraktaroglu I, Orailoglu A. Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs Ieee Transactions On Computers. 52: 1480-1489. DOI: 10.1109/Tc.2003.1244945  0.808
2003 Sinanoglu O, Orailoglu A. Compacting test responses for deeply embedded SoC cores Ieee Design and Test of Computers. 20: 22-30. DOI: 10.1109/Mdt.2003.1214349  0.672
2003 Petrov P, Orailoglu A. Application-specific instruction memory customizations for power-efficient embedded processors Ieee Design and Test of Computers. 20: 18-25+7. DOI: 10.1109/Mdt.2003.1173049  0.366
2003 Sinanoglu O, Orailoglu A. Parity-based output compaction for core-based SOCs [logic testing] Proceedings of the European Test Workshop. 2003: 15-20. DOI: 10.1109/ETW.2003.1231663  0.687
2003 Rao W, Orailoglu A. Virtual compression through test vector stitching for scan based designs Proceedings -Design, Automation and Test in Europe, Date. 104-109. DOI: 10.1109/DATE.2003.1253594  0.642
2003 Arslan B, Orailoglu A. Extracting precise diagnosis of bridging faults from stuck-at fault information Proceedings of the Asian Test Symposium. 2003: 230-235. DOI: 10.1109/ATS.2003.1250815  0.584
2003 Sinanoglu O, Orailoglu A. Test data manipulation techniques for energy-frugal, rapid scan test Proceedings of the Asian Test Symposium. 2003: 202-207. DOI: 10.1109/ATS.2003.1250810  0.663
2003 Sinanoglu O, Bayraktaroglu I, Orailoglu A. Reducing average and peak test power through scan chain modification Journal of Electronic Testing: Theory and Applications (Jetta). 19: 457-467. DOI: 10.1023/A:1024600311740  0.836
2003 Ozev S, Orailoglu A. Automated system-level test development for mixed-signal circuits Analog Integrated Circuits and Signal Processing. 35: 169-178. DOI: 10.1023/A:1024130616851  0.709
2003 Ozev S, Orailoglu A. Statistical tolerance analysis for assured analog test coverage Journal of Electronic Testing: Theory and Applications (Jetta). 19: 173-182. DOI: 10.1023/A:1022893724851  0.688
2003 Sinanoglu O, Orailoglu A. Partial Core Encryption for Performance-Efficient Test of SOCs Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 91-94.  0.665
2003 Sinanoglu O, Orailoglu A. Modeling Scan Chain Modifications for Scan-in Test Power Minimization Ieee International Test Conference (Tc). 602-611.  0.638
2003 Petrov P, Orailoglu A. Customizable embedded processor architectures Proceedings - Euromicro Symposium On Digital System Design, Dsd 2003. 468-475.  0.326
2003 Sinanoglu O, Orailoglu A. Hierarchical constraint conscious RT-level test generation Proceedings - Euromicro Symposium On Digital System Design, Dsd 2003. 312-318.  0.649
2003 Sinanoglu O, Orailoglu A. Aggressive test power reduction through test stimuli transformation Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 542-547.  0.648
2003 Rao W, Bayraktaroglu I, Orailoglu A. Test application time and volume compression through seed overlapping Proceedings - Design Automation Conference. 732-737.  0.785
2002 Sinanoglu O, Orailoglu A. A novel scan architecture for power-efficient, rapid test Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 299-303. DOI: 10.1145/774572.774617  0.669
2002 Goodby L, Orailoǧlu A, Chau PM. Microarchitectural synthesis of performance-constrained, low-power VLSI designs Acm Transactions On Design Automation of Electronic Systems. 7: 122-136. DOI: 10.1145/504914.504919  0.398
2002 Ozev S, Orailoglu A. Boosting the accuracy of analog test coverage computation through statistical tolerance analysis Proceedings of the Ieee Vlsi Test Symposium. 2002: 213-219. DOI: 10.1109/VTS.2002.1011141  0.66
2002 Sinanoglu O, Bayraktaroglu I, Orailoglu A. Test power reduction through minimization of scan chain transitions Proceedings of the Ieee Vlsi Test Symposium. 2002: 166-171. DOI: 10.1109/VTS.2002.1011129  0.83
2002 Sinanoglu O, Orailoglu A. Efficlent construction of aliasing-free compaction circuitry Ieee Micro. 22: 82-92. DOI: 10.1109/Mm.2002.1044302  0.679
2002 Ozev S, Olgaard CV, Orailoglu A. Multilevel testability analysis and solutions for integrated bluetooth transceivers Ieee Design and Test of Computers. 19: 82-91. DOI: 10.1109/Mdt.2002.1033796  0.602
2002 Ozev S, Orailoglu A. An integrated tool for analog test generation and fault simulation Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 267-272. DOI: 10.1109/ISQED.2002.996748  0.676
2002 Sinanoglu O, Bayraktaroglu I, Orailoglu A. Dynamic test data transformations for average and peak power reductions Proceedings of the European Test Workshop. 2002: 113-118. DOI: 10.1109/ETW.2002.1029647  0.833
2002 Sinanoglu O, Orailoglu A. Fast and energy-frugal deterministic test through test vector correlation exploitation Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 2002: 325-333. DOI: 10.1109/DFTVS.2002.1173529  0.677
2002 Petrov P, Orailoglu A. Power efficient embedded processor IPs through application-specific tag compression in data caches Proceedings -Design, Automation and Test in Europe, Date. 1065-1071. DOI: 10.1109/DATE.2002.998434  0.341
2002 Reda S, Orailoglu A. Reducing test application time through test data mutation encoding Proceedings -Design, Automation and Test in Europe, Date. 387-393. DOI: 10.1109/DATE.2002.998303  0.37
2002 Bayraktaroglu I, Orailoglu A. Gate level fault diagnosis in scan-based BIST Proceedings -Design, Automation and Test in Europe, Date. 376-381. DOI: 10.1109/DATE.2002.998301  0.76
2002 Makris Y, Orailoglu A. Test requirement analysis for low cost hierarchical test path construction Proceedings of the Asian Test Symposium. 2002: 134-139. DOI: 10.1109/ATS.2002.1181700  0.641
2002 Bayraktaroglu I, Orailoglu A. Cost-effective deterministic partitioning for rapid diagnosis in scan-based BIST Ieee Design and Test of Computers. 19: 42-53. DOI: 10.1109/54.980052  0.766
2002 Makris Y, Collins J, Orailoǧlu A. Fast hierarchical test path construction for circuits with DFT-free controller-datapath interface Journal of Electronic Testing: Theory and Applications (Jetta). 18: 29-42. DOI: 10.1023/A:1013723905896  0.7
2002 Arslan B, Orailoglu A. Fault dictionary size reduction through test response superposition Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 480-485.  0.615
2002 Ozev S, Orailoglu A. Cost-effective concurrent test hardware design for linear analog circuits Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 258-264.  0.599
2002 Ozev S, Orailoglu A, Haggag H. Automated test development and test time reduction for RF subsystems Proceedings - Ieee International Symposium On Circuits and Systems. 1.  0.65
2002 Sinanoglu O, Bayraktaroglu I, Orailoglu A. Scan power reduction through test data transition frequency analysis Ieee International Test Conference (Tc). 844-850.  0.788
2001 Bayraktaroglu I, Orailoglu A. Diagnosis for scan-based BIST: Reaching deep into the signatures Proceedings -Design, Automation and Test in Europe, Date. 102-109. DOI: 10.1109/DATE.2001.915008  0.744
2001 Ozev S, Orailoglu A. System-level test synthesis for mixed-signal designs Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 48: 588-599. DOI: 10.1109/82.943329  0.651
2001 Bayraktaroglu I, Orailoglu A. Concurrent test for digital linear systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1132-1142. DOI: 10.1109/43.945308  0.768
2001 Bayraktaroglu I, Orailoglu A. Test volume and application time reduction through scan chain concealment Proceedings - Design Automation Conference. 151-155.  0.77
2001 Sinanoglu O, Orailoglu A. Space and time compaction schemes for embedded cores Ieee International Test Conference (Tc). 521-529.  0.643
2001 Sinanoglu O, Orailoglu A. RT-level fault simulation based on symbolic propagation Proceedings of the Ieee Vlsi Test Symposium. 240-245.  0.591
2001 Sinanoglu O, Orailoglu A. Compaction schemes with minimum test application time Proceedings of the Asian Test Symposium. 199-204.  0.658
2001 Bayraktaroglu I, Orailoglu A. Selecting a PRPG: Randomness, primitiveness, or sheer luck? Proceedings of the Asian Test Symposium. 373-378.  0.755
2001 Petrov P, Orailoglu A. Towards effective embedded processors in codesigns: Customizable partitioned caches Hardware/Software Codesign - Proceedings of the International Workshop. 79-84.  0.349
2001 Almukhaizim S, Petrov P, Orailoglu A. Faults in processor control subsystems: Testing correctness and performance faults in the data prefetching unit Proceedings of the Asian Test Symposium. 319-324.  0.336
2001 Almukhaizim S, Petrov P, Orailoglu A. Low-cost, software-based self-test methodologies for performance faults in processor control subsystems Proceedings of the Custom Integrated Circuits Conference. 263-266.  0.401
2001 Ozev S, Olgaard C, Orailoglu A. Testability implications in low-cost integrated radio transceivers: A Bluetooth case study Ieee International Test Conference (Tc). 965-974.  0.575
2001 Makris Y, Patel V, Orailoglu A. Efficient transparency extraction and utilization in hierarchical test Proceedings of the Ieee Vlsi Test Symposium. 246-251.  0.588
2000 Ozev S, Orailoglu A. Path-based test composition for mixed-signal SOC's 2000 Southwest Symposium On Mixed-Signal Design, Ssmsd 2000. 153-158. DOI: 10.1109/SSMSD.2000.836464  0.661
2000 Hamilton SN, Orailoglu A. On-line test for fault-secure fault identification Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 446-452. DOI: 10.1109/92.863626  0.412
2000 Makris Y, Collins J, Orailoglu A, Vishakantaiah P. Transparency-based hierarchical test generation for modular RTL designs Proceedings - Ieee International Symposium On Circuits and Systems. 2.  0.403
1999 Makris Y, Orailoglu A. Channel-based behavioral test synthesis for improved module reachability Proceedings -Design, Automation and Test in Europe, Date. 283-288. DOI: 10.1109/DATE.1999.761135  0.617
1999 Goodby L, Orailoglu A. Redundancy and testability in digital filter datapaths Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 631-644. DOI: 10.1109/43.759079  0.316
1998 Orailoğlu A. On-Line Fault Resilience Through Gracefully Degradable ASICs Journal of Electronic Testing. 12: 145-151. DOI: 10.1023/A:1008298226600  0.423
1997 Harris IG, Orailoglu A. Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction Vlsi Design. 5: 167-182. DOI: 10.1155/1997/81902  0.634
1997 Orailoglu A. Microarchitectural synthesis for rapid BIST testing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 573-586. DOI: 10.1109/43.640616  0.509
1996 Karri R, Hogstedt K, Orailoglu A. Computer-aided design of fault-tolerant VLSI systems Ieee Design and Test of Computers. 13: 88-96. DOI: 10.1109/54.536099  0.581
1996 Karri R, Orailoglu A. Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors Ieee Transactions On Reliability. 45: 404-412. DOI: 10.1109/24.536993  0.639
1996 Orailoglu A, Karri R. Automatic synthesis of self-recovering VLSI systems Ieee Transactions On Computers. 45: 131-142. DOI: 10.1109/12.485368  0.617
1994 Orailoglu A, Karri R. Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2: 304-311. DOI: 10.1109/92.311639  0.601
1994 Orailoǧlu A, Karri R. Synthesis of fault-tolerant and real-time microarchitectures Journal of Systems and Software. 25: 73-84. DOI: 10.1016/0164-1212(94)90058-2  0.649
1990 Karri R, Orailoglu A. Standard seven segmented display for burmese numerals Ieee Transactions On Consumer Electronics. 36: 959-961. DOI: 10.1109/30.61581  0.54
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