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Mitchell A. Thornton - Publications

Affiliations: 
Computer Science and Engineering Southern Methodist University, Dallas, TX, United States 
Area:
Computer Science, Electronics and Electrical Engineering
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46 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Smith K, Soeken M, Schmitt B, Micheli GD, Thornton M. Using ZDDs in the mapping of quantum circuits Arxiv: Quantum Physics. 318: 106-118. DOI: 10.4204/Eptcs.318.7  0.394
2016 Niemann P, Wille R, Miller DM, Thornton MA, Drechsler R. QMDDs: Efficient Quantum Function Representation and Manipulation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 86-99. DOI: 10.1109/Tcad.2015.2459034  0.31
2016 Gupta SD, Thornton MA. A Fixed-Point Squaring Algorithm Using an Implicit Arbitrary Radix Number System Ieee Journal On Emerging and Selected Topics in Circuits and Systems. DOI: 10.1109/Jetcas.2016.2528739  0.479
2015 Thornton MA. Simulation and Implication Using a Transfer Function Model for Switching Logic Ieee Transactions On Computers. 64: 3580-3590. DOI: 10.1109/Tc.2015.2401034  0.355
2015 Smith KN, Thornton MA. A multiple-valued logic synthesis tool for optical computing elements 2015 Ieee Dallas Circuits and Systems Conference: Enabling Technologies For a Connected World, Dcas 2015. DOI: 10.1109/DCAS.2015.7356589  0.301
2014 Thornton MA. Modeling digital switching circuits with linear algebra Synthesis Lectures On Digital Circuits and Systems. 44: 1-145. DOI: 10.2200/S00579ED1V01Y201404DCS044  0.446
2012 Feinstein DY, Thornton MA. Using the asynchronous paradigm for reversible sequential circuit implementation Proceedings of the International Symposium On Multiple-Valued Logic. 305-310. DOI: 10.1109/ISMVL.2012.33  0.396
2012 Menon RP, Thornton MA. Global multiple-valued clock approach for high- performance multi-phase clock integrated circuits Proceedings of the International Symposium On Multiple-Valued Logic. 19-24. DOI: 10.1109/ISMVL.2012.30  0.337
2012 Feinstein DY, Thornton MA. Reversible logic synthesis based on decision diagram variable ordering Journal of Multiple-Valued Logic and Soft Computing. 19: 325-339.  0.342
2010 Li L, Thornton MA. Digital system verification: A combined formal methods and simulation framework Synthesis Lectures On Digital Circuits and Systems. 27: 1-93. DOI: 10.2200/S00257ED1V01Y201002DCS027  0.319
2010 Datla SRPR, Thornton MA. Quaternary voltage-mode logic cells and fixed-point multiplication circuits Proceedings of the International Symposium On Multiple-Valued Logic. 128-133. DOI: 10.1109/ISMVL.2010.32  0.385
2009 Fit-Florea A, Li L, Thornton MA, Matula DW. A discrete logarithm number system for integer arithmetic modulo 2 k: Algorithms and lookup structures Ieee Transactions On Computers. 58: 163-174. DOI: 10.1109/Tc.2008.204  0.539
2009 Chen W, Thornton MA, Gui P. A digital-to-frequency converter using redundant signed binary addition Midwest Symposium On Circuits and Systems. 495-498. DOI: 10.1109/MWSCAS.2009.5236046  0.34
2009 Datla SR, Thornton MA, Hendrix L, Henderson D. Quaternary addition circuits based on SUSLOC voltage-mode cells and modeling with system verilog© Proceedings of the International Symposium On Multiple-Valued Logic. 256-261. DOI: 10.1109/ISMVL.2009.66  0.648
2009 Feinstein DY, Thornton MA. On the guidance of reversible logic synthesis by dynamic variable reordering Proceedings of the International Symposium On Multiple-Valued Logic. 132-138. DOI: 10.1109/ISMVL.2009.31  0.347
2009 Datla SR, Thornton MA, Matula DW. A low power high performance radix-4 approximate squaring circuit Proceedings of the International Conference On Application-Specific Systems, Architectures and Processors. 91-97. DOI: 10.1109/ASAP.2009.35  0.656
2009 Chen W, Thornton MA, Gui P. Redundant signed binary addition based digital-to-frequency converter Electronics Letters. 45: 824-826. DOI: 10.1049/El.2009.0823  0.39
2008 Feinstein DY, Thornton MA, Miller DM. Partially redundant logic detection using symbolic equivalence checking in reversible and irreversible logic circuits Proceedings -Design, Automation and Test in Europe, Date. 1378-1381. DOI: 10.1109/DATE.2008.4484932  0.371
2008 Moore J, Thornton MA, Matula DW. A low power radix-4 dual recoded integer squaring implementation for use in design of application specific arithmetic circuits Conference Record - Asilomar Conference On Signals, Systems and Computers. 1819-1822. DOI: 10.1109/ACSSC.2008.5074741  0.416
2007 Feinstein DY, Thornton MA, Nair VSS. Prefix parallel adder virtual implementation in reversible logic 2007 Ieee Region 5 Technical Conference, Tps. 74-80. DOI: 10.1109/TPSD.2007.4380355  0.34
2007 Amoui M, Große D, Thornton MA, Drechsler R. Evaluation of toggle coverage for MVL circuits specified in the SystemVerilog HDL Proceedings of the International Symposium On Multiple-Valued Logic. DOI: 10.1109/ISMVL.2007.19  0.413
2006 Li L, Fit-Florea A, Thornton MA, Matula DW. Performance evaluation of a novel direct table lookup method and architecture with application to 16-bit integer functions Proceedings of the International Conference On Application-Specific Systems, Architectures and Processors. 99-104. DOI: 10.1109/ASAP.2006.52  0.335
2005 Reese RB, Traver C, Thornton MA, Hemmendinger D. Early evaluation for performance enhancement in phased logic Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 532-550. DOI: 10.1109/Tcad.2005.844084  0.511
2005 Fazel K, Thornton MA, Reese RB. Early evaluation for phased logic circuits using BDDS and MVL Ieee Pacific Rim Conference On Communications, Computers, and Signal Processing - Proceedings. 2005: 400-403. DOI: 10.1109/PACRIM.2005.1517310  0.305
2005 Fit-Florea A, Matula DW, Thornton MA. Additive bit-serial algorithm for discrete logarithm modulo 2k Electronics Letters. 41: 57-59. DOI: 10.1049/El:20056993  0.323
2004 Reese RB, Thornton MA, Traver C. Two-phase micropipeline control wrapper with early evaluation Electronics Letters. 40: 365-366. DOI: 10.1049/El:20040256  0.31
2004 Thornton MA. Mixed-radix MVL function spectral and decision diagram representation Automation and Remote Control. 65: 1007-1017. DOI: 10.1023/B:Aurc.0000030910.23047.2D  0.461
2004 Kocan F, Gunes M, Thornton MA. Static variable ordering in ZBDDs for path delay fault coverage calculation Midwest Symposium On Circuits and Systems. 1.  0.349
2003 Thornton M. Performance Evaluation of a Parallel Decoupled Data Driven Multiprocessor Parallel Processing Letters. 13: 497-507. DOI: 10.1142/S0129626403001458  0.357
2003 Reese RB, Thornton MA, Traver C. A coarse-grain phased logic CPU Proceedings - International Symposium On Asynchronous Circuits and Systems. 2-13. DOI: 10.1109/Tc.2005.105  0.418
2003 Reese RB, Thornton MA, Traver C. A fine-grain Phased Logic CPU Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 2003: 70-79. DOI: 10.1109/ISVLSI.2003.1183355  0.314
2003 Thornton M. A signed binary addition circuit based on an alternative class of addition tables Computers and Electrical Engineering. 29: 303-315. DOI: 10.1016/S0045-7906(01)00027-1  0.523
2002 Bruce JW, Thornton MA, Shivakumaraiah L, Kokate PS, Li X. Efficient adder circuits based on a conservative reversible logic gate Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 2002: 83-88. DOI: 10.1109/ISVLSI.2002.1016879  0.446
2002 Thornton MA, Drechsler R, Miller DM. Multi-output timed Shannon circuits Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 2002: 47-52. DOI: 10.1109/ISVLSI.2002.1016873  0.421
2002 Thornton MA, Fazel K, Reese RB, Traver C. Generalized early evaluation in self-timed circuits Proceedings -Design, Automation and Test in Europe, Date. 255-259. DOI: 10.1109/DATE.2002.998281  0.365
2002 Thornton MA, Drechsler R, Günther W. Logic circuit equivalence checking using Haar spectral coefficients and partial BDDs Vlsi Design. 14: 53-64. DOI: 10.1080/10655140290009800  0.422
2001 Reese RB, Thornton MA, Traver C. Arithmetic logic circuits using self-timed bit level dataflow and early evaluation Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 18-23.  0.348
1999 Thornton MA, Nair VSS. Behavioral synthesis of combinational logic using spectral-based heuristics Acm Transactions On Design Automation of Electronic Systems. 4: 219-230. DOI: 10.1145/307988.308000  0.399
1999 Thornton MA, Gaiche JD, Lemieux JV. Tradeoff analysis of integer multiplier circuits implemented in FPGAs Ieee Pacific Rim Conference On Communications, Computers, and Signal Processing - Proceedings. 301-304.  0.415
1997 Thornton MA. Signed binary addition circuitry with inherent even parity outputs Ieee Transactions On Computers. 46: 811-816. DOI: 10.1109/12.599901  0.46
1997 Thornton MA. Modified Haar transform calculation using digital circuit output probabilities Proceedings of the International Conference On Information, Communications and Signal Processing, Icics. 1: 52-58.  0.393
1997 Thornton MA, Moore RP, Cordova JC. Applications of circuit probability computation using decision diagrams Ieee Pacific Rim Conference On Communications, Computers, and Signal Processing - Proceedings. 2: 683-687.  0.37
1996 Thornton MA, Nair VSS. BDD-based spectral approach for Reed-Muller circuit realisation Iee Proceedings: Computers and Digital Techniques. 143: 145-150.  0.335
1995 Thornton MA, Nair VSS. Efficient Calculation of Spectral Coefficients and Their Applications Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 1328-1341. DOI: 10.1109/43.469660  0.416
1994 Thornton MA, Nair VSS. Behavioral to structural translation in ESOP form Proceedings of the 1994 International Verilog Hdl Conference. 58-62. DOI: 10.1109/Ivc.1994.323747  0.471
1994 Thornton MA, Nair VSS. Efficient Spectral Coefficient Calculation Using Circuit Output Probabilities Digital Signal Processing. 4: 245-254. DOI: 10.1006/Dspr.1994.1024  0.382
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