Year |
Citation |
Score |
2009 |
Amelifard B, Pedram M. Optimal design of the power-delivery network for multiple voltage-island system-on-chips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 888-900. DOI: 10.1109/Tcad.2009.2017437 |
0.665 |
|
2009 |
Amelifard B, Fallah F, Pedram M. Low-power fanout optimization using multi threshold voltages and multi channel lengths Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 478-489. DOI: 10.1109/Tcad.2009.2013992 |
0.652 |
|
2008 |
Ghasemazar M, Amelifard B, Pedram M. A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops Proceedings of the International Symposium On Low Power Electronics and Design. 33-38. DOI: 10.1145/1393921.1393935 |
0.609 |
|
2008 |
Abrishami H, Hatami S, Amelifard B, Pedram M. NBTI-aware flip-flop characterization and design Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 29-34. DOI: 10.1145/1366110.1366121 |
0.621 |
|
2008 |
Amelifard B, Fallah F, Pedram M. Leakage minimization of SRAM cells in a dual-14 and dual-TOX technology Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 851-860. DOI: 10.1109/Tvlsi.2008.2000459 |
0.654 |
|
2008 |
Amelifard B, Hatami S, Fatemi H, Pedram M. A current source model for CMOS logic cells considering multiple input switching and stack effect Proceedings -Design, Automation and Test in Europe, Date. 568-573. DOI: 10.1109/DATE.2008.4484737 |
0.607 |
|
2007 |
Amelifard B, Pedram M. Design of an efficient power delivery network in an soc to enable dynamic power management Proceedings of the International Symposium On Low Power Electronics and Design. 328-333. DOI: 10.1145/1283780.1283850 |
0.646 |
|
2007 |
Amelifard B, Pedram M. Optimal selection of voltage regulator modules in a power delivery network Proceedings - Design Automation Conference. 168-173. DOI: 10.1109/DAC.2007.375146 |
0.645 |
|
2006 |
Amelifard B, Fallah F, Pedarm M. Low-power fanout optimization using MTCMOS and multi-Vt techniques Proceedings of the International Symposium On Low Power Electronics and Design. 2006: 334-337. DOI: 10.1145/1165573.1165652 |
0.498 |
|
2006 |
Amelifard B, Fallah F, Pedram M. Low-leakage SRAM design with dual V/sub t/ transistors Proceedings - International Symposium On Quality Electronic Design, Isqed. 729-734. DOI: 10.1109/ISQED.2006.84 |
0.52 |
|
2006 |
Amelifard B, Fallah F, Pedram M. Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using dual-Vt and dual-Tox assignment Proceedings -Design, Automation and Test in Europe, Date. 1. |
0.544 |
|
2005 |
Amelifard B, Fallah F, Pedram M. Closing the gap between carry select adder and ripple carry adder: A new class of low-power high-performance adders Proceedings - International Symposium On Quality Electronic Design, Isqed. 148-152. DOI: 10.1109/ISQED.2005.131 |
0.377 |
|
2005 |
Amelifard B, Afzali-Kusha A, Khademzadeh A. Enhancing the efficiency of cluster voltage scaling technique for low-power application Proceedings - Ieee International Symposium On Circuits and Systems. 1666-1669. DOI: 10.1109/ISCAS.2005.1464925 |
0.558 |
|
2005 |
Amelifard B, Fallah F, Pedram M. Low-power fanout optimization using multiple threshold voltage inverters Proceedings of the International Symposium On Low Power Electronics and Design. 95-98. |
0.54 |
|
2003 |
Taherzadeh-S M, Amelifard B, Iman-Eini H, Farbiz F, Afzali-Kusha A, Nourani M. Power and delay estimation of CMOS inverters using fully analytical approach 2003 Southwest Symposium On Mixed-Signal Design, Ssmsd 2003. 116-120. DOI: 10.1109/SSMSD.2003.1190409 |
0.427 |
|
2003 |
Taherzadeh-S M, Iman-Eini H, Amelifard B, Farazian M, Afzali-Kusha A, Nourani M. A simple yet accurate analytical method for reducing CMOS gates to equivalent inverters 2003 Southwest Symposium On Mixed-Signal Design, Ssmsd 2003. 112-115. DOI: 10.1109/SSMSD.2003.1190408 |
0.507 |
|
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