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Eby G. Friedman - Publications

Affiliations: 
1989 Electrical Engineering University of California, Irvine, Irvine, CA 
 1979-1991 Hughes Aircraft Company 
 1991- Electrical and Computer Engineering University of Rochester, Rochester, NY 
Area:
Integrated circuits, VLSI, Design automation
Website:
http://www.hajim.rochester.edu/ece/people/faculty/friedman_eby/index.html
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268 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Ciprut A, Friedman EG. Distributed Pass Gates in Power Delivery Systems With Digital Low-Dropout Regulators Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 28: 414-420. DOI: 10.1109/Tvlsi.2019.2941967  0.488
2020 Bairamkulov R, Friedman EG. Effective Resistance of Finite Two-Dimensional Grids Based on Infinity Mirror Technique Ieee Transactions On Circuits and Systems I-Regular Papers. 67: 3224-3233. DOI: 10.1109/Tcsi.2020.2985652  0.354
2020 Xu K, Vaisband B, Sizikov G, Li X, Friedman EG. EMI Suppression With Distributed $LLC$ Resonant Converter for High-Voltage VR-on-Package Ieee Transactions On Components, Packaging and Manufacturing Technology. 10: 263-271. DOI: 10.1109/Tcpmt.2019.2960699  0.453
2020 Zhu Y, Tan CW, Chua SL, Lim YD, Vaisband B, Tay BK, Friedman EG, Tan CS. Assembly Process and Electrical Properties of Top-Transferred Graphene on Carbon Nanotubes for Carbon-Based 3-D Interconnects Ieee Transactions On Components, Packaging and Manufacturing Technology. 10: 516-524. DOI: 10.1109/Tcpmt.2019.2940511  0.767
2020 Bairamkulov R, Xu K, Popovich M, Ochoa JS, Srinivas V, Friedman EG. Power Delivery Exploration Methodology Based on Constrained Optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 1916-1924. DOI: 10.1109/Tcad.2019.2925397  0.461
2020 Jabbari T, Krylov G, Whiteley S, Kawa J, Friedman EG. Repeater Insertion in SFQ Interconnect Ieee Transactions On Applied Superconductivity. 30: 1-8. DOI: 10.1109/Tasc.2020.3000982  0.384
2020 Krylov G, Friedman EG. Asynchronous Dynamic Single-Flux Quantum Majority Gates Ieee Transactions On Applied Superconductivity. 30: 1-7. DOI: 10.1109/Tasc.2020.2978428  0.437
2020 Kumar H, Jabbari T, Krylov G, Basu K, Friedman EG, Karri R. Toward Increasing the Difficulty of Reverse Engineering of RSFQ Circuits Ieee Transactions On Applied Superconductivity. 30: 1-13. DOI: 10.1109/Tasc.2019.2901895  0.414
2019 Ciprut A, Friedman EG. Stability of On-Chip Power Delivery Systems With Multiple Low-Dropout Regulators Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 27: 1779-1789. DOI: 10.1109/Tvlsi.2019.2914395  0.443
2019 Bairamkulov R, Friedman EG. Effective Resistance of Two-Dimensional Truncated Infinite Mesh Structures Ieee Transactions On Circuits and Systems I: Regular Papers. 66: 4368-4376. DOI: 10.1109/Tcsi.2019.2933749  0.353
2019 Xu K, Vaisband B, Sizikov G, Li X, Friedman EG. Power Noise and Near-Field EMI of High-Current System-in-Package With VR Top and Bottom Placements Ieee Transactions On Components, Packaging and Manufacturing Technology. 9: 712-718. DOI: 10.1109/Tcpmt.2019.2903285  0.846
2019 Jabbari T, Krylov G, Whiteley S, Mlinar E, Kawa J, Friedman EG. Interconnect Routing for Large-Scale RSFQ Circuits Ieee Transactions On Applied Superconductivity. 29: 1-5. DOI: 10.1109/Tasc.2019.2903023  0.464
2018 Vaisband B, Maurice A, Tan CW, Tay BK, Friedman EG. Electrical and Thermal Models of CNT TSV and Graphite Interface Ieee Transactions On Electron Devices. 65: 1880-1886. DOI: 10.1109/Ted.2018.2812761  0.773
2018 Zhang Y, Wang X, Friedman EG. Memristor-Based Circuit Design for Multilayer Neural Networks Ieee Transactions On Circuits and Systems I: Regular Papers. 65: 677-686. DOI: 10.1109/Tcsi.2017.2729787  0.352
2018 Xu K, Patel R, Raghavan P, Friedman EG. Exploratory design of on-chip power delivery for 14, 10, and 7 nm and beyond FinFET ICs Integration. 61: 11-19. DOI: 10.1016/J.Vlsi.2017.10.007  0.574
2018 Vaisband B, Friedman EG. Heterogeneous 3-D ICs as a platform for hybrid energy harvesting in IoT systems Future Generation Computer Systems. 87: 152-158. DOI: 10.1016/J.Future.2018.04.092  0.811
2017 Shapiro AE, Friedman EG. Interconnect Delay Model for Wide Supply Voltage Range Repeater Insertion in Sub-22 nm FinFET Technologies Journal of Low Power Electronics. 13: 395-401. DOI: 10.1166/Jolpe.2017.1495  0.371
2017 Zhang Y, Li Y, Wang X, Friedman EG. Synaptic Characteristics of Ag/AgInSbTe/Ta-Based Memristor for Pattern Recognition Applications Ieee Transactions On Electron Devices. 64: 1806-1811. DOI: 10.1109/Ted.2017.2671433  0.315
2017 Zhang Y, Wang X, Li Y, Friedman EG. Memristive Model for Synaptic Circuits Ieee Transactions On Circuits and Systems Ii: Express Briefs. 64: 767-771. DOI: 10.1109/Tcsii.2016.2605069  0.401
2017 Vaisband B, Friedman EG. Hexagonal TSV Bundle Topology for 3-D ICs Ieee Transactions On Circuits and Systems Ii: Express Briefs. 64: 11-15. DOI: 10.1109/Tcsii.2016.2551552  0.797
2017 Krylov G, Friedman EG. Design for Testability of SFQ Circuits Ieee Transactions On Applied Superconductivity. 27: 1-7. DOI: 10.1109/Tasc.2017.2759239  0.378
2016 Ciprut A, Friedman EG. Modeling Size Limitations of Resistive Crossbar Array With Cell Selectors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2570120  0.316
2016 Vaisband B, Friedman EG. Noise Coupling Models in Heterogeneous 3-D ICs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2535370  0.804
2016 Shapiro A, Friedman EG. Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 24: 774-778. DOI: 10.1109/Tvlsi.2015.2409051  0.663
2016 Vaisband I, Friedman EG. Stability of distributed power delivery systems with multiple parallel on-chip LDO regulators Ieee Transactions On Power Electronics. 31: 5625-5634. DOI: 10.1109/Tpel.2015.2493512  0.461
2016 Kazemi M, Rowlands GE, Ipek E, Buhrman RA, Friedman EG. Compact Model for Spin-Orbit Magnetic Tunnel Junctions Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2015.2510543  0.309
2016 Shapiro AE, Atallah F, Kim K, Jeong J, Fischer J, Friedman EG. Adaptive power gating of 32-bit Kogge Stone adder Integration, the Vlsi Journal. 53: 80-87. DOI: 10.1016/J.Vlsi.2015.12.001  0.477
2016 Savidis I, Ciftcioglu B, Xu J, Hu J, Jain M, Berman R, Xue J, Liu P, Moore D, Wicks G, Huang M, Wu H, Friedman EG. Heterogeneous 3-D circuits: Integrating free-space optics with CMOS Microelectronics Journal. 50: 66-75. DOI: 10.1016/J.Mejo.2015.10.004  0.753
2016 Vaisband IP, Popovich M, Köse S, Jakushokas R, Mezhiba AV, Friedman EG. On-Chip power delivery and management, fourth edition On-Chip Power Delivery and Management, Fourth Edition. 1-742. DOI: 10.1007/978-3-319-29395-0  0.83
2015 Bai Y, Song Y, Bojnordi MN, Shapiro A, Friedman EG, Ipek E. Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2455874  0.686
2015 Wang J, Gong N, Friedman EG. PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low-Power Microprocessors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2419255  0.501
2015 Patel R, Guo X, Guo Q, Ipek E, Friedman EG. Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2401577  0.466
2015 Savidis I, Vaisband B, Friedman EG. Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 2077-2089. DOI: 10.1109/Tvlsi.2014.2357441  0.786
2015 Patel R, Kvatinsky S, Friedman EG, Kolodny A. Multistate register based on resistive RAM Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 1750-1759. DOI: 10.1109/Tvlsi.2014.2347926  0.797
2015 Kazemi M, Ipek E, Friedman EG. Energy-Efficient Nonvolatile Flip-Flop With Subnanosecond Data Backup Time for Fine-Grain Power Gating Ieee Transactions On Circuits and Systems Ii: Express Briefs. 62: 1154-1158. DOI: 10.1109/Tcsii.2015.2468931  0.407
2015 Kvatinsky S, Ramadan M, Friedman EG, Kolodny A. VTEAM: A General Model for Voltage-Controlled Memristors Ieee Transactions On Circuits and Systems Ii: Express Briefs. 62: 786-790. DOI: 10.1109/Tcsii.2015.2433536  0.778
2015 Guo Q, Guo X, Bai Y, Patel R, Ipek E, Friedman EG. Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing Ieee Micro. 35: 62-71. DOI: 10.1109/Mm.2015.89  0.521
2015 Xu K, Friedman EG. Scaling trends of power noise in 3-D ICs Integration, the Vlsi Journal. 51: 139-148. DOI: 10.1016/J.Vlsi.2015.07.007  0.439
2015 Vaisband I, Friedman EG. Energy efficient adaptive clustering of on-chip power delivery systems Integration, the Vlsi Journal. 48: 1-9. DOI: 10.1016/J.Vlsi.2014.06.003  0.421
2015 Vaisband I, Price B, Köse S, Kolla Y, Friedman EG, Fischer J. Distributed LDO regulators in a 28 nm power delivery system Analog Integrated Circuits and Signal Processing. 83: 295-309. DOI: 10.1007/S10470-015-0526-Y  0.693
2014 Shapiro A, Friedman EG. MOS current mode logic near threshold circuits Journal of Low Power Electronics and Applications. 4: 138-152. DOI: 10.3390/Jlpea4020138  0.675
2014 Vaisband I, Azhar M, Friedman EG, Kose S. Digitally Controlled Pulse Width Modulator for On-Chip Power Management Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 2527-2534. DOI: 10.1109/Tvlsi.2013.2294402  0.668
2014 Kvatinsky S, Satat G, Wald N, Friedman EG, Kolodny A, Weiser UC. Memristor-based material implication (IMPLY) logic: Design principles and methodologies Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 2054-2066. DOI: 10.1109/Tvlsi.2013.2282132  0.774
2014 Kvatinsky S, Belousov D, Liman S, Satat G, Wald N, Friedman EG, Kolodny A, Weiser UC. MAGIC - Memristor-aided logic Ieee Transactions On Circuits and Systems Ii: Express Briefs. 61: 895-899. DOI: 10.1109/Tcsii.2014.2357292  0.771
2014 Vaisband I, Friedman EG. Dynamic power management with power network-on-chip 2014 Ieee 12th International New Circuits and Systems Conference, Newcas 2014. 225-228. DOI: 10.1109/NEWCAS.2014.6934024  0.343
2014 Kvatinsky S, Nacson YH, Etsion Y, Friedman EG, Kolodny A, Weiser UC. Memristor-based multithreading Ieee Computer Architecture Letters. 13: 41-44. DOI: 10.1109/L-Ca.2013.3  0.776
2014 Vaisband B, Savidis I, Friedman EG. Thermal conduction path analysis in 3-D ICs Proceedings - Ieee International Symposium On Circuits and Systems. 594-597. DOI: 10.1109/ISCAS.2014.6865205  0.696
2014 Kvatinsky S, Nacson YH, Etsion Y, Kolodny A, Weiser UC, Patel R, Friedman EG. Memristive multistate pipeline register International Workshop On Cellular Nanoscale Networks and Their Applications. DOI: 10.1109/CNNA.2014.6888594  0.716
2014 Levy Y, Bruck J, Cassuto Y, Friedman EG, Kolodny A, Yaakobi E, Kvatinsky S. Logic operations in memory using a memristive Akers array Microelectronics Journal. 45: 1429-1437. DOI: 10.1016/J.Mejo.2014.06.006  0.75
2014 Patel R, Ipek E, Friedman EG. 2T-1R STT-MRAM memory cells for enhanced on/off current ratio Microelectronics Journal. 45: 133-143. DOI: 10.1016/J.Mejo.2013.11.015  0.506
2013 Jakushokas R, Friedman EG. Power network optimization based on link breaking methodology Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 983-987. DOI: 10.1109/Tvlsi.2012.2201186  0.841
2013 Kose S, Tam S, Pinzon S, McDermott B, Friedman EG. Active filter-based hybrid on-chip DC-DC converter for point-of-load voltage regulation Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 680-691. DOI: 10.1109/Tvlsi.2012.2190539  0.695
2013 Vaisband I, Friedman EG. Heterogeneous methodology for energy efficient distribution of on-chip power supplies Ieee Transactions On Power Electronics. 28: 4267-4280. DOI: 10.1109/Tpel.2012.2230408  0.442
2013 Kvatinsky S, Friedman EG, Kolodny A, Weiser UC. TEAM: Threshold adaptive memristor model Ieee Transactions On Circuits and Systems I: Regular Papers. 60: 211-221. DOI: 10.1109/Tcsi.2012.2215714  0.757
2013 Shapiro A, Friedman EG. Performance characteristics of 14 nm near threshold MCML circuits 2013 Ieee Soi-3d-Subthreshold Microelectronics Technology Unified Conference, S3s 2013. DOI: 10.1109/S3S.2013.6716545  0.368
2013 Kvatinsky S, Friedman EG, Kolodny A, Weiser UC. The desired memristor for circuit designers Ieee Circuits and Systems Magazine. 13: 17-22. DOI: 10.1109/Mcas.2013.2256257  0.781
2013 Savidis I, Kose S, Friedman EG. Power noise in TSV-based 3-D integrated circuits Ieee Journal of Solid-State Circuits. 48: 587-597. DOI: 10.1109/Jssc.2012.2217891  0.834
2013 Kose S, Friedman EG, Secareanu RM, Hartin O. Current profile of a microcontroller to determine electromagnetic emissions Proceedings - Ieee International Symposium On Circuits and Systems. 2650-2653. DOI: 10.1109/ISCAS.2013.6572423  0.747
2013 Kose S, Vaisband I, Friedman EG. Digitally controlled wide range pulse width modulator for on-chip power supplies Proceedings - Ieee International Symposium On Circuits and Systems. 2251-2254. DOI: 10.1109/ISCAS.2013.6572325  0.302
2013 Abdelhadi A, Ginosar R, Kolodny A, Friedman EG. Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks Integration, the Vlsi Journal. 46: 382-391. DOI: 10.1016/J.Vlsi.2012.12.001  0.654
2013 Ge S, Friedman EG. Data bus swizzling in TSV-based three-dimensional integrated circuits Microelectronics Journal. 44: 696-705. DOI: 10.1016/J.Mejo.2013.05.001  0.431
2012 Ciftcioglu B, Berman R, Wang S, Hu J, Savidis I, Jain M, Moore D, Huang M, Friedman EG, Wicks G, Wu H. 3-D integrated heterogeneous intra-chip free-space optical interconnect. Optics Express. 20: 4331-45. PMID 22418191 DOI: 10.1364/Oe.20.004331  0.724
2012 Jakushokas R, Friedman EG. Link breaking methodology: Mitigating noise within power networks Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 129-134. DOI: 10.1145/2206781.2206814  0.829
2012 Wu H, Ciftcioglu B, Berman R, Hu J, Wang S, Savidis I, Jain M, Moore D, Huang M, Friedman EG, Wicks G. Chip-scale demonstration of 3-D integrated intra-chip free-space optical interconnect Proceedings of Spie - the International Society For Optical Engineering. 8265. DOI: 10.1117/12.913314  0.728
2012 Köse S, Friedman EG. Distributed on-chip power delivery Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 2: 704-713. DOI: 10.1109/Jetcas.2012.2226378  0.724
2012 Vaisband I, Friedman EG, Ginosar R, Kolodny A. Energy metrics for power efficient crosslink and mesh topologies Iscas 2012 - 2012 Ieee International Symposium On Circuits and Systems. 1656-1659. DOI: 10.1109/ISCAS.2012.6271575  0.632
2012 Kose S, Friedman EG. Design methodology to distribute on-chip power in next generation integrated circuits 2012 Ieee 27th Convention of Electrical and Electronics Engineers in Israel, Ieeei 2012. DOI: 10.1109/EEEI.2012.6377093  0.433
2012 Kose S, Friedman EG. Distributed power delivery for energy efficient and low power systems Conference Record - Asilomar Conference On Signals, Systems and Computers. 757-761. DOI: 10.1109/ACSSC.2012.6489114  0.365
2012 Köse S, Friedman EG. Efficient algorithms for fast IR drop analysis exploiting locality Integration, the Vlsi Journal. 45: 149-161. DOI: 10.1016/J.Vlsi.2011.09.003  0.665
2012 Vishnyakov V, Friedman EG, Kolodny A. Multi-aggressor capacitive and inductive coupling noise modeling and mitigation Microelectronics Journal. 43: 235-243. DOI: 10.1016/J.Mejo.2011.12.007  0.58
2012 Salman E, Friedman EG. Utilizing interdependent timing constraints to enhance robustness in synchronous circuits Microelectronics Journal. 43: 119-127. DOI: 10.1016/J.Mejo.2011.11.005  0.682
2011 Vaisband I, Friedman EG, Ginosar R, Kolodny A. Low power clock network design Journal of Low Power Electronics and Applications. 1: 219-246. DOI: 10.3390/Jlpea1010219  0.674
2011 Pavlidis VF, Savidis I, Friedman EG. Clock distribution networks in 3-D integrated systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 2256-2266. DOI: 10.1109/Tvlsi.2010.2073724  0.827
2011 Rosenfeld J, Friedman EG. Linear and switch-mode conversion in 3-D circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 2095-2108. DOI: 10.1109/Tvlsi.2010.2070849  0.652
2011 Köse S, Salman E, Friedman EG. Shielding methodologies in the presence of power/ground noise Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1458-1468. DOI: 10.1109/Tvlsi.2010.2054119  0.74
2011 Rosenfeld J, Friedman EG. A distributed filter within a switching converter for application to 3-D integrated circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1075-1085. DOI: 10.1109/Tvlsi.2010.2045601  0.629
2011 Jakushokas R, Friedman EG. Multi-layer interdigitated power distribution networks Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 774-786. DOI: 10.1109/Tvlsi.2010.2043453  0.813
2011 Kose S, Friedman EG. Effective resistance of a two layer mesh Ieee Transactions On Circuits and Systems Ii: Express Briefs. 58: 739-743. DOI: 10.1109/Tcsii.2011.2168016  0.65
2011 Kose S, Friedman EG. Distributed power network co-design with on-chip power supplies and decoupling capacitors International Workshop On System Level Interconnect Prediction, Slip. DOI: 10.1109/SLIP.2011.6135434  0.386
2011 Ciftcioglu B, Berman R, Zhang J, Darling Z, Wang S, Hu J, Xue J, Garg A, Jain M, Savidis I, Moore D, Huang M, Friedman EG, Wicks G, Wu H. A 3-D integrated intrachip free-space optical interconnect for many-core chips Ieee Photonics Technology Letters. 23: 164-166. DOI: 10.1109/Lpt.2010.2093876  0.721
2011 Savidis I, Pavlidis V, Friedman EG. Clock distribution models of 3-D integrated systems Proceedings - Ieee International Symposium On Circuits and Systems. 2225-2228. DOI: 10.1109/ISCAS.2011.5938043  0.727
2011 Kvatinsky S, Kolodny A, Weiser UC, Friedman EG. Memristor-based IMPLY logic design procedure Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 142-147. DOI: 10.1109/ICCD.2011.6081389  0.728
2011 Wang J, Savidis I, Friedman EG. Thermal analysis of oxide-confined VCSEL arrays Microelectronics Journal. 42: 820-825. DOI: 10.1016/J.Mejo.2010.11.005  0.704
2011 Köse S, Friedman EG. Fast algorithms for IR voltage drop analysis exploiting locality Proceedings - Design Automation Conference. 996-1001.  0.634
2010 Xue J, Garg A, Ciftcioglu B, Hu J, Wang S, Savidis I, Jain M, Berman R, Liu P, Huang M, Wu H, Friedman E, Wicks G, Moore D. An intra-chip free-space optical interconnect Proceedings - International Symposium On Computer Architecture. 94-105. DOI: 10.1145/1815961.1815975  0.715
2010 Salman E, Friedman EG. Methodology to achieve higher tolerance to delay variations in synchronous circuits Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 447-452. DOI: 10.1145/1785481.1785585  0.642
2010 Köse S, Friedman EG. On-chip point-of-load voltage regulator for distributed power supplies Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 377-380. DOI: 10.1145/1785481.1785568  0.646
2010 Jakushokas R, Friedman EG. Line width optimization for interdigitated power/ground networks Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 329-334. DOI: 10.1145/1785481.1785557  0.801
2010 Abdelhadi A, Ginosar R, Kolodny A, Friedman EG. Timing-driven variation-aware nonuniform clock mesh synthesis Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 15-20. DOI: 10.1145/1785481.1785487  0.604
2010 Morgenshtein A, Friedman EG, Ginosar R, Kolodny A. Corrections to “Unified Logical Effort—A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect” [May 10 689-696] Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1262-1262. DOI: 10.1109/Tvlsi.2010.2052421  0.558
2010 Jakushokas R, Friedman EG. Resource based optimization for simultaneous shield and repeater insertion Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 742-749. DOI: 10.1109/Tvlsi.2009.2015950  0.804
2010 Morgenshtein A, Friedman EG, Ginosar R, Kolodny A. Unified logical effort - A method for delay evaluation and minimization in logic paths with RC interconnect Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 689-696. DOI: 10.1109/Tvlsi.2009.2014239  0.624
2010 Köse S, Friedman EG. Simultaneous co-design of distributed on-chip power supplies and decoupling capacitors Proceedings - Ieee International Soc Conference, Socc 2010. 15-18. DOI: 10.1109/SOCC.2010.5784662  0.682
2010 Jakushokas R, Friedman EG. Methodology for multi-layer interdigitated power and ground network design Iscas 2010 - 2010 Ieee International Symposium On Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 3208-3211. DOI: 10.1109/ISCAS.2010.5537931  0.806
2010 Köse S, Friedman EG. Fast algorithms for power grid analysis based on effective resistance Iscas 2010 - 2010 Ieee International Symposium On Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 3661-3664. DOI: 10.1109/ISCAS.2010.5537772  0.653
2010 Jakushokas R, Friedman EG. Globally integrated power and clock distribution network Iscas 2010 - 2010 Ieee International Symposium On Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 1751-1754. DOI: 10.1109/ISCAS.2010.5537570  0.81
2010 Jakushokas R, Salman E, Friedman EG, Secareanu RM, Hartin OL, Recker CL. Compact substrate models for efficient noise coupling and signal isolation analysis Iscas 2010 - 2010 Ieee International Symposium On Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2346-2349. DOI: 10.1109/ISCAS.2010.5537192  0.789
2010 Köse S, Friedman EG. An area efficient fully monolithic hybrid voltage regulator Iscas 2010 - 2010 Ieee International Symposium On Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2718-2721. DOI: 10.1109/ISCAS.2010.5537035  0.648
2010 Kvatinsky S, Friedman EG, Kolodny A, Schächter L. Power grid analysis based on a macro circuit model 2010 Ieee 26th Convention of Electrical and Electronics Engineers in Israel, Ieeei 2010. 708-712. DOI: 10.1109/EEEI.2010.5662121  0.801
2010 Pavlidis VF, Friedman EG. Physical design issues in 3-D integrated technologies Ifip Advances in Information and Communication Technology. 313: 1-21. DOI: 10.1007/978-3-642-12267-5_1  0.708
2009 Vaisband I, Ginosar R, Kolodny A, Friedman EG. Power efficient tree-based crosslinks for skew reduction Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 285-290. DOI: 10.1145/1531542.1531609  0.632
2009 Jakushokas R, Friedman EG. Simultaneous shield and repeater insertion Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 15-19. DOI: 10.1145/1531542.1531551  0.79
2009 Salman E, Jakushokas R, Friedman EG, Secareanu RM, Hartin OL. Contact merging algorithm for efficient substrate noise analysis in large scale circuits Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 9-14. DOI: 10.1145/1531542.1531550  0.819
2009 Chen G, Friedman EG. Transient response of a distributed rlc interconnect based on direct pole extraction Journal of Circuits, Systems and Computers. 18: 1263-1285. DOI: 10.1142/S0218126609005654  0.549
2009 Rosenfeld J, Friedman EG. Quasi-resonant interconnects: A low power, low latency design methodology Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 181-193. DOI: 10.1109/Tvlsi.2008.2011197  0.68
2009 Salman E, Friedman EG, Secareanu RM, Hartin OL. Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 1559-1564. DOI: 10.1109/Tvlsi.2008.2005195  0.786
2009 Salman E, Jakushokas R, Friedman EG, Secareanu RM, Hartin OL. Methodology for efficient substrate noise analysis in large-scale mixed-signal circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 1405-1418. DOI: 10.1109/Tvlsi.2008.2003518  0.828
2009 Savidis I, Friedman EG. Closed-form expressions of 3-D via resistance, inductance, and capacitance Ieee Transactions On Electron Devices. 56: 1873-1881. DOI: 10.1109/Ted.2009.2026200  0.706
2009 Jakushokas R, Friedman EG. Inductance model of interdigitated power and ground distribution networks Ieee Transactions On Circuits and Systems Ii: Express Briefs. 56: 585-589. DOI: 10.1109/Tcsii.2009.2023297  0.796
2009 Salman E, Friedman EG, Secareanu RM, Hartin OL. Worst case power/ground noise estimation using an equivalent transition time for resonance Ieee Transactions On Circuits and Systems I: Regular Papers. 56: 997-1004. DOI: 10.1109/Tcsi.2009.2016614  0.803
2009 Pavlidis VF, Friedman EG. Interconnect-based design methodologies for three-dimensional integrated circuits Proceedings of the Ieee. 97: 123-140. DOI: 10.1109/JPROC.2008.2007473  0.744
2009 Rosenfeld J, Friedman EG. On-Chip DC-DC converters for three-dimensional ICs Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 759-764. DOI: 10.1109/ISQED.2009.4810388  0.385
2009 Jakushokas R, Friedman EG. Minimizing noise via shield and repeater insertion Proceedings - Ieee International Symposium On Circuits and Systems. 2265-2268. DOI: 10.1109/ISCAS.2009.5118250  0.79
2009 Kourtev IS, Taskin B, Friedman EG. Timing optimization through clock skew scheduling Timing Optimization Through Clock Skew Scheduling. 1-265. DOI: 10.1007/978-0-387-71056-3  0.758
2008 Morgenshtein A, Friedman EG, Ginosar R, Kolodny A. Timing optimization in logic with interconnect International Workshop On System Level Interconnect Prediction, Slip. 1-9. DOI: 10.1145/1353610.1353615  0.568
2008 Popovich M, Friedman EG, Secareanu RM, Hartin OL. Efficient distributed on-chip decoupling capacitors for nanoscale ICs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 1717-1721. DOI: 10.1109/Tvlsi.2008.2001735  0.811
2008 Popovich M, Friedman EG, Sotman M, Kolodny A. On-chip power distribution grids with multiple supply voltages for high-performance integrated circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 908-921. DOI: 10.1109/Tvlsi.2008.2000515  0.762
2008 Popovich M, Sotman M, Kolodny A, Friedman EG. Effective radii of on-chip decoupling capacitors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 894-907. DOI: 10.1109/Tvlsi.2008.2000454  0.784
2008 Chen G, Friedman EG. Effective capacitance of inductive interconnects for short-circuit power analysis Ieee Transactions On Circuits and Systems Ii: Express Briefs. 55: 26-30. DOI: 10.1109/Tcsii.2007.907812  0.495
2008 Popovich M, Friedman EG. Nanoscale on-chip decoupling capacitors 2008 Ieee International Soc Conference, Socc. 51-54. DOI: 10.1109/SOCC.2008.4641478  0.637
2008 Köse S, Salman E, Ignjatovic Z, Friedman EG. Pseudo-random clocking to enhance signal integrity 2008 Ieee International Soc Conference, Socc. 47-50. DOI: 10.1109/SOCC.2008.4641477  0.634
2008 Salman E, Friedman EG. Methodology for placing localized guard rings to reduce substrate noise in mixed-signal circuits Prime - 2008 Phd Research in Microelectronics and Electronics, Proceedings. 85-88. DOI: 10.1109/RME.2008.4595731  0.626
2008 Salman E, Friedman EG, Secareanu RM, Hartin OL. Dominant substrate noise coupling mechanism for multiple switching gates Proceedings of the 9th International Symposium On Quality Electronic Design, Isqed 2008. 261-266. DOI: 10.1109/ISQED.2008.4479736  0.798
2008 Salman E, Friedman EG, Secareanu RM, Hartin OL. Equivalent rise time for resonance in power/ground noise estimation Proceedings - Ieee International Symposium On Circuits and Systems. 2422-2425. DOI: 10.1109/ISCAS.2008.4541944  0.803
2008 Savidis I, Friedman EG. Electrical modeling and characterization of 3-D vias Proceedings - Ieee International Symposium On Circuits and Systems. 784-787. DOI: 10.1109/ISCAS.2008.4541535  0.706
2008 Salman E, Jakushokas R, Friedman EG, Secareanu RM, Hartin OL. Input port reduction for efficient substrate extraction in large scale IC's Proceedings - Ieee International Symposium On Circuits and Systems. 376-379. DOI: 10.1109/ISCAS.2008.4541433  0.814
2008 Pavlidis VF, Savidis I, Friedman EG. Clock distribution networks for 3-D integrated circuits Proceedings of the Custom Integrated Circuits Conference. 651-654. DOI: 10.1109/CICC.2008.4672170  0.827
2008 Pavlidis VF, Friedman EG. Timing-driven via placement heuristics for three-dimensional ICs Integration, the Vlsi Journal. 41: 489-508. DOI: 10.1016/J.Vlsi.2007.11.002  0.736
2008 Popovich M, Mezhiba AV, Friedman EG. Power distribution networks with on-chip decoupling capacitors Power Distribution Networks With On-Chip Decoupling Capacitors. 1-515. DOI: 10.1007/978-0-387-71601-5  0.846
2007 Pavlidis VF, Friedman EG. 3-D topologies for Networks-on-Chip 2006 Ieee International Systems-On-Chip Conference, Soc. 285-288. DOI: 10.1109/Tvlsi.2007.893649  0.725
2007 Salman E, Dasdan A, Taraporevala F, Küçükçakar K, Friedman EG. Exploiting setup - Hold-time interdependence in static timing analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1114-1125. DOI: 10.1109/Tcad.2006.885834  0.635
2007 Salman E, Friedman EG, Secareanu RM. Substrate and ground noise interactions in mixed-signal circuits 2006 Ieee International Systems-On-Chip Conference, Soc. 293-296. DOI: 10.1109/SOCC.2006.283901  0.802
2007 Popovich M, Friedman EG, Secareanu RM, Hartin OL. Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 811-816. DOI: 10.1109/ICCAD.2007.4397365  0.774
2007 El-Moursy MA, Friedman EG. Wire shaping of RLC interconnects Integration, the Vlsi Journal. 40: 461-472. DOI: 10.1016/J.Vlsi.2006.06.002  0.76
2007 Rosenfeld J, Friedman EG. Quasi-resonant interconnects: A low power design methodology Proceedings - Ieee International Symposium On Circuits and Systems. 641-644.  0.387
2006 Zhang J, Haurylau M, Chen H, Chen G, Nelson NA, Albonesi DH, Friedman EG, Fauchet PM. A Semi-Analytical Simulation Model for Capacitor Based E-O Modulators Frontiers in Optics. DOI: 10.1364/Fio.2006.Fwo2  0.482
2006 Andreev B, Titlebaum EL, Friedman EG. Sizing cmos inverters with miller effect and threshold voltage variations Journal of Circuits, Systems and Computers. 15: 437-454. DOI: 10.1142/S0218126606003143  0.828
2006 Rosenfeld J, Friedman EG. Design methodology for global resonant H-tree clock distribution networks Proceedings - Ieee International Symposium On Circuits and Systems. 2073-2076. DOI: 10.1109/Tvlsi.2007.893576  0.622
2006 Zhang J, Friedman EG. Crosstalk modeling for coupled RLC interconnects with application to shield insertion Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 641-646. DOI: 10.1109/Tvlsi.2006.878223  0.415
2006 Popovich M, Friedman EG. Decoupling capacitors for multi-voltage power distribution systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 217-228. DOI: 10.1109/Tvlsi.2006.871756  0.7
2006 Chen G, Friedman EG. Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 161-172. DOI: 10.1109/Tvlsi.2005.863750  0.613
2006 Haurylau M, Chen G, Chen H, Zhang J, Nelson NA, Albonesi DH, Friedman EG, Fauchet PM. On-chip optical interconnect roadmap: Challenges and critical directions Ieee Journal On Selected Topics in Quantum Electronics. 12: 1699-1704. DOI: 10.1109/Jstqe.2006.880615  0.517
2006 Xu W, Friedman EG. On-chip test circuit for measuring substrate and line-to-line coupling noise Ieee Journal of Solid-State Circuits. 41: 474-482. DOI: 10.1109/Jssc.2005.862349  0.607
2006 Salman E, Dasdan A, Taraporevala F, Kucukcakar K, Friedman EG. Pessimism reduction in static timing analysis using interdependent setup and hold times Proceedings - International Symposium On Quality Electronic Design, Isqed. 159-164. DOI: 10.1109/ISQED.2006.100  0.623
2006 Kursun V, Friedman EG. Multi-Voltage CMOS Circuit Design Multi-Voltage Cmos Circuit Design. 1-225. DOI: 10.1002/0470033371  0.637
2006 Pavlidis VF, Friedman EG. Via placement for minimum interconnect delay in three-dimensional (3-D) circuits Proceedings - Ieee International Symposium On Circuits and Systems. 4587-4590.  0.752
2006 El-Moursy MA, Friedman EG. Optimum wire tapering for minimum power dissipation in RLC interconnects Proceedings - Ieee International Symposium On Circuits and Systems. 485-488.  0.733
2006 Chen G, Friedman EG. Effective capacitance of RLC loads for estimating short-circuit power Proceedings - Ieee International Symposium On Circuits and Systems. 2065-2068.  0.398
2005 Friedman EG. What are clock distribution networks? Acm Sigda Newsletter. 35: 1. DOI: 10.1145/1113788.1113790  0.431
2005 El-Moursy MA, Friedman EG. Shielding effect of on-chip interconnect inductance Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 396-400. DOI: 10.1109/Tvlsi.2004.842315  0.769
2005 Chen G, Friedman EG. An RLC interconnect model based on fourier analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 170-182. DOI: 10.1109/Tcad.2004.841065  0.536
2005 Popovich M, Friedman EG. Noise aware decoupling capacitors for multi-voltage power distribution systems Proceedings - International Symposium On Quality Electronic Design, Isqed. 334-339. DOI: 10.1109/ISQED.2005.84  0.664
2005 Popovich M, Friedman EG. Noise coupling in multi-voltage power distribution systems with decoupling capacitors Proceedings - Ieee International Symposium On Circuits and Systems. 620-623. DOI: 10.1109/ISCAS.2005.1464664  0.668
2005 Secareanu RM, Banerjee SK, Hartin O, Fernandez V, Friedman EG. Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment Proceedings - Ieee International Symposium On Circuits and Systems. 612-615. DOI: 10.1109/ISCAS.2005.1464662  0.762
2005 Chen G, Friedman EG. Low power repeaters driving RLC interconnects with delay and bandwidth constraints Proceedings - Ieee International Symposium On Circuits and Systems. 596-599. DOI: 10.1109/ISCAS.2005.1464658  0.376
2005 Kursun V, Schrom G, De VK, Friedman EG, Narendra SG. Cascode buffer for monolithic voltage conversion operating at high input supply voltages Proceedings - Ieee International Symposium On Circuits and Systems. 464-467. DOI: 10.1109/ISCAS.2005.1464625  0.613
2005 Kursun V, De VK, Friedman EG, Narendra SG. Monolithic voltage conversion in low-voltage CMOS technologies Microelectronics Journal. 36: 863-867. DOI: 10.1016/j.mejo.2005.03.008  0.605
2005 Kourtev IS, Friedman EG. Clock Skew Scheduling for Improved Reliability The Electrical Engineering Handbook. 231-262. DOI: 10.1016/B978-012170960-0/50021-9  0.757
2005 Kursun V, Narendra SG, De VK, Friedman EG. Cascode monolithic DC-DC converter for reliable operation at high input voltages Analog Integrated Circuits and Signal Processing. 42: 231-238. DOI: 10.1007/S10470-005-6757-6  0.638
2005 El-Moursy MA, Friedman EG. Design methodologies for on-chip inductive interconnect Interconnect-Centric Design For Advanced Soc and Noc. 85-124. DOI: 10.1007/1-4020-7836-6_4  0.745
2005 Pavlidis VF, Friedman EG. Interconnect delay minimization through interlayer via placement in 3-D ICs Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 20-25.  0.717
2004 Bhansali S, Chapman GH, Friedman E, Ismail Y, Mukund PR, Tebbe D, Jain V. 3-D heterogeneous sensor system on a chip for defense and security applications Proceedings of Spie - the International Society For Optical Engineering. 5417: 413-424. DOI: 10.1117/12.548199  0.518
2004 El-Moursy MA, Friedman EG. Exponentially tapered H-tree clock distribution networks Proceedings - Ieee International Symposium On Circuits and Systems. 2. DOI: 10.1109/Tvlsi.2005.853602  0.736
2004 El-Moursy MA, Friedman EG. Exponentially tapered H-tree clock distribution networks Proceedings - Ieee International Symposium On Circuits and Systems. 2. DOI: 10.1109/TVLSI.2005.853602  0.715
2004 Mezhiba AV, Friedman EG. Impedance characteristics of power distribution grids in nanoscale integrated circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 1148-1155. DOI: 10.1109/Tvlsi.2004.836304  0.83
2004 Kursun V, Friedman EG. Sleep switch dual threshold voltage domino logic with reduced standby leakage current Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 485-496. DOI: 10.1109/Tvlsi.2004.826198  0.643
2004 Secareanu RM, Warner S, Seabridge S, Burke C, Becerra J, Watrobski TE, Morton C, Staub W, Tellier T, Kourtev IS, Friedman EG. Substrate Coupling in Digital Circuits in Mixed-Signal Smart-Power Systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 67-78. DOI: 10.1109/Tvlsi.2003.820526  0.841
2004 Kursun V, Narendra SG, De VK, Friedman EG. Low-voltage-swing monolithic dc-dc conversion Ieee Transactions On Circuits and Systems Ii: Express Briefs. 51: 241-248. DOI: 10.1109/Tcsii.2004.827557  0.66
2004 Kursun V, Narendra SG, De VK, Friedman EG. High input voltage step-down DC-DC converters for integration in a low voltage CMOS process Proceedings - 5th International Symposium On Quality Electronic Design, Isqued 2004. 517-521. DOI: 10.1109/ISQED.2004.1283725  0.602
2004 Kursun V, Friedman EG. Node voltage dependent subthreshold leakage current characteristics of dynamic circuits Proceedings - 5th International Symposium On Quality Electronic Design, Isqued 2004. 104-109. DOI: 10.1109/ISQED.2004.1283658  0.62
2004 Andreev BD, Titlebaum EL, Friedman EG. Complex ±1 multiplier based on signed-binary transformations Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 38: 13-24. DOI: 10.1023/B:VLSI.0000028530.88948.36  0.596
2004 El-Moursy MA, Friedman EG. Resistive power in CMOS circuits Analog Integrated Circuits and Signal Processing. 41: 5-11. DOI: 10.1023/B:Alog.0000038278.71500.0C  0.756
2004 Friedman EG. Challenges in ultra deep submicrometer high performance VLSI circuits 11th Ieee International Conference On Electronics, Circuits and Systems, Icecs 2004. 238.  0.368
2004 Kursun V, Friedman EG. Forward body biased keeper for enhanced noise immunity in domino logic circuits Proceedings - Ieee International Symposium On Circuits and Systems. 2.  0.603
2004 Kursun V, Friedman EG. Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage Proceedings - Ieee International Symposium On Circuits and Systems. 2.  0.614
2004 Shem-Tov B, Kozak M, Friedman EG. A high-speed CMOS OP-Amp design technique using negative miller capacitance 11th Ieee International Conference On Electronics, Circuits and Systems, Icecs 2004. 623-626.  0.308
2004 Rosenfeld J, Kozak M, Friedman EG. A bulk-driven CMOS OTA with 68 dB DC gain 11th Ieee International Conference On Electronics, Circuits and Systems, Icecs 2004. 5-8.  0.312
2004 Shem-Tov B, Kozak M, Friedman EG. A 250 MHZ Delta-Sigma modulator for low cost ultrasound/sonar beamforming applications 11th Ieee International Conference On Electronics, Circuits and Systems, Icecs 2004. 113-116.  0.329
2004 Velenis D, Sundaresha R, Friedman EG. Buffer sizing for delay uncertainty induced by process variations 11th Ieee International Conference On Electronics, Circuits and Systems, Icecs 2004. 415-418.  0.692
2004 Chen G, Friedman EG. Low power repeaters driving RC interconnects with delay and bandwidth constraints Proceedings - Ieee International Soc Conference. 335-339.  0.347
2004 Popovich M, Friedman EG. Impedance characteristics of decoupling capacitors in multi-power distribution systems 11th Ieee International Conference On Electronics, Circuits and Systems, Icecs 2004. 160-163.  0.657
2004 Popovich M, Friedman EG. Decoupling capacitors for power distribution systems with multiple power supply voltages Proceedings - Ieee International Soc Conference. 331-334.  0.655
2004 Velenis D, Friedman EG. Buffer sizing for crosstalk induced delay uncertainty Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3254: 750-759.  0.698
2003 El-Moursy MA, Friedman EG. Power characteristics of inductive interconnect Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 2: 499-502. DOI: 10.1109/Tvlsi.2004.834227  0.761
2003 Kursun V, Friedman EG. Domino logic with variable threshold voltage keeper Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 1080-1093. DOI: 10.1109/Tvlsi.2003.817515  0.688
2003 Kursun V, Narendra SG, De VK, Friedman EG. Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 514-522. DOI: 10.1109/Tvlsi.2003.812289  0.663
2003 Rosenfeld J, Kozak M, Friedman EG. A 0.8 volt high performance OTA using bulk-driven MOSFETs for low power mixed-signal SOCs Proceedings - Ieee International Soc Conference, Socc 2003. 245-246. DOI: 10.1109/SOC.2003.1241503  0.364
2003 Ismall YI, Friedman EG. Effects of inductance on the propagation delay and repeater insertion in VLSI circuits: A summary Ieee Circuits and Systems Magazine. 3: 24-28. DOI: 10.1109/Mcas.2003.1228505  0.461
2003 Albonesi DH, Balasubramonian R, Dropsho SG, Dwarkadas S, Friedman EG, Huang MC, Kursun V, Magklis G, Scott ML, Semeraro G, Bose P, Buyuktosunoglu A, Cook PW, Schuster SE. Dynamically Tuning Processor Resources with Adaptive Processing Computer. 36: 49-50+4. DOI: 10.1109/Mc.2003.1250883  0.571
2003 Kursun V, Narendra SG, De VK, Friedman EG. Monolithic DC-DC converter analysis and MOSFET gate voltage optimization Proceedings - International Symposium On Quality Electronic Design, Isqed. 2003: 279-284. DOI: 10.1109/ISQED.2003.1194746  0.6
2003 Velenis D, Papaefthymiou MC, Friedman EG. Reduced delay uncertainty in high performance clock distribution networks Proceedings -Design, Automation and Test in Europe, Date. 68-73. DOI: 10.1109/DATE.2003.1253589  0.714
2003 Mezhiba AV, Friedman EG. Frequency characteristics of high speed power distribution grids Analog Integrated Circuits and Signal Processing. 35: 207-214. DOI: 10.1023/A:1024143019577  0.816
2003 El-Moursy MA, Friedman EG. Optimum wire sizing of RLC interconnect with repeaters Proceedings of the Ieee Great Lakes Symposium On Vlsi. 27-32. DOI: 10.1016/J.Vlsi.2004.04.001  0.743
2003 Ismail YI, Friedman EG. On the extraction of on-chip inductance Journal of Circuits, Systems and Computers. 12: 31-40. DOI: 10.1007/978-1-4615-1685-9_13  0.606
2003 El-Moursy MA, Friedman EG. Inductive interconnect width optimization for low power Proceedings - Ieee International Symposium On Circuits and Systems. 5.  0.74
2003 Mezhiba AV, Friedman EG. Electrical characteristics of multi-layer power distribution grids Proceedings - Ieee International Symposium On Circuits and Systems. 5.  0.802
2002 Ismail YI, Friedman EG, Neves JL. Inductance effects in RLC trees Journal of Circuits, Systems and Computers. 11: 305-321. DOI: 10.1142/S0218126602000458  0.713
2002 Velenis D, Tang KT, Kourtev IS, Adler V, Baez F, Friedman EG. Demonstration of speed and power enhancements on an industrial circuit through application of clock skew scheduling Journal of Circuits, Systems and Computers. 11: 231-245. DOI: 10.1142/S0218126602000410  0.829
2002 Mezhiba AV, Friedman EG. Scaling Trends of On-Chip Power Distribution Noise International Workshop On System Level Interconnect Prediction. 47-53. DOI: 10.1109/Tvlsi.2004.825834  0.841
2002 Mezhiba AV, Friedman EG. Scaling Trends of On-Chip Power Distribution Noise International Workshop On System Level Interconnect Prediction. 47-53. DOI: 10.1109/TVLSI.2004.825834  0.837
2002 Mezhiba AV, Friedman EG. Inductive properties of high-performance power distribution grids Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 762-776. DOI: 10.1109/Tvlsi.2003.808683  0.824
2002 Tang KT, Friedman EG. Simultaneous switching noise in on-chip CMOS power distribution networks Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 487-493. DOI: 10.1109/Tvlsi.2002.800533  0.548
2002 Dropsho S, Kursun V, Albonesi DH, Dwarkadas S, Friedman EG. Managing static leakage energy in microprocessor functional units Proceedings of the Annual International Symposium On Microarchitecture, Micro. 2002: 321-332. DOI: 10.1109/MICRO.2002.1176260  0.525
2002 Mezhiba AV, Friedman EG. Inductive characteristics of power distribution grids in high speed integrated circuits Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 316-321. DOI: 10.1109/ISQED.2002.996764  0.823
2002 Mezhiba AV, Friedman EG. Variation of inductance with frequency in high performance power distribution grids Proceedings of the Annual Ieee International Asic Conference and Exhibit. 2002: 421-425. DOI: 10.1109/ASIC.2002.1158096  0.81
2002 Kursun V, Friedman EG. Variable threshold voltage keeper for contention reduction in dynamic circuits Proceedings of the Annual Ieee International Asic Conference and Exhibit. 2002: 314-318. DOI: 10.1109/ASIC.2002.1158077  0.658
2002 Xu W, Friedman EG. A circuit technique for accurately measuring coupling capacitance Proceedings of the Annual Ieee International Asic Conference and Exhibit. 2002: 176-180. DOI: 10.1109/ASIC.2002.1158051  0.328
2002 Liu X, Papaefthymiou MC, Friedman EG. Retiming and clock scheduling for digital circuit optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 184-203. DOI: 10.1109/43.980258  0.39
2002 Ismail YI, Friedman EG. DTT: Direct truncation of the transfer function - An alternative to moment matching for tree structured interconnect Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 131-144. DOI: 10.1109/43.980254  0.51
2002 Tang KT, Friedman EG. Incorporating voltage fluctuations of the power distribution network into the transient analysis of CMOS logic gates Analog Integrated Circuits and Signal Processing. 31: 249-259. DOI: 10.1023/A:1015348708421  0.517
2002 Tang KT, Friedman EG. The effect of signal activity on propagation delay of CMOS logic gates driving coupled on-chip interconnections Analog Integrated Circuits and Signal Processing. 31: 209-224. DOI: 10.1023/A:1015344607513  0.429
2002 Xu W, Friedman EG. Clock feedthrough in CMOS analog transmission gate switches Proceedings of the Annual Ieee International Asic Conference and Exhibit. 2002: 181-185. DOI: 10.1007/S10470-005-3014-Y  0.611
2002 Kursun V, Friedman EG. Domino logic with dynamic body biased keeper European Solid-State Circuits Conference. 675-678.  0.646
2002 Mezhiba AV, Friedman EG. Inductance/area/resistance tradeoffs in high performance power distribution grids Proceedings - Ieee International Symposium On Circuits and Systems. 1.  0.817
2002 El-Moursy MA, Friedman EG. Optimizing inductive interconnect for low power Canadian Journal of Electrical and Computer Engineering. 27: 183-187.  0.742
2002 Kursun V, Secareanu RM, Friedman EG. CMOS voltage interface circuit for low power systems Proceedings - Ieee International Symposium On Circuits and Systems. 3.  0.815
2002 Kursun V, Narendra SG, De VK, Friedman EG. Efficiency analysis of a high frequency buck converter for on-chip integration with a dual-VDDmicroprocessor European Solid-State Circuits Conference. 743-746.  0.629
2002 Mader R, Friedman EG, Litman A, Kourtev IS. Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits Proceedings - Ieee International Symposium On Circuits and Systems. 1.  0.751
2001 Velenis D, Friedman EG, Papaefthymiou MC. A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty Materials Research Society Symposium - Proceedings. 626. DOI: 10.1109/ISCAS.2001.922263  0.694
2001 Ismail YI, Friedman EG, Neves JL. Exploiting the on-chip inductance in high-speed clock distribution networks Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 963-973. DOI: 10.1109/92.974910  0.785
2001 Ismail YI, Friedman EG, Neves JL. Repeater insertion in tree structured inductive interconnect Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 48: 471-481. DOI: 10.1109/82.938357  0.76
2001 Friedman EG. Clock distribution networks in synchronous digital integrated circuits Proceedings of the Ieee. 89: 665-692. DOI: 10.1109/5.929649  0.318
2001 Secareanu RM, Friedman EG. Applying analog techniques in digital CMOS buffers to improve speed and noise immunity Analog Integrated Circuits and Signal Processing. 27: 275-279. DOI: 10.1023/A:1011257908593  0.77
2001 Secareanu RM, Warner S, Seabridge S, Burke C, Watrobski TE, Morton C, Staub W, Tellier T, Friedman EG. Placement of substrate contacts to minimize substrate noise in mixed-signal integrated circuits Analog Integrated Circuits and Signal Processing. 28: 253-264. DOI: 10.1023/A:1011204026940  0.75
2001 Tang KT, Friedman EG. Estimation of transient voltage fluctuations in the CMOS-based power distribution networks Proceedings - Ieee International Symposium On Circuits and Systems. 5: 463-466.  0.422
2001 Secareanu RM, Albonesi D, Friedman EG. A dynamic reconfigurable clock generator Proceedings of the Annual Ieee International Asic Conference and Exhibit. 330-333.  0.72
2001 Velenis D, Friedman EG, Papaefthymiou MC. A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty Materials Research Society Symposium - Proceedings. 626.  0.3
2000 Ismail YI, Friedman EG. Effects of inductance on the propagation delay and repeater insertion in VLSI circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 195-206. DOI: 10.1109/92.831439  0.655
2000 Adler V, Friedman EG. Uniform repeater insertion in RC trees Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 47: 1515-1523. DOI: 10.1109/81.886981  0.613
2000 Ismail YI, Friedman EG, Neves JL. Equivalent Elmore delay for RLC trees Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 83-97. DOI: 10.1109/43.822622  0.709
2000 Tang KT, Friedman EG. Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections Integration, the Vlsi Journal. 29: 131-165. DOI: 10.1016/S0167-9260(00)00005-5  0.437
2000 Tang KT, Friedman EG. Estimation of On-chip simultaneous switching noise in VDSM CMOS circuits 2000 International Conference On Modeling and Simulation of Microsystems - Msm 2000. 313-316.  0.366
2000 Tang KT, Friedman EG. Lumped versus distributed RC and RLC interconnect impedances Midwest Symposium On Circuits and Systems. 1: 136-139.  0.31
2000 Tang KT, Friedman EG. Transient IR voltage drops in CMOS-based power distribution networks Midwest Symposium On Circuits and Systems. 3: 1396-1399.  0.404
2000 Secareanu RM, Friedman EG. Low power digital CMOS buffer systems for driving highly capacitive interconnect lines Midwest Symposium On Circuits and Systems. 1: 362-365.  0.772
2000 Ismail YI, Friedman EG. Fast and accurate simulation of tree structured interconnect Midwest Symposium On Circuits and Systems. 3: 1130-1134.  0.513
2000 Ismail YI, Friedman EG, Neves JL. Exploiting on-chip inductance in high speed clock distribution networks Midwest Symposium On Circuits and Systems. 3: 1236-1239.  0.769
1999 Tang KT, Friedman EG. Peak crosstalk noise estimation in CMOS VLSI circuits Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 3: 1539-1542. DOI: 10.1109/ICECS.1999.814464  0.342
1999 Liu X, Papaefthymiou MC, Friedman EG. Minimizing sensitivity to delay variations in high-performance synchronous circuits Proceedings -Design, Automation and Test in Europe, Date. 643-649. DOI: 10.1109/DATE.1999.761197  0.304
1999 Ismail YI, Friedman EG, Neves JL. Figures of merit to characterize the importance of on-chip inductance Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 7: 442-449. DOI: 10.1109/92.805751  0.767
1999 Ismail YI, Friedman EG, Neves JL. Dynamic and short-circuit power of CMOS gates driving lossless transmission lines Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 46: 950-961. DOI: 10.1109/81.780376  0.778
1999 Gaj K, Herr QP, Adler V, Brock DK, Friedman EG, Feldman MJ. Toward a systematic design methodology for large multigigahertz rapid single flux quantum circuits Ieee Transactions On Applied Superconductivity. 9: 4591-4606. DOI: 10.1109/77.791915  0.638
1999 Gaj K, Herr QP, Adler V, Krasniewski A, Friedman EG, Feldman MJ. Tools for the computer-aided design of multigigahertz superconducting digital circuits Ieee Transactions On Applied Superconductivity. 9: 18-38. DOI: 10.1109/77.763251  0.612
1999 Kourtev IS, Friedman EG. Synthesis of clock tree topologies to implement nonzero clock skew schedule Iee Proceedings: Circuits, Devices and Systems. 146: 321-326. DOI: 10.1049/ip-eds:19990582  0.772
1998 Neves JL, Friedman EG. Automated synthesis of skew-based clock distribution networks Vlsi Design. 7: 31-57. DOI: 10.1155/1998/72951  0.711
1998 Adler V, Friedman EG. Repeater design to reduce delay and power in resistive interconnect Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 45: 607-616. DOI: 10.1109/82.673643  0.69
1997 Cherkauer BS, Friedman EG. A hybrid radix-4/radix-8 low power signed multiplier architecture Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 44: 656-659. DOI: 10.1109/82.618039  0.821
1997 Hahm MD, Friedman EG, Titlebaum EL. A comparison of analog and digital circuit implementations of low power matched filters for use in portable wireless communication terminals Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 44: 498-506. DOI: 10.1109/82.592584  0.813
1997 Adler V, Cheah C, Gaj K, Brock DK, Friedman EG. A Cadence-based design environment for single flux quantum circuits Ieee Transactions On Applied Superconductivity. 7: 3294-3297. DOI: 10.1109/77.622058  0.36
1997 Herr QP, Vukovic N, Mancini CA, Gaj K, Ke Q, Adler V, Friedman EG, Krasniewski A, Bocko MF, Feldman MJ. Design and low speed testing of a four-bit RSFQ multiplier-accumulator Ieee Transactions On Applied Superconductivity. 7: 3168-3171. DOI: 10.1109/77.622003  0.452
1997 Gaj K, Cheah C, Friedman EG, Feldman MJ. Functional modeling of RSFQ circuits using Verilog HDL Ieee Transactions On Applied Superconductivity. 7: 3151-3154. DOI: 10.1109/77.622000  0.423
1997 Soyata T, Friedman EG, Mulligan JH. Incorporating interconnect, register, and clock distribution delays into the retiming process Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 105-120. DOI: 10.1109/43.559335  0.706
1997 Becerra JJ, Friedman EG. Analog Integrated Circuits and Signal Processing. 14: 5-8. DOI: 10.1023/A:1008200122141  0.452
1997 Adler V, Friedman EG. Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load Analog Integrated Circuits and Signal Processing. 14: 29-39.  0.615
1997 Neves JL, Friedman EG. Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 16: 149-161.  0.648
1996 Neves JL, Friedman EG. Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 4: 286-291. DOI: 10.1109/92.502201  0.692
1995 Cherkauer BS, Friedman EG. A Unified Design Methodology for CMOS Tapered Buffers Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 3: 99-111. DOI: 10.1109/92.365457  0.824
1995 Gaj K, Friedman EG, Feldman MJ, Krasniewski A. A Clock Distribution Scheme for Large RSFQ Circuits Ieee Transactions On Applied Superconductivity. 5: 3320-3324. DOI: 10.1109/77.403302  0.396
1995 Cherkauer BS, Friedman EG. Design of Tapered Buffers with Local Interconnect Capacitance Ieee Journal of Solid-State Circuits. 30: 151-155. DOI: 10.1109/4.341744  0.821
1994 Cherkauer BS, Friedman EG. Channel Width Tapering of Serially Connected Mosfet's with Emphasis on Power Dissipation Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2: 100-114. DOI: 10.1109/92.273155  0.84
1993 Friedman EG. Latching Characteristics of a CMOS Bistable Register Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 40: 902-908. DOI: 10.1109/81.269031  0.407
1992 Friedman EG. The limiting performance of a CMOS bistable register based on waveform considerations International Journal of Electronics. 73: 371-384. DOI: 10.1080/00207219208925674  0.32
1991 Friedman EG, Mulligan JH. Clock Frequency and Latency in Synchronous Digital Systems Ieee Transactions On Signal Processing. 39: 930-934. DOI: 10.1109/78.80915  0.383
1991 Friedman EG, Mulligan JH. Pipelining of high performance synchronous digital systems International Journal of Electronics. 70: 917-935. DOI: 10.1080/00207219108921338  0.37
1988 Yacoub GY, Pham H, Ma M, Friedman EG. A system for critical path analysis based on back annotation and distributed interconnect impedance models Microelectronics Journal. 19: 21-30. DOI: 10.1016/S0026-2692(88)80051-X  0.401
1986 Friedman E, Powell S. Design and analysis of a hierarchical clock distribution system for synchronous standard cell/macrocell VLSI Ieee Journal of Solid-State Circuits. 21: 240-246. DOI: 10.1109/Jssc.1986.1052510  0.383
1985 Friedman EG. Feedback in Silicon Compilers Ieee Circuits and Devices Magazine. 1: 15-20. DOI: 10.1109/Mcd.1985.6311966  0.303
1984 Powell S, Iodice E, Friedman E. An automated, low power, high speed complementary PLA design system for VLSI applications Microelectronics Journal. 15: 47-54. DOI: 10.1016/S0026-2692(84)80070-1  0.431
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