| Year |
Citation |
Score |
| 2020 |
Ankit A, Hajj IE, Chalamalasetti SR, Agarwal S, Marinella M, Foltin M, Strachan JP, Milojicic D, Hwu W, Roy K. PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM Ieee Transactions On Computers. 69: 1128-1142. DOI: 10.1109/Tc.2020.2998456 |
0.328 |
|
| 2018 |
Hwu W, Patel S. Accelerator Architectures A Ten-Year Retrospective Ieee Micro. 38: 56-62. DOI: 10.1109/Mm.2018.2877839 |
0.392 |
|
| 2018 |
Mutlu O, Mahlke S, Conte T, Hwu W. Iterative Modulo Scheduling Ieee Micro. 38: 115-117. DOI: 10.1109/Mm.2018.011441569 |
0.7 |
|
| 2018 |
Min S, Alian M, Hwu W, Kim NS. Semi-Coherent DMA: An Alternative I/O Coherency Management for Embedded Systems Ieee Computer Architecture Letters. 17: 221-224. DOI: 10.1109/Lca.2018.2866568 |
0.39 |
|
| 2018 |
Cecilia JM, Llanes A, Abellán JL, Gómez-Luna J, Chang L, Hwu WW. High-throughput Ant Colony Optimization on graphics processing units Journal of Parallel and Distributed Computing. 113: 261-274. DOI: 10.1016/J.Jpdc.2017.12.002 |
0.412 |
|
| 2017 |
Kim NS, Chen D, Xiong J, Hwu WW. Heterogeneous Computing Meets Near-Memory Acceleration and High-Level Synthesis in the Post-Moore Era Ieee Micro. 37: 10-18. DOI: 10.1109/Mm.2017.3211105 |
0.54 |
|
| 2016 |
Chen Y, Nguyen T, Chen Y, Gurumani ST, Liang Y, Rupnow K, Cong J, Hwu W, Chen D. FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 2032-2045. DOI: 10.1109/Tcad.2016.2552821 |
0.536 |
|
| 2016 |
Mutlu O, Belgard R, Gross TR, Jouppi NR, Hennessy JL, Przybylski S, Rowen C, Patt YN, Hwu WW, Melvin SW, Shebanow MC, Yeh T, Wolfe A. Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor Ieee Micro. 36: 70-85. DOI: 10.1109/Mm.2016.66 |
0.688 |
|
| 2010 |
Kindratenko V, Wilhelmson R, Brunner R, J. Martïnez T, Hwu W. High-Performance Computing with Accelerators Computing in Science & Engineering. 12: 12-16. DOI: 10.1109/Mcse.2010.88 |
0.385 |
|
| 2009 |
Hwu W, Rodrigues C, Ryoo S, Stratton J. Compute Unified Device Architecture Application Suitability Computing in Science & Engineering. 11: 16-26. DOI: 10.1109/Mcse.2009.48 |
0.676 |
|
| 2008 |
Patel S, Hwu WW. Accelerator Architectures Ieee Micro. 28: 4-12. DOI: 10.1109/Mm.2008.50 |
0.334 |
|
| 2008 |
Yeh D, Peh L, Borkar S, Darringer J, Agarwal A, Hwu W. Thousand-Core Chips [Roundtable] Ieee Design & Test of Computers. 25: 272-278. DOI: 10.1109/Mdt.2008.85 |
0.329 |
|
| 2008 |
Hwu W, Keutzer K, Mattson TG. The Concurrency Challenge Ieee Design & Test of Computers. 25: 312-320. DOI: 10.1109/Mdt.2008.110 |
0.427 |
|
| 2006 |
Barnes RD, Ryoo S, Hwu WW. Tolerating Cache-Miss Latency with Multipass Pipelines Ieee Micro. 26: 40-47. DOI: 10.1109/Mm.2006.25 |
0.732 |
|
| 2001 |
Monks JP, Bharghavan V, Hwu WW. A power controlled multiple access protocol for wireless packet networks Proceedings - Ieee Infocom. 1: 219-228. |
0.653 |
|
| 1997 |
Hank RE, Hwu WW, Rau BR. Region-based compilation: Introduction, motivation, and initial experience International Journal of Parallel Programming. 25: 113-146. DOI: 10.1007/Bf02700049 |
0.37 |
|
| 1994 |
Hwu W, Conte T. The susceptibility of programs to context switching Ieee Transactions On Computers. 43: 994-1003. DOI: 10.1109/12.312110 |
0.585 |
|
| 1994 |
Anik S, Hwu W. Performance Implications of Synchronization Support for Parallel Fortran Programs Journal of Parallel and Distributed Computing. 22: 202-215. DOI: 10.1006/Jpdc.1994.1081 |
0.421 |
|
| 1994 |
Chen S, Alewine NJ, Fuchs WK, Hwu WW. Incremental compiler transformations for multiple instruction retry Software: Practice and Experience. 24: 1179-1198. DOI: 10.1002/Spe.4380241206 |
0.38 |
|
| 1993 |
Chen W, Chang P, Conte T, Hwu W. The effect of code expanding optimizations on instruction cache design Ieee Transactions On Computers. 42: 1045-1057. DOI: 10.1109/12.241594 |
0.63 |
|
| 1993 |
Gupta A, Hwu WW. An execution profiler for window-oriented applications Software: Practice and Experience. 23: 487-510. DOI: 10.1002/Spe.4380230505 |
0.382 |
|
| 1992 |
Hwu WW, Chang PP. Efficient Instruction Sequencing with Inline Target Insertion Ieee Transactions On Computers. 41: 1537-1551. DOI: 10.1109/12.214662 |
0.359 |
|
| 1992 |
Chang PP, Mahlke SA, Chen WY, Hwu WW. Profile-guided automatic inline expansion for C programs Software: Practice and Experience. 22: 349-369. DOI: 10.1002/Spe.4380220502 |
0.634 |
|
| 1991 |
Conte TM, Hwu WW. A brief survey of benchmark usage in the architecture community Acm Sigarch Computer Architecture News. 19: 37-44. DOI: 10.1145/122576.122580 |
0.605 |
|
| 1991 |
Chang PP, Mahlke SA, Hwu WW. Using profile information to assist classic code optimizations Software: Practice and Experience. 21: 1301-1321. DOI: 10.1002/Spe.4380211204 |
0.635 |
|
| Show low-probability matches. |
