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Visvesh S. Sathe, Ph.D. - Publications

Affiliations: 
2007 University of Michigan, Ann Arbor, Ann Arbor, MI 
Area:
Electronics and Electrical Engineering
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32 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Uehlin JP, Smith WA, Pamula VR, Pepin EP, Perlmutter S, Sathe V, Rudell JC. A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS Ieee Journal of Solid-State Circuits. 55: 1749-1761. DOI: 10.1109/Jssc.2020.2991524  0.468
2020 Rahman Fu, Pamula R, Sathe VS. Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS Ieee Journal of Solid-State Circuits. 55: 494-504. DOI: 10.1109/Jssc.2019.2956884  0.468
2020 Shen Y, Tang X, Shen L, Zhao W, Xin X, Liu S, Zhu Z, Sathe VS, Sun N. A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique Ieee Journal of Solid-State Circuits. 55: 680-692. DOI: 10.1109/Jssc.2019.2946215  0.362
2019 Uehlin JP, Smith WA, Pamula VR, Perlmutter S, Rudell JC, Sathe VS. A 0.0023 mm/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture with Stimulus Artifact Suppression. Ieee Transactions On Biomedical Circuits and Systems. PMID 31902767 DOI: 10.1109/Tbcas.2019.2963174  0.367
2019 Sun X, Rahman Fu, Pamula VR, Kim S, Li X, John N, Sathe VS. An All-Digital Fused PLL-Buck Architecture for 82% Average V dd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor Ieee Journal of Solid-State Circuits. 54: 3215-3225. DOI: 10.1109/Jssc.2019.2936968  0.424
2019 ur Rahman F, Taylor G, Sathe V. A 1–2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation Ieee Journal of Solid-State Circuits. 54: 2487-2500. DOI: 10.1109/Jssc.2019.2926191  0.447
2019 Rahman Fu, Kim S, John N, Kumar R, Li X, Pamula R, Bowman KA, Sathe VS. A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains Ieee Journal of Solid-State Circuits. 54: 1173-1184. DOI: 10.1109/Jssc.2018.2888866  0.488
2018 Kim S, Howe P, Moreau T, Alaghi A, Ceze L, Sathe VS. Energy-Efficient Neural Network Acceleration in the Presence of Bit-Level Memory Errors Ieee Transactions On Circuits and Systems I: Regular Papers. 65: 4285-4298. DOI: 10.1109/Tcsi.2018.2839613  0.369
2018 Lee VT, Alaghi A, Pamula R, Sathe VS, Ceze L, Oskin M. Architecture Considerations for Stochastic Computing Accelerators Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 2277-2289. DOI: 10.1109/Tcad.2018.2858338  0.427
2018 Rahman Fu, Sathe V. Quasi-Resonant Clocking: Continuous Voltage-Frequency Scalable Resonant Clocking System for Dynamic Voltage-Frequency Scaling Systems Ieee Journal of Solid-State Circuits. 53: 924-935. DOI: 10.1109/Jssc.2017.2780219  0.552
2016 Smith WA, Mogen BJ, Fetz EE, Sathe VS, Otis BP. Exploiting Electrocorticographic Spectral Characteristics for Optimized Signal Chain Design: A 1.08 μW Analog Front End With Reduced ADC Resolution Requirements. Ieee Transactions On Biomedical Circuits and Systems. PMID 27071192 DOI: 10.1109/Tbcas.2016.2518923  0.364
2016 CHIANG P, SATHE VS. Introduction to the Special Issue on the 2015 Custom Integrated Circuits Conference Ieee Journal of Solid-State Circuits. DOI: 10.1109/Jssc.2016.2584198  0.393
2016 Rahman FU, Sathe VS. 19.6 voltage-scalable frequency-independent quasi-resonant clocking implementation of a 0.7-to-1.2V DVFS System Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 59: 334-335. DOI: 10.1109/ISSCC.2016.7418043  0.481
2016 Yen TT, Yu B, Sathe VS. All-digital hybrid-control buck converter for Integrated Voltage Regulator applications Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, Date 2016. 567-570.  0.319
2015 Sathe VS, Seo JS. Analysis and optimization of CMOS switched-capacitor converters Proceedings of the International Symposium On Low Power Electronics and Design. 2015: 327-334. DOI: 10.1109/ISLPED.2015.7273535  0.317
2013 Sathe VS, Arekapudi S, Ishii A, Ouyang C, Papaefthymiou MC, Naffziger S. Resonant-clock design for a power-efficient, high-volume x86-64 microprocessor Ieee Journal of Solid-State Circuits. 48: 140-149. DOI: 10.1109/JSSC.2012.2218068  0.715
2012 Kao JC, Ma WH, Sathe VS, Papaefthymiou M. Energy-efficient low-latency 600 MHz FIR with high-overdrive charge-recovery logic Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 977-988. DOI: 10.1109/Tvlsi.2011.2140346  0.815
2010 Ma WH, Kao JC, Sathe VS, Papaefthymiou MC. 187 MHz subthreshold-supply charge-recovery FIR Ieee Journal of Solid-State Circuits. 45: 793-803. DOI: 10.1109/Jssc.2010.2042247  0.803
2010 Le HP, Seeman M, Sanders SR, Sathe V, Naffziger S, Alon E. A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 53: 210-211. DOI: 10.1109/ISSCC.2010.5433981  0.32
2009 Kao JC, Ma WH, Sathe VS, Papaefthymiou M. A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead Esscirc 2009 - Proceedings of the 35th European Solid-State Circuits Conference. 160-163. DOI: 10.1109/ESSCIRC.2009.5325975  0.741
2009 Ishii AT, Kao JC, Sathe VS, Papaefthymiou MC. A resonant-clock 200MHz ARM926EJ-S™ microcontroller Esscirc 2009 - Proceedings of the 35th European Solid-State Circuits Conference. 356-359. DOI: 10.1109/ESSCIRC.2009.5325961  0.758
2009 Ma WH, Kao JC, Sathe VS, Papaefthymiou M. A 187MHz subthreshold-supply robust FIR filter with charge-recovery logic Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 202-203.  0.679
2008 Sathe VS, Kao JC, Papaefthymiou MC. Resonant-clock latch-based design Ieee Journal of Solid-State Circuits. 43: 864-872. DOI: 10.1109/Jssc.2008.917501  0.796
2007 Sathe VS, Kao JC, Papaefthymiou MC. RF2: A 1GHz FIR filter with distributed resonant clock generator Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 44-45. DOI: 10.1109/VLSIC.2007.4342759  0.779
2007 Sathe VS, Chueh JY, Papaefthymiou MC. Energy-efficient GHz-class charge-recovery logic Ieee Journal of Solid-State Circuits. 42: 38-46. DOI: 10.1109/JSSC.2006.885053  0.809
2007 Sathe VS, Kao JC, Papaefthymiou MC. A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches Proceedings of the Ieee 2007 Custom Integrated Circuits Conference, Cicc 2007. 583-586. DOI: 10.1109/CICC.2007.4405799  0.784
2007 Sathe V, Papaefthymiou MC, Kosonocky SV, Kim S. On-chip synchronous communication between clock domains with quotient frequencies Electronics Letters. 43: 496-499. DOI: 10.1049/El:20070057  0.692
2006 Chueh JY, Sathe V, Papaefthymiou MC. 900MHz to 1.2GHz two-phase resonant clock network with programmable driver and loading Proceedings of the Custom Integrated Circuits Conference. 777-780. DOI: 10.1109/CICC.2006.320995  0.754
2005 Sathe V, Chueh JY, Kim J, Ziesler CH, Kim S, Papaefthymiou MC. Fast, efficient, recovering, and irreversible 2005 Computing Frontiers Conference. 407-413. DOI: 10.1145/1062261.1062330  0.755
2005 Sathe VS, Papaefthymiou MC, Ziesler CH. Boost Logic: A high speed energy recovery circuit family Proceedings - Ieee Computer Society Annual Symposium On Vlsi - New Frontiers in Vlsi. 22-27. DOI: 10.1109/ISVLSI.2005.22  0.749
2005 Sathe VS, Papaefthymiou MC, Ziesler CH. A GHz-class charge recovery logic Proceedings of the International Symposium On Low Power Electronics and Design. 91-94.  0.745
2003 Ziesler CH, Kim J, Sathe VS, Papaefthymiou MC. A 225 MHz Resonant Clocked ASIC Chip Proceedings of the International Symposium On Low Power Electronics and Design. 48-53.  0.782
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