Wayne Burleson - Publications

Affiliations: 
Electrical & Computer Engineering University of Massachusetts, Amherst, Amherst, MA 
Area:
Computer Engineering, Electronics and Electrical Engineering

150 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Burleson W, Mutlu O, Tiwari M. Invited - Who is the major threat to tomorrow's security?: You, the hardware designer Proceedings - Design Automation Conference. 5. DOI: 10.1145/2897937.2905022  1
2015 Neshatpour K, Khajeh A, Burleson W, Homayoun H. Revisiting dynamic thermal management exploiting inverse thermal dependence Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 20: 385-390. DOI: 10.1145/2742060.2742086  1
2015 Lu S, Tessier R, Burleson W. Reinforcement learning for thermal-aware many-core task allocation Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 20: 379-384. DOI: 10.1145/2742060.2742078  1
2015 Suresh VB, Burleson WP. Entropy and Energy Bounds for Metastability based TRNG with Lightweight Post-processing Ieee Transactions On Circuits and Systems I: Regular Papers. DOI: 10.1109/TCSI.2015.2441966  1
2015 Xu X, Rahmati A, Holcomb DE, Fu K, Burleson W. Reliable physical unclonable functions using data retention voltage of SRAM Cells Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 903-914. DOI: 10.1109/TCAD.2015.2418288  1
2015 Buckler M, Vaidya A, Liu X, Burleson W. Dynamic synchronizer flip-flop performance in FinFET technologies Proceedings - 2014 8th Ieee/Acm International Symposium On Networks-On-Chip, Nocs 2014. 104-110. DOI: 10.1109/NOCS.2014.7008768  1
2015 Malik S, Becker GT, Paar C, Burleson WP. Development of a layout-level hardware obfuscation tool Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 7: 204-209. DOI: 10.1109/ISVLSI.2015.118  1
2015 Kumar R, Burleson W. Side-channel assisted modeling attacks on feed-forward arbiter PUFs using silicon data Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 9440: 53-67. DOI: 10.1007/978-3-319-24837-0_4  1
2015 Xu X, Rührmair U, Holcomb DE, Burleson W. Security evaluation and enhancement of Bistable Ring PUFs Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 9440: 3-16. DOI: 10.1007/978-3-319-24837-0_1  1
2014 Xu X, Burleson W. Hybrid side-channel/machine-learning attacks on PUFs: A new threat? Proceedings -Design, Automation and Test in Europe, Date. DOI: 10.7873/DATE2014.362  1
2014 Rührmair U, Schlichtmann U, Burleson W. Special session: How secure are PUFs really? on the reach and limits of recent PUF attacks Proceedings -Design, Automation and Test in Europe, Date. DOI: 10.7873/DATE2014.359  1
2014 Guo X, Burleson W, Stan M. Modeling and experimental demonstration of accelerated self-healing techniques Proceedings - Design Automation Conference. DOI: 10.1145/2593069.2593162  1
2014 Lu S, Tessier R, Burleson W. Dynamic on-chip thermal sensor calibration using performance counters Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 853-866. DOI: 10.1109/TCAD.2014.2302384  1
2014 Suresh VB, Burleson WP. REFLEX: Reconfigurable logic for entropy extraction International System On Chip Conference. 341-346. DOI: 10.1109/SOCC.2014.6948951  1
2014 Suresh VB, Burleson WP. Variation aware design of post-silicon tunable clock buffer Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 1-6. DOI: 10.1109/ISVLSI.2014.95  1
2014 Xu X, Suresh V, Kumar R, Burleson W. Post-silicon validation and calibration of hardware security primitives Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 29-34. DOI: 10.1109/ISVLSI.2014.80  1
2014 Zhao J, Lu S, Burleson W, Tessier R. A broadcast-enabled sensing system for embedded multi-core processors Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 190-195. DOI: 10.1109/ISVLSI.2014.18  1
2014 Suresh VB, Burleson WP. Fine grained wearout sensing using metastability resolution time Proceedings - International Symposium On Quality Electronic Design, Isqed. 480-485. DOI: 10.1109/ISQED.2014.6783363  1
2014 Buckler M, Burleson W. Predictive synchronization for DVFS-enabled multi-processor systems Proceedings - International Symposium On Quality Electronic Design, Isqed. 270-275. DOI: 10.1109/ISQED.2014.6783336  1
2014 Kumar R, Burleson W. Hybrid modeling attacks on current-based PUFs 2014 32nd Ieee International Conference On Computer Design, Iccd 2014. 493-496. DOI: 10.1109/ICCD.2014.6974725  1
2014 Kumar R, Burleson W. On design of a highly secure PUF based on non-linear current mirrors Proceedings of the 2014 Ieee International Symposium On Hardware-Oriented Security and Trust, Host 2014. 38-43. DOI: 10.1109/HST.2014.6855565  1
2014 Kumar R, Jovanovic P, Burleson W, Polian I. Parametric trojans for fault-injection attacks on cryptographic hardware Proceedings - 2014 Workshop On Fault Diagnosis and Tolerance in Cryptography, Fdtc 2014. 18-28. DOI: 10.1109/FDTC.2014.12  1
2014 Becker GT, Regazzoni F, Paar C, Burleson WP. Stealthy dopant-level hardware Trojans: Extended version Journal of Cryptographic Engineering. 4: 19-31. DOI: 10.1007/s13389-013-0068-0  1
2014 Carrara S, Burleson W. Conclusions and a vision of the future Security and Privacy For Implantable Medical Devices. 2147483647: 195-199. DOI: 10.1007/978-1-4614-1674-6_9  1
2014 Burleson W, Carrara S. Segue Security and Privacy For Implantable Medical Devices. 2147483647: 155-156. DOI: 10.1007/978-1-4614-1674-6_6  1
2014 Burleson W, Carrara S. Introduction Security and Privacy For Implantable Medical Devices. 2147483647: 1-11. DOI: 10.1007/978-1-4614-1674-6_1  1
2013 Rostami M, Burleson W, Juels A, Koushanfar F. Balancing security and utility in medical devices? Proceedings - Design Automation Conference. DOI: 10.1145/2463209.2488750  1
2013 Xu H, Pavlidis VF, Tang X, Burleson W, De Micheli G. Timing uncertainty in 3-D clock trees due to process variations and power supply noise Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 2226-2239. DOI: 10.1109/TVLSI.2012.2230035  1
2013 Kumar R, Burleson W. Litho-aware and low power design of a secure current-based physically unclonable function Proceedings of the International Symposium On Low Power Electronics and Design. 402-407. DOI: 10.1109/ISLPED.2013.6629331  1
2013 Buckler M, Burleson W, Sadowski G. Low-power Networks-on-Chip: Progress and remaining challenges Proceedings of the International Symposium On Low Power Electronics and Design. 132-134. DOI: 10.1109/ISLPED.2013.6629279  1
2013 Becker GT, Regazzoni F, Paar C, Burleson WP. Stealthy dopant-level hardware trojans Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 8086: 197-214. DOI: 10.1007/978-3-642-40349-1-12  1
2013 Hinterwälder G, Zenger CT, Baldimtsi F, Lysyanskaya A, Paar C, Burleson WP. Efficient e-cash in practice: NFC-based payments for public transportation systems Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 7981: 40-59. DOI: 10.1007/978-3-642-39077-7_3  1
2013 Burleson W, Carrara S. Security and privacy for implantable medical devices Security and Privacy For Implantable Medical Devices. 1-205. DOI: 10.1007/978-1-4614-1674-6  1
2013 Zhao J, Lu S, Burleson W, Tessier R. Run-time probabilistic detection of miscalibrated thermal sensors in many-core systems Proceedings -Design, Automation and Test in Europe, Date. 1395-1398.  1
2012 Carrara S, Ghoreishizadeh S, Olivo J, Taurino I, Baj-Rossi C, Cavallini A, de Beeck MO, Dehollain C, Burleson W, Moussy FG, Guiseppi-Elie A, De Micheli G. Fully integrated biochip platforms for advanced healthcare Sensors (Switzerland). 12: 11013-11060. PMID 23112644 DOI: 10.3390/s120811013  1
2012 Burleson W, Clark SS, Ransford B, Fu K. Design challenges for secure implantable medical devices Proceedings - Design Automation Conference. 12-17. DOI: 10.1145/2228360.2228364  1
2012 Zhao J, Tessier R, Burleson W. Distributed sensor data processing for many-cores Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 159-164. DOI: 10.1145/2206781.2206821  1
2012 Bayrak AG, Velickovic N, Ienne P, Burleson W. An architecture-independent instruction shuffler to protect against side-channel attacks Transactions On Architecture and Code Optimization. 8. DOI: 10.1145/2086696.2086699  1
2012 Jang J, Franza O, Burleson W. Compact expressions for supply noise induced period jitter of global binary clock trees Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 66-79. DOI: 10.1109/TVLSI.2010.2089706  1
2012 Becker GT, Strobel D, Paar C, Burleson W. Detecting software theft in embedded systems: A side-channel approach Ieee Transactions On Information Forensics and Security. 7: 1144-1154. DOI: 10.1109/TIFS.2012.2191964  1
2012 Kumar R, Burleson W. PHAP: Password based Hardware Authentication using PUFs Proceedings - 2012 Ieee/Acm 45th International Symposium On Microarchitecture Workshops, Microw 2012. 24-31. DOI: 10.1109/MICROW.2012.14  1
2012 Xu H, Pavlidis VF, Burleson W, De Micheli G. The combined effect of process variations and power supply noise on clock skew and jitter Proceedings - International Symposium On Quality Electronic Design, Isqed. 320-327. DOI: 10.1109/ISQED.2012.6187512  1
2012 Suresh VB, Burleson WP. Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration Proceedings - International Symposium On Quality Electronic Design, Isqed. 298-305. DOI: 10.1109/ISQED.2012.6187509  1
2012 Lu S, Tessier R, Burleson W. Collaborative calibration of on-chip thermal sensors using performance counters Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 15-22.  1
2011 Datta B, Burleson W. Temperature effects on practical energy optimization of sub-threshold circuits in deep nanometer technologies Journal of Low Power Electronics. 7: 403-419. DOI: 10.1166/jolpe.2011.1148  1
2011 Datta B, Burleson W. A high sensitivity and process tolerant digital thermal sensing scheme for 3-D Ics Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 289-294. DOI: 10.1145/1973009.1973067  1
2011 Datta B, Burleson W. A 45.6μ 2 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 133-138. DOI: 10.1145/1973009.1973037  1
2011 Jang J, Burleson W. An arbiter based on-chip droop detector system Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 1-6. DOI: 10.1145/1973009.1973011  1
2011 Zhao J, Madduri S, Vadlamani R, Burleson W, Tessier R. A dedicated monitoring infrastructure for multicore processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1011-1022. DOI: 10.1109/TVLSI.2010.2043964  1
2011 Todd M, Burleson W, Tessier R. The design and assessment of a secure passive RFID sensor system 2011 Ieee 9th International New Circuits and Systems Conference, Newcas 2011. 494-497. DOI: 10.1109/NEWCAS.2011.5981327  1
2011 Becker GT, Burleson W, Paar C. Side-channel watermarks for embedded software 2011 Ieee 9th International New Circuits and Systems Conference, Newcas 2011. 478-481. DOI: 10.1109/NEWCAS.2011.5981323  1
2011 Datta B, Burleson W. A 12.4μm2 133.4μW 4.56mV/°C resolution digital on-chip thermal sensing circuit in 45nm CMOS utilizing sub-threshold operation Proceedings of the 12th International Symposium On Quality Electronic Design, Isqed 2011. 67-73. DOI: 10.1109/ISQED.2011.5770705  1
2010 Lin L, Holcomb D, Krishnappa DK, Shabadi P, Burleson W. Low-power sub-threshold design of secure physical unclonable functions Proceedings of the International Symposium On Low Power Electronics and Design. 43-48. DOI: 10.1145/1840845.1840855  1
2010 Datta B, Burleson W. Circuit-level NBTI macro-models for collaborative reliability monitoring Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 453-458. DOI: 10.1145/1785481.1785586  1
2010 Datta B, Burleson W. Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performance Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 341-346. DOI: 10.1145/1785481.1785559  1
2010 Zhao J, Datta B, Burleson W, Tessier R. Thermal-aware voltage droop compensation for multi-core architectures Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 335-340. DOI: 10.1145/1785481.1785558  1
2010 Datta B, Burleson W. Calibration of on-chip thermal sensors using process monitoring circuits Proceedings of the 11th International Symposium On Quality Electronic Design, Isqed 2010. 461-467. DOI: 10.1109/ISQED.2010.5450535  1
2010 Suresh VB, Burleson WP. Entropy extraction in metastability-based TRNG Proceedings of the 2010 Ieee International Symposium On Hardware-Oriented Security and Trust, Host 2010. 135-140. DOI: 10.1109/HST.2010.5513099  1
2010 Vadlamani R, Zhao J, Burleson W, Tessier R. Multicore soft error rate stabilization using adaptive dual modular redundancy Proceedings -Design, Automation and Test in Europe, Date. 27-32.  1
2009 Datta B, Burleson W. Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 145-148. DOI: 10.1145/1531542.1531579  1
2009 Holcomb DE, Burleson WP, Fu K. Power-Up SRAM state as an identifying fingerprint and source of true random numbers Ieee Transactions On Computers. 58: 1198-1210. DOI: 10.1109/TC.2008.212  1
2009 Datta B, Burleson W. Temperature effects on energy optimization in sub-threshold circuit design Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 680-685. DOI: 10.1109/ISQED.2009.4810375  1
2009 Datta B, Burleson W. On temperature planarization effect of copper dummy fills in deep nanometer technology Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 494-499. DOI: 10.1109/ISQED.2009.4810344  1
2009 Lin L, Kasper M, Güneysu T, Paar C, Burleson W. Trojan side-channels: Lightweight hardware Trojans through side-channel engineering Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5747: 382-395. DOI: 10.1007/978-3-642-04138-9_27  1
2009 Lin L, Burleson W. Analysis and mitigation of process variation impacts on power-attack tolerance Proceedings - Design Automation Conference. 238-243.  1
2009 Lin L, Burleson W, Paar C. MOLES: Malicious off-chip leakage enabled by side-channels Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 117-122.  1
2009 Madduri S, Vadlamani R, Burleson W, Tessier R. A monitor interconnect and support subsystem for multicore processors Proceedings -Design, Automation and Test in Europe, Date. 761-766.  1
2008 Arunachalam V, Burleson W. Low-power clock distribution in a multilayer core 3D microprocessor Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 429-434. DOI: 10.1145/1366110.1366212  1
2008 Datta B, Burleson W. Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 41-46. DOI: 10.1145/1366110.1366123  1
2008 Jang J, Franza O, Burleson W. Period jitter estimation in global clock trees 12th Ieee Workshop On Signal Propagation On Interconnects, Spi. DOI: 10.1109/SPI.2008.4558367  1
2008 Datta B, Burleson WP. Temperature measurement in content addressable memory cells using bias-controlled VCO 2008 Ieee International Soc Conference, Socc. 147-150. DOI: 10.1109/SOCC.2008.4641499  1
2008 Lin L, Burleson W. Leakage-based differential power analysis (LDPA) on Sub-90nm CMOS cryptosystems Proceedings - Ieee International Symposium On Circuits and Systems. 252-255. DOI: 10.1109/ISCAS.2008.4541402  1
2008 Jang J, Franza O, Burleson W. Compact expressions for period jitter of global binary clock trees Electrical Performance of Electronic Packaging, Epep. 47-49. DOI: 10.1109/EPEP.2008.4675873  1
2008 Venkatraman V, Burleson W. An energy-efficient multi-bit quaternary current-mode signaling for on-chip interconnects Proceedings of the Custom Integrated Circuits Conference. 301-304. DOI: 10.1109/CICC.2007.4405738  1
2007 Datta B, Burleson WP. Low power on-chip thermal sensors based on wires 2007 Ifip International Conference On Very Large Scale Integration, Vlsi-Soc. 258-263. DOI: 10.1109/VLSISOC.2007.4402508  1
2007 Maheshwari A, Burleson W. Current-sensing and repeater hybrid circuit technique for on-chip interconnects Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 1239-1244. DOI: 10.1109/TVLSI.2007.904109  1
2007 Venkatraman V, Anders M, Kaul H, Burleson W, Krishnamurthy R. A low-swing signaling circuit technique for 65nm on-chip interconnects 2006 Ieee International Systems-On-Chip Conference, Soc. 289-292. DOI: 10.1109/SOCC.2006.283900  1
2007 Sheng X, Benito I, Burleson W. Thermal impacts on NoC interconnects Proceedings - Nocs 2007: First International Symposium On Networks-On-Chip. 220. DOI: 10.1109/NOCS.2007.43  1
2007 Datta B, Burleson W. Low-power and robust on-chip thermal sensing using differential ring oscillators Midwest Symposium On Circuits and Systems. 29-32. DOI: 10.1109/MWSCAS.2007.4488534  1
2007 Kumar D, Burleson W. Distributed collaborative adaptive sensing: A unifying theme for a junior level embedded systems course Proceedings - Mse 2007: 2007 Ieee International Conference On Microelectronic Systems Education: Educating Systems Designers For the Global Economy and a Secure World. 47-48. DOI: 10.1109/MSE.2007.35  1
2006 Benito I, Venkatraman V, Burleson W. Process variation-aware vdd assignment technique for repeated interconnects Midwest Symposium On Circuits and Systems. 2: 370-374. DOI: 10.1109/MWSCAS.2006.382289  1
2006 Xu S, Venkatraman V, Burleson W. Energy-aware differential current sensing for global on-chip interconnects Midwest Symposium On Circuits and Systems. 1: 718-722. DOI: 10.1109/MWSCAS.2006.382163  1
2006 Gogniat G, Wolf T, Burleson W. Reconfigurable security support for embedded systems Proceedings of the Annual Hawaii International Conference On System Sciences. 10. DOI: 10.1109/HICSS.2006.409  1
2006 Bossuet L, Gogniat G, Burleson W. Dynamically configurable security for SRAM FPGA bitstreams International Journal of Embedded Systems. 2: 73-85.  1
2005 Tessier R, Jasinski D, Maheshwari A, Natarajan A, Xu W, Burleson W. An energy-aware active smart card Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 1190-1199. DOI: 10.1109/TVLSI.2005.859471  1
2005 Tessier R, Swaminathan S, Ramaswamy R, Goeckel D, Burleson W. A reconfigurable, power-efficient adaptive Viterbi decoder Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 484-488. DOI: 10.1109/TVLSI.2004.842930  1
2005 Heath MW, Burleson WP, Harris IG. Synchro-tokens: A deterministic GALS methodology for chip-level debug and test Ieee Transactions On Computers. 54: 1532-1546. DOI: 10.1109/TC.2005.203  1
2005 Burleson W, Xu S. Digital systems design with ASIC and FPGA: A novel course using CD/DVD and on-line formats Proceedings - 2005 Ieee International Conference On Microelectronic Systems Education, Mse '05 - Promoting Excellence and Innovation in Microelectronic Systems Education. 2005: 3-4. DOI: 10.1109/MSE.2005.27  1
2005 Natarajan A, Shankar V, Maheshwari A, Burleson W. Sensing design issues in deep submicron CMOS SRAMs Proceedings - Ieee Computer Society Annual Symposium On Vlsi - New Frontiers in Vlsi. 42-45. DOI: 10.1109/ISVLSI.2005.67  1
2005 Venkatraman V, Burleson W. Robust multi-level current-mode on-chip interconnect signaling in the presence of process variations Proceedings - International Symposium On Quality Electronic Design, Isqed. 522-527. DOI: 10.1109/ISQED.2005.107  1
2005 Hsu S, Venkatraman V, Mathew S, Kaul H, Anders M, Dighe S, Burleson W, Krishnamurthy R. A 2GHz 13.6mW 12×9b multiplier for energy efficient FFT accelerators Proceedings of Esscirc 2005: 31st European Solid-State Circuits Conference. 199-202. DOI: 10.1109/ESSCIR.2005.1541594  1
2005 Euh J, Chittamuru J, Burleson W. Power-aware 3D computer graphics rendering Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 39: 15-33. DOI: 10.1023/B:VLSI.0000047269.03965.e9  1
2005 Venkatraman V, Burleson W. Impact of process variations on multi-level signaling for on-chip interconnects Proceedings of the Ieee International Conference On Vlsi Design. 362-367.  1
2005 Hoffman O, Dobosh P, Djaferis T, Burleson W. Moving towards a more systems approach in a robotics based introductory engineering course at Mount Holyoke College Asee Annual Conference and Exposition, Conference Proceedings. 10547-10562.  1
2005 Jang J, Xu S, Burleson W. Jitter in deep sub-micron interconnect Proceedings - Ieee Computer Society Annual Symposium On Vlsi - New Frontiers in Vlsi. 84-89.  1
2005 Gogniat G, Wolf T, Burleson W. Reconfigurable security primitive for embedded systems 2005 International Symposium On System-On-Chip, Proceedings. 2005: 23-28.  1
2005 Gogniat G, Burleson W, Bossuet L. Configurable computing for high-security/high-performance ambient systems Lecture Notes in Computer Science. 3553: 72-81.  1
2004 Maheshwari A, Burleson W. Differential current-sensing for on-chip interconnects Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 1321-1329. DOI: 10.1109/TVLSI.2004.837987  1
2004 Maheshwari A, Burleson W, Tessier R. Trading Off Transient Fault Tolerance and Power Consumption in Deep Submicron (DSM) VLSI Circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 299-311. DOI: 10.1109/TVLSI.2004.824302  1
2004 Maheshwari A, Koren I, Burleson W. Accurate estimation of soft error rate (SER) in VLSI circuits Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 377-385. DOI: 10.1109/DFTVS.2004.1347862  1
2004 Heath MW, Burleson WP, Harris IG. Synchro-tokens: Eliminating nondeterminism to enable chip-level test of globally-asynchronous locally-synchronous SoC's Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 410-415. DOI: 10.1109/DATE.2004.1268881  1
2004 Venkatraman V, Maheshwari A, Burleson W. Mitigating static power in current-sensed interconnects Proceedings of the Acm Great Lakes Symposium On Vlsi. 224-229.  1
2003 Maheshwari A, Koren I, Burleson W. Techniques for transient fault sensitivity analysis and reduction in VLSI circuits Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 2003: 597-604. DOI: 10.1109/TSM.2005.1250160  1
2003 Chittamuru J, Burleson W, Euh J. Dynamic wordlength variation for low-power 3D graphics texture mapping Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 2003: 251-256. DOI: 10.1109/SIPS.2003.1235678  1
2003 Laffely A, Burleson W. Using system-on-a-chip as a vehicle for VLSI design education Proceedings - 2003 Ieee International Conference On Microelectronic Systems Education: Educating Tomorrow's Microsystems Designers, Mse 2003. 148-149. DOI: 10.1109/MSE.2003.1205293  1
2003 Srinivasaraghavan S, Burleson W. Interconnect effort - a unification of repeater insertion and logical effort Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 2003: 55-61. DOI: 10.1109/ISVLSI.2003.1183353  1
2003 Adrion WR, Burleson W, Cooper W, Israel WL, Kurose J, Watts K. Excite: Enabling x-campus information technology education Proceedings - Frontiers in Education Conference, Fie. 3: S4F18-S4F23. DOI: 10.1109/FIE.2003.1266036  1
2003 Maheshwari A, Burleson W. Repeater and current-sensing hybrid circuits for on-chip interconnects Proceedings of the Ieee Great Lakes Symposium On Vlsi. 269-272.  1
2003 Euh J, Chittamuru J, Burleson W. A low-power content-adaptive texture mapping architecture for real-time 3D graphics Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2325: 99-109.  1
2003 Natarajan A, Jasinski D, Burleson W, Tessier R. A hybrid adiabatic content addressable memory for ultra low-power applications Proceedings of the Ieee Great Lakes Symposium On Vlsi. 72-75.  1
2003 Laffely A, Liang J, Tessier R, Burleson W. Adaptive System on a Chip (aSoC): A backbone for power-aware signal processing cores Ieee International Conference On Image Processing. 3: 105-108.  1
2002 Euh J, Chittamuru J, Burleson W. CORDIC vector interpolator for power-aware 3D computer graphics Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 2002: 240-245. DOI: 10.1109/SIPS.2002.1049716  1
2002 Maheshwari A, Srinivasaraghavan S, Burleson W. Quantifying the impact of current-sensing on interconnect delay trends Proceedings of the Annual Ieee International Asic Conference and Exhibit. 2002: 461-465. DOI: 10.1109/ASIC.2002.1158103  1
2002 Burleson W, Kelley S, Thampuran S. A new course in multimedia systems for non-technical majors Asee Annual Conference Proceedings. 13253-13262.  1
2002 Swaminathan S, Tessier R, Goeckel D, Burleson W. A dynamically reconfigurable adaptive Viterbi decoder Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 227-236.  1
2002 Burleson W, Thampuran S, Ramaswamy N. Multimedia systems: Enabling computer engineering education Proceedings - Frontiers in Education Conference. 1.  1
2002 Burleson W, Cooper W, Kurose J, Thampuran S, Watts K. An empirical study of student interaction with CD-based multimedia courseware Asee Annual Conference Proceedings. 13309-13321.  1
2001 Maheshwari A, Burleson W. Current sensing techniques for global interconnects in very deep submicron (VDSM) CMOS Proceedings - Ieee Computer Society Workshop On Vlsi, Wvlsi 2001. 66-70. DOI: 10.1109/IWV.2001.923141  1
2001 Burleson W, Jain P, Venkatraman S. Dynamically parameterized architectures for power-aware video coding: Motion estimation and DCT Proceedings - 2nd International Workshop On Digital and Computational Video, Dcv 2001. 4-12. DOI: 10.1109/DCV.2001.929936  1
2001 Burleson W, Shanbhag N. Guest editorial: Reconfigurable signal processing systems Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 28: 5-6. DOI: 10.1023/A:1008171903873  1
2001 Tessier R, Burleson W. Reconfigurable computing for digital signal processing: A survey Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 28: 7-27. DOI: 10.1023/A:1008155020711  1
2001 Nalamalpu A, Burleson W. Boosters for driving long on-chip interconnects: Design issues, interconnect synthesis and comparison with repeaters Proceedings of the International Symposium On Physical Design. 204-211.  1
2001 Sinha M, Burleson W. Current-sensing for crossbars Proceedings of the Annual Ieee International Asic Conference and Exhibit. 25-29.  1
2001 Nalamalpu A, Burleson W. A practical approach to DSM repeater insertion: Satisfying delay constraints while minimizing area and power Proceedings of the Annual Ieee International Asic Conference and Exhibit. 152-156.  1
2001 Euh J, Burleson W. Exploiting content variation and perception in power-aware 3D graphics rendering Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2008: 51-64.  1
2001 Thampuran S, Burleson W, Watts K. Multimedia distance learning without the wait Proceedings - Frontiers in Education Conference. 1.  1
2001 Burleson W, Ganz A, Harris I. Educational Innovations in Multimedia Systems Journal of Engineering Education. 90.  1
2001 Laffely A, Liang J, Jain P, Burleson W, Tessier R. Adaptive systems on a chip (aSoC) for low-power signal processing Conference Record of the Asilomar Conference On Signals, Systems and Computers. 2: 1217-1221.  1
2000 Peden J, Burleson W, Leonardo C. The multimedia online collaboration architecture: Tools to enable distance learning Ieee International Conference On Multi-Media and Expo. 593-596.  1
1999 Burleson W, Ko J, Niehaus D, Ramamritham K, Stankovic JA, Wallace G, Weems C. The spring scheduling coprocessor: A scheduling accelerator Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 7: 38-47. DOI: 10.1109/92.748199  1
1999 Park SR, Burleson W. Configuration cloning: Exploiting regularity in dynamic DSP architectures Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 81-89.  1
1999 Garcia A, Burleson W, Danger JL. Power modelling in field programmable gate arrays (FPGA) Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1673: 396-404.  1
1998 Jung B, Burleson WP. Efficient VLSI for Lempel-Ziv compression in wireless data communication networks Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 475-483. DOI: 10.1109/92.711318  1
1998 Burleson WP, Ciesielski M, Klass F, Liu W. Wave-pipelining: A tutorial and research survey Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 464-474. DOI: 10.1109/92.711317  1
1998 Park SR, Burleson W. Reconfiguration for power saving in real-time motion estimation Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 5: 3037-3040.  1
1998 Jung B, Burleson WP. Performance optimization of wireless local area networks through VLSI data compression Wireless Networks. 4: 27-39.  1
1997 Stan MR, Burleson WP. Low-power encodings for global communication in CMOS VLSI Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 5: 444-455. DOI: 10.1109/92.645071  1
1997 Jeong YJ, Burleson WP. VLSI array algorithms and architectures for RSA modular multiplication Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 5: 211-217. DOI: 10.1109/92.585224  1
1996 Jung B, Burleson W. VLSI array architectures for pyramid vector quantization Ieee Workshop On Vlsi Signal Processing, Proceedings. 349-358.  1
1996 Jung B, Burleson W. VLSI array architectures for pyramid vector quantization Ieee Workshop On Vlsi Signal Processing, Proceedings. 349-358.  1
1995 Stan MR, Burleson WP. Bus-Invert Coding for Low-Power I/O Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 3: 49-58. DOI: 10.1109/92.365453  1
1994 Jeong YJ, Burleson W. Vlsi Array Synthesis for Polynomial Gcd Computation and Application to Finite Field Division Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 41: 891-897. DOI: 10.1109/81.340851  1
1994 Stan MR, Burleson WP, Connolly CI, Grupen RA. Analog VLSI for robot path planning Journal of Vlsi Signal Processing. 8: 61-73. DOI: 10.1007/BF02407111  1
1994 Stan MR, Burleson WP, Connolly CI, Grupen RA. Analog VLSI for robot path planning Analog Integrated Circuits and Signal Processing. 6: 61-73. DOI: 10.1007/BF01250736  1
1994 Choi H, Burleson WP. Search-based wordlength optimization for VLSI/DSP synthesis Ieee Workshop On Vlsi Signal Processing, Proceedings. 198-207.  1
1994 Burleson WP, Lee CY, Tan EJ. 150 MHz wave-pipelined adaptive digital filter in 2 μm CMOS Ieee Workshop On Vlsi Signal Processing, Proceedings. 296-305.  1
1993 Choi H, Burleson WP, Phatak DS. Fixed-point roundoff error analysis of large feedforward neural networks Proceedings of the International Joint Conference On Neural Networks. 2: 1947-1950.  1
1991 Burleson WP, Scharf LL. A VLSI design methodology for distributed arithmetic Journal of Vlsi Signal Processing. 2: 235-252. DOI: 10.1007/BF00925468  1
1990 Burleson WP. Polynomial Evaluation in VLSI Using Distributed Arithmetic Ieee Transactions On Circuits and Systems. 37: 1299-1304. DOI: 10.1109/31.103226  1
1989 Burleson WP, Scharf LL, Gabriel AR, Endsley NH. A Systolic VLSI Chip for Implementing Orthogonal Transforms Ieee Journal of Solid-State Circuits. 24: 466-469. DOI: 10.1109/4.18610  1
Show low-probability matches.