David L. Kencke, Ph.D. - Publications

Affiliations: 
2000 University of Texas at Austin, Austin, Texas, U.S.A. 
Area:
Electronics and Electrical Engineering, Computer Science

29 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2015 Roy U, Kencke DL, Pramanik T, Register LF, Banerjee SK. Write error rate in spin-transfer-torque random access memory including micromagnetic effects Device Research Conference - Conference Digest, Drc. 2015: 147-148. DOI: 10.1109/DRC.2015.7175598  0.64
2012 Avci UE, Kencke DL, Chang PLD. Floating-body diode-a novel DRAM device Ieee Electron Device Letters. 33: 161-163. DOI: 10.1109/Led.2011.2177239  0.64
2010 Ban I, Avci UE, Kencke DL, Tolchinsky P, Chang PLD. Integration of back-gate doping for 15-nm node floating body cell (FBC) memory Digest of Technical Papers - Symposium On Vlsi Technology. 159-160. DOI: 10.1109/VLSIT.2010.5556210  0.64
2010 Spadini G, Karpov IV, Kencke DL. Future high density memories for computing applications: Device behavior and modeling challenges International Conference On Simulation of Semiconductor Processes and Devices, Sispad. 223-226. DOI: 10.1109/SISPAD.2010.5604521  0.64
2008 Ban I, Avci UE, Kencke DL, Chang PLD. A scaled floating body cell (FBC) memory with high-k+metal gate on thin-silicon and thin-BOX for 16-nm technology node and beyond Digest of Technical Papers - Symposium On Vlsi Technology. 92-93. DOI: 10.1109/VLSIT.2008.4588575  0.64
2008 Avci UE, Ban I, Kencke DL, Chang PLD. Floating body cell (FBC) memory for 16-nm technology with low variation on thin silicon and 10-nm BOX Proceedings - Ieee International Soi Conference. 29-30. DOI: 10.1109/SOI.2008.4656279  0.64
2008 Reifenberg JP, Kencke DL, Goodson KE. The impact of thermal boundary resistance in phase-change memory devices Ieee Electron Device Letters. 29: 1112-1114. DOI: 10.1109/Led.2008.2003012  0.64
2007 Kencke DL, Karpov IV, Johnson BG, Lee SJ, Kau D, Hudgens SJ, Reifenberg JP, Savransky SD, Zhang J, Giles MD, Spadini G. The role of interfaces in Damascene phase-change memory Technical Digest - International Electron Devices Meeting, Iedm. 323-326. DOI: 10.1109/IEDM.2007.4418936  0.64
2006 Ban I, Avci UE, Shah U, Barns CE, Kencke DL, Chang P. Floating body cell with independently-controlled double gates for high density memory Technical Digest - International Electron Devices Meeting, Iedm. DOI: 10.1109/IEDM.2006.346847  0.64
2005 Cadien KC, Reshotko MR, Block BA, Bowen AM, Kencke DL, Davids P. Challenges for on-chip optical interconnects Progress in Biomedical Optics and Imaging - Proceedings of Spie. 5730: 133-143. DOI: 10.1117/12.591163  0.64
2004 Reshotko MR, Kencke DL, Block B. High-speed CMOS compatible photodetectors for optical interconnects Proceedings of Spie - the International Society For Optical Engineering. 5564: 146-155. DOI: 10.1117/12.557049  0.64
2002 Wang X, Kencke DL, Liu KC, Register LF, Banerjee SK. Band alignments in sidewall strained Si/strained SiGe heterostructures Solid-State Electronics. 46: 2021-2025. DOI: 10.1016/S0038-1101(02)00247-2  0.64
2000 Ouyang Q, Chen X, Mudanai SP, Wang X, Kencke DL, Tasch AF, Register LF, Banerjee SK. A novel Si/SiGe heterojunction pMOSFET with reduced short-channel effects and enhanced drive current Ieee Transactions On Electron Devices. 47: 1943-1949. DOI: 10.1109/16.870577  0.64
2000 Wang X, Kencke DL, Liu KC, Tasch AF, Register LF, Banerjee SK. Monte Carlo simulation of electron transport in simple orthorhombically strained silicon Journal of Applied Physics. 88: 4717-4724. DOI: 10.1063/1.1311304  0.64
2000 Kencke DL, Ouyang Q, Chen W, Wang H, Mudanai S, Tasch A, Banerjee SK. Tinkering with the well-tempered MOSFET: Source-channel barrier modulation with high-permittivity dielectrics Superlattices and Microstructures. 27: 207-214. DOI: 10.1006/Spmi.1999.0803  0.64
2000 Wang X, Kencke DL, Liu KC, Tasch AF, Register LF, Banerjee SK. Electron transport properties in novel orthorhombically-strained silicon material explored by the Monte Carlo method International Conference On Simulation of Semiconductor Processes and Devices, Sispad. 70-73.  0.64
2000 Wang X, Kencke DL, Liu KC, Tasch AF, Register LF, Banerjee SK. Monte Carlo simulation of electron transport in simple orthorhombically strained silicon Journal of Applied Physics. 88: 4717-4724.  0.64
2000 Kencke DL, Wang X, Ouyang Q, Mudanai S, Tasch A. J, Banerjee SK. Enhanced secondary electron injection in novel SiGe flash memory devices Technical Digest - International Electron Devices Meeting. 105.  0.64
2000 Ouyang Q, Chen XD, Mudanai S, Kencke DL, Wang X, Tasch AF, Register LF, Banerjee SK. Two-dimensional bandgap engineering in a novel Si/SiGe pMOSFET with enhanced device performance and scalability International Conference On Simulation of Semiconductor Processes and Devices, Sispad. 151-154.  0.64
2000 Ouyang Q, Chen XD, Mudanai S, Kencke DL, Tasch AF, Banerjee SK. Bandgap engineering in deep submicron vertical pMOSFETs Annual Device Research Conference Digest. 27-28.  0.64
1999 Kencke DL, Chen W, Wang H, Mudanai S, Ouyang Q, Tasch A, Banerjee SK. Source-side barrier effects with very high-K dielectrics in 50 nm Si MOSFETs Annual Device Research Conference Digest. 22-23.  0.64
1998 Kencke DL, Richart R, Garg S, Banerjee SK. A multilevel approach toward quadrupling the density of flash memory Ieee Electron Device Letters. 19: 86-88. DOI: 10.1109/55.661173  0.64
1998 Kencke DL, Wang X, Wang H, Ouyang Q, Jallepalli S, Rashed M, Maziar C, Tasch A, Banerjee SK. Origin of secondary electron gate current: A multiple-stage Monte Carlo study for scaled, low-power flash memory Technical Digest - International Electron Devices Meeting. 889-892.  0.64
1997 Liu KC, Ray SK, Oswal SK, Chakraborti NB, Chang RD, Kencke DL, Banerjee SK. Enhancement of drain current in vertical SiGe/Si PMOS transistors using novel CMOS technology Annual Device Research Conference Digest. 128-129.  0.64
1996 Kencke DL, Richart R, Garg S, Banerjee SK. Sixteen level scheme enabling 64Mbit flash memory using 16Mbit technology Technical Digest - International Electron Devices Meeting. 937-939.  0.64
1995 Hu CY, Kencke DL, Banerjee SK, Richart R, Bandyopadhyay B, Moore B, Ibok E, Garg S. A Convergence Scheme for Over-Erased Flash EEPROM's Using Substrate-Bias-Enhanced Hot Electron Injection Ieee Electron Device Letters. 16: 500-502. DOI: 10.1109/55.468280  0.64
1995 Hu C‐, Kencke DL, Banerjee S, Bandyopadhyay B, Ibok E, Garg S. Determining effective dielectric thicknesses of metal‐oxide‐semiconductor structures in accumulation mode Applied Physics Letters. 66: 1638-1640. DOI: 10.1063/1.113877  0.44
1995 Hu CY, Kencke DL, Banerjee S, Bandyopadhyay B, Ibok E, Garg S. Determining effective dielectric thicknesses of metal-oxide-semiconductor structures in accumulation mode Applied Physics Letters. 1638.  0.64
1995 Hu CY, Kencke DL, Banerjee SK, Richart R, Bandyopadhyay B, Moore B, Ibok E, Garg S. Substrate-current-induced hot electron (SCIHE) injection: a new convergence scheme for flash memory Technical Digest - International Electron Devices Meeting. 283-286.  0.64
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