Sivakumar P. Mudanai, Ph.D. - Publications

Affiliations: 
2001 University of Texas at Austin, Austin, Texas, U.S.A. 
Area:
Electronics and Electrical Engineering

15 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Roy AS, Sarkar A, Mudanai SP. Compact modeling of magnetic tunneling junctions Ieee Transactions On Electron Devices. 63: 652-658. DOI: 10.1109/TED.2015.2510368  0.64
2014 Roy AS, Mudanai SP, Basu D, Stettler MA. Compact model for ultrathin low electron effective mass double gate MOSFET Ieee Transactions On Electron Devices. 61: 308-313. DOI: 10.1109/TED.2013.2290779  0.64
2011 Roy AS, Mudanai SP, Stettler M. Mechanism of long-channel drain-induced barrier lowering in halo MOSFETs Ieee Transactions On Electron Devices. 58: 979-984. DOI: 10.1109/TED.2011.2109387  0.64
2010 Kotlyar R, Giles MD, Mudanai SP, Kuhn KJ, Cea SM, Linton TD, Pillarisetty R. Compressive uniaxial stress bandstructure engineering for transferred-hole devices Ieee Electron Device Letters. 31: 878-880. DOI: 10.1109/LED.2010.2050053  0.64
2006 Li F, Mudanai SP, Fan YY, Register LF, Banerjee SK. Physically based quantum - Mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT ∼ 1nm) SiO2 and high-k gate stacks Ieee Transactions On Electron Devices. 53: 1096-1106. DOI: 10.1109/Ted.2006.871877  0.64
2003 Li F, Mudanai SP, Fan YY, Register LF, Banerjee SK. Compact model of MOSFET electron tunneling current through ultra-thin SiO<inf>2</inf> and high-k gate stacks Device Research Conference - Conference Digest, Drc. 2003: 47-48. DOI: 10.1109/DRC.2003.1226865  0.64
2003 Li F, Mudanai SP, Fan YY, Zhao W, Register LF, Banerjee SK. A simulated annealing approach for automatic extraction of device and material parameters of MOS with SiO2/high-K gate stacks Biennial University/Government/Industry Microelectronics Symposium - Proceedings. 218-221.  0.64
2002 Mudanai S, Li F, Samavedam SB, Tobin PJ, Kang CS, Nieh R, Lee JC, Register LF, Banerjee SK. Interfacial defect states in HfO2 and ZrO2 nMOS capacitors Ieee Electron Device Letters. 23: 728-730. DOI: 10.1109/Led.2002.805753  0.64
2001 Mudanai S, Register LF, Tasch AF, Banerjee SK. Understanding the effects of wave function penetration on the inversion layer capacitance of NMOSFETs Ieee Electron Device Letters. 22: 145-147. DOI: 10.1109/55.910624  0.64
2000 Ouyang Q, Chen X, Mudanai SP, Wang X, Kencke DL, Tasch AF, Register LF, Banerjee SK. A novel Si/SiGe heterojunction pMOSFET with reduced short-channel effects and enhanced drive current Ieee Transactions On Electron Devices. 47: 1943-1949. DOI: 10.1109/16.870577  0.64
2000 Mudanai S, Fan YY, Ouyang Q, Tasch AF, Banerjee SK. Modeling of direct tunneling current through gate dielectric stacks Ieee Transactions On Electron Devices. 47: 1851-1857. DOI: 10.1109/16.870561  0.64
2000 Kencke DL, Ouyang Q, Chen W, Wang H, Mudanai S, Tasch A, Banerjee SK. Tinkering with the well-tempered MOSFET: Source-channel barrier modulation with high-permittivity dielectrics Superlattices and Microstructures. 27: 207-214. DOI: 10.1006/Spmi.1999.0803  0.64
1999 Mudanai S, Chindalore GL, Shih W-, Wang H, Ouyang Q, Tasch AF, Maziar CM, Banerjee SK. Models for electron and hole mobilities in MOS accumulation layers Ieee Transactions On Electron Devices. 46: 1749-1759. DOI: 10.1109/16.777166  0.64
1999 Chindalore G, Mudanai S, Shih WK, Tasch AF, Maziar CM. Temperature dependence characterization of effective electron and hole mobilities in the accumulation layers of N- and P-type MOSFET's Ieee Transactions On Electron Devices. 46: 1290-1294. DOI: 10.1109/16.766900  0.64
1998 Chindalore GL, McKeon JB, Mudanai S, Hareland SA, Shih WK, Wang C, Tasch AF, Maziar CM. An improved technique and experimental results for the extraction of electron and hole mobilities in MOS accumulation layers Ieee Transactions On Electron Devices. 45: 502-511. DOI: 10.1109/16.658687  0.64
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