Year |
Citation |
Score |
2017 |
Morad TY, Shomron G, Erez M, Kolodny A, Weiser UC. Optimizing Read-Once Data Flow in Big-Data Applications Ieee Computer Architecture Letters. 16: 68-71. DOI: 10.1109/Lca.2016.2520927 |
0.319 |
|
2016 |
Manevich R, Cidon I, Kolodny A. Design and dynamic management of hierarchical NoCs Microprocessors and Microsystems. 40: 154-166. DOI: 10.1016/J.Micpro.2015.09.004 |
0.319 |
|
2016 |
Morad TY, Shalev N, Keidar I, Kolodny A, Weiser UC. EFS: Energy-Friendly Scheduler for memory bandwidth constrained systems Journal of Parallel and Distributed Computing. 95: 3-14. DOI: 10.1016/J.Jpdc.2016.03.007 |
0.391 |
|
2015 |
Soudry D, Di Castro D, Gal A, Kolodny A, Kvatinsky S. Memristor-based multilayer neural networks with online gradient descent training. Ieee Transactions On Neural Networks and Learning Systems. 26: 2408-21. PMID 25594981 DOI: 10.1109/Tnnls.2014.2383395 |
0.708 |
|
2015 |
Patel R, Kvatinsky S, Friedman EG, Kolodny A. Multistate register based on resistive RAM Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 1750-1759. DOI: 10.1109/Tvlsi.2014.2347926 |
0.746 |
|
2015 |
Ben-Itzhak Y, Cidon I, Kolodny A, Shabun M, Shmuel N. Heterogeneous NoC Router Architecture Ieee Transactions On Parallel and Distributed Systems. 26: 2479-2492. DOI: 10.1109/Tpds.2014.2351816 |
0.388 |
|
2015 |
Kvatinsky S, Ramadan M, Friedman EG, Kolodny A. VTEAM: A General Model for Voltage-Controlled Memristors Ieee Transactions On Circuits and Systems Ii: Express Briefs. 62: 786-790. DOI: 10.1109/Tcsii.2015.2433536 |
0.743 |
|
2015 |
Ben-Itzhak Y, Cidon I, Kolodny A. Average latency and link utilization analysis of heterogeneous wormhole NoCs Integration, the Vlsi Journal. 51: 92-106. DOI: 10.1016/J.Vlsi.2015.07.002 |
0.32 |
|
2015 |
Moiseev K, Wimer S, Kolodny A. Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing Integration, the Vlsi Journal. 48: 116-128. DOI: 10.1016/J.Vlsi.2014.03.002 |
0.368 |
|
2014 |
Kvatinsky S, Satat G, Wald N, Friedman EG, Kolodny A, Weiser UC. Memristor-based material implication (IMPLY) logic: Design principles and methodologies Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 2054-2066. DOI: 10.1109/Tvlsi.2013.2282132 |
0.751 |
|
2014 |
Kvatinsky S, Belousov D, Liman S, Satat G, Wald N, Friedman EG, Kolodny A, Weiser UC. MAGIC - Memristor-aided logic Ieee Transactions On Circuits and Systems Ii: Express Briefs. 61: 895-899. DOI: 10.1109/Tcsii.2014.2357292 |
0.76 |
|
2014 |
Kvatinsky S, Nacson YH, Etsion Y, Friedman EG, Kolodny A, Weiser UC. Memristor-based multithreading Ieee Computer Architecture Letters. 13: 41-44. DOI: 10.1109/L-Ca.2013.3 |
0.745 |
|
2014 |
Zahavi E, Keslassy I, Kolodny A. Distributed adaptive routing convergence to non-blocking DCN routing assignments Ieee Journal On Selected Areas in Communications. 32: 88-101. DOI: 10.1109/Jsac.2014.140109 |
0.313 |
|
2014 |
Kvatinsky S, Nacson YH, Etsion Y, Kolodny A, Weiser UC, Patel R, Friedman EG. Memristive multistate pipeline register International Workshop On Cellular Nanoscale Networks and Their Applications. DOI: 10.1109/CNNA.2014.6888594 |
0.688 |
|
2014 |
Manevich R, Polishuk L, Cidon I, Kolodny A. Designing single-cycle long links in hierarchical NoCs Microprocessors and Microsystems. 38: 814-825. DOI: 10.1016/J.Micpro.2014.05.005 |
0.351 |
|
2014 |
Levy Y, Bruck J, Cassuto Y, Friedman EG, Kolodny A, Yaakobi E, Kvatinsky S. Logic operations in memory using a memristive Akers array Microelectronics Journal. 45: 1429-1437. DOI: 10.1016/J.Mejo.2014.06.006 |
0.739 |
|
2013 |
Zahavie E, Cidon I, Kolodny A. Gana: A novel low-cost conflict-free NOC architecture Transactions On Embedded Computing Systems. 12. DOI: 10.1145/2485984.2485997 |
0.345 |
|
2013 |
Kvatinsky S, Friedman EG, Kolodny A, Weiser UC. TEAM: Threshold adaptive memristor model Ieee Transactions On Circuits and Systems I: Regular Papers. 60: 211-221. DOI: 10.1109/Tcsi.2012.2215714 |
0.742 |
|
2013 |
Kvatinsky S, Friedman EG, Kolodny A, Weiser UC. The desired memristor for circuit designers Ieee Circuits and Systems Magazine. 13: 17-22. DOI: 10.1109/Mcas.2013.2256257 |
0.75 |
|
2013 |
Abdelhadi A, Ginosar R, Kolodny A, Friedman EG. Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks Integration, the Vlsi Journal. 46: 382-391. DOI: 10.1016/J.Vlsi.2012.12.001 |
0.562 |
|
2012 |
Morad TY, Kolodny A, Weiser UC. Task scheduling based on thread essence and resource limitations Journal of Computers. 7: 53-64. DOI: 10.4304/Jcp.7.1.53-64 |
0.31 |
|
2012 |
Vaisband I, Friedman EG, Ginosar R, Kolodny A. Energy metrics for power efficient crosslink and mesh topologies Iscas 2012 - 2012 Ieee International Symposium On Circuits and Systems. 1656-1659. DOI: 10.1109/ISCAS.2012.6271575 |
0.522 |
|
2012 |
Kvatinsky S, Talisveyberg K, Fliter D, Kolodny A, Weiser UC, Friedman EG. Models of memristors for SPICE simulations 2012 Ieee 27th Convention of Electrical and Electronics Engineers in Israel, Ieeei 2012. DOI: 10.1109/EEEI.2012.6377081 |
0.618 |
|
2012 |
Kvatinsky S, Wald N, Satat G, Kolodny A, Weiser UC, Friedman EG. MRL - Memristor Ratioed Logic International Workshop On Cellular Nanoscale Networks and Their Applications. DOI: 10.1109/CNNA.2012.6331426 |
0.647 |
|
2012 |
Vishnyakov V, Friedman EG, Kolodny A. Multi-aggressor capacitive and inductive coupling noise modeling and mitigation Microelectronics Journal. 43: 235-243. DOI: 10.1016/J.Mejo.2011.12.007 |
0.484 |
|
2012 |
Moiseev K, Kolodny A, Wimer S. The complexity of VLSI power-delay optimization by interconnect resizing Journal of Combinatorial Optimization. 23: 292-300. DOI: 10.1007/S10878-010-9355-1 |
0.31 |
|
2011 |
Vaisband I, Friedman EG, Ginosar R, Kolodny A. Low power clock network design Journal of Low Power Electronics and Applications. 1: 219-246. DOI: 10.3390/Jlpea1010219 |
0.569 |
|
2011 |
Aizik Y, Kolodny A. Finding the energy efficient curve: Gate sizing for minimum power under delay constraints Vlsi Design. 2011. DOI: 10.1155/2011/845957 |
0.409 |
|
2011 |
Kvatinsky S, Kolodny A, Weiser UC, Friedman EG. Memristor-based IMPLY logic design procedure Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 142-147. DOI: 10.1109/ICCD.2011.6081389 |
0.695 |
|
2011 |
Krimer E, Keslassy I, Kolodny A, Walter I, Erez M. Static timing analysis for modeling QoS in networks-on-chip Journal of Parallel and Distributed Computing. 71: 687-699. DOI: 10.1016/J.Jpdc.2010.10.003 |
0.348 |
|
2010 |
Abdelhadi A, Ginosar R, Kolodny A, Friedman EG. Timing-driven variation-aware nonuniform clock mesh synthesis Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 15-20. DOI: 10.1145/1785481.1785487 |
0.506 |
|
2010 |
Morgenshtein A, Friedman EG, Ginosar R, Kolodny A. Corrections to “Unified Logical Effort—A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect” [May 10 689-696] Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1262-1262. DOI: 10.1109/Tvlsi.2010.2052421 |
0.529 |
|
2010 |
Dobkin RR, Moyal M, Kolodny A, Ginosar R. Asynchronous current mode serial communication Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1107-1117. DOI: 10.1109/Tvlsi.2009.2020859 |
0.406 |
|
2010 |
Morgenshtein A, Friedman EG, Ginosar R, Kolodny A. Unified logical effort - A method for delay evaluation and minimization in logic paths with RC interconnect Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 689-696. DOI: 10.1109/Tvlsi.2009.2014239 |
0.584 |
|
2010 |
Moiseev K, Kolodny A, Wimer S. Interconnect bundle sizing under discrete design rules Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1650-1654. DOI: 10.1109/Tcad.2010.2051633 |
0.352 |
|
2010 |
Kvatinsky S, Friedman EG, Kolodny A, Schächter L. Power grid analysis based on a macro circuit model 2010 Ieee 26th Convention of Electrical and Electronics Engineers in Israel, Ieeei 2010. 708-712. DOI: 10.1109/EEEI.2010.5662121 |
0.729 |
|
2009 |
Moiseev K, Kolodny A, Wimer S. Power-delay optimization in VLSI microprocessors by wire spacing Acm Transactions On Design Automation of Electronic Systems. 14. DOI: 10.1145/1562514.1562523 |
0.36 |
|
2009 |
Vaisband I, Ginosar R, Kolodny A, Friedman EG. Power efficient tree-based crosslinks for skew reduction Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 285-290. DOI: 10.1145/1531542.1531609 |
0.512 |
|
2009 |
Kolodny A, Peh LS. Special section on international symposium on networks-on-chip (NOCS) Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 317-318. DOI: 10.1109/Tvlsi.2009.2012524 |
0.347 |
|
2009 |
Dobkin R(, Ginosar R, Kolodny A. QNoC asynchronous router Integration, the Vlsi Journal. 42: 103-115. DOI: 10.1016/J.Vlsi.2008.03.001 |
0.355 |
|
2008 |
Moiseev K, Kolodny A, Wimer S. Timing-aware power-optimal ordering of signals Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1391962.1391973 |
0.323 |
|
2008 |
Morgenshtein A, Friedman EG, Ginosar R, Kolodny A. Timing optimization in logic with interconnect International Workshop On System Level Interconnect Prediction, Slip. 1-9. DOI: 10.1145/1353610.1353615 |
0.524 |
|
2008 |
Popovich M, Friedman EG, Sotman M, Kolodny A. On-chip power distribution grids with multiple supply voltages for high-performance integrated circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 908-921. DOI: 10.1109/Tvlsi.2008.2000515 |
0.548 |
|
2008 |
Popovich M, Sotman M, Kolodny A, Friedman EG. Effective radii of on-chip decoupling capacitors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 894-907. DOI: 10.1109/Tvlsi.2008.2000454 |
0.582 |
|
2008 |
Walter I, Cidon I, Kolodny A. BENoC: A bus-enhanced network on-chip for a power efficient CMP Ieee Computer Architecture Letters. 7: 61-64. DOI: 10.1109/L-Ca.2008.11 |
0.397 |
|
2008 |
Aizik Y, Kolodny A. Exploration of energy-delay tradeoffs in digital circuit design Ieee Convention of Electrical and Electronics Engineers in Israel, Proceedings. 1-5. DOI: 10.1109/EEEI.2008.4736618 |
0.31 |
|
2008 |
Moiseev K, Wimer S, Kolodny A. On optimal ordering of signals in parallel wire bundles Integration, the Vlsi Journal. 41: 253-268. DOI: 10.1016/J.Vlsi.2007.06.002 |
0.327 |
|
2007 |
Guz Z, Walter I, Bolotin E, Cidon I, Ginosar R, Kolodny A. Network Delays and Link Capacities in Application-Specific Wormhole NoCs Vlsi Design. 2007: 1-15. DOI: 10.1155/2007/90941 |
0.335 |
|
2007 |
Guz Z, Keidar I, Kolodny A, Weiser UC. Nahalal: Cache organization for Chip Multiprocessors Ieee Computer Architecture Letters. 6. DOI: 10.1109/L-Ca.2007.6 |
0.312 |
|
2006 |
Moreinis M, Morgenshtein A, Wagner IA, Kolodny A. Logic Gates as Repeaters (LGR) for area-efficient timing optimization Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 1276-1281. DOI: 10.1109/Tvlsi.2006.886400 |
0.422 |
|
2006 |
Wimer S, Michaely S, Moiseev K, Kolodny A. Optimal bus sizing in migration of processor design Ieee Transactions On Circuits and Systems I: Regular Papers. 53: 1089-1100. DOI: 10.1109/Tcsi.2006.869902 |
0.318 |
|
2005 |
Dolev N, Kornfeld A, Kolodny A. Comparison Of Sigma–Delta Converter Circuit Architectures In Digital Cmos Technology Journal of Circuits, Systems, and Computers. 14: 515-532. DOI: 10.1142/S0218126605002507 |
0.424 |
|
2004 |
Bolotin E, Cidon I, Ginosar R, Kolodny A. Cost considerations in network on chip Integration, the Vlsi Journal. 38: 19-42. DOI: 10.1016/J.Vlsi.2004.03.006 |
0.336 |
|
2004 |
Bolotin E, Cidon I, Ginosar R, Kolodny A. QNoC: QoS architecture and design process for network on chip Journal of Systems Architecture. 50: 105-128. DOI: 10.1016/J.Sysarc.2003.07.004 |
0.33 |
|
2003 |
Milter O, Kolodny A. Crosstalk noise reduction in synthesized digital logic circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 1153-1158. DOI: 10.1109/Tvlsi.2003.817551 |
0.397 |
|
2002 |
Elboim Y, Kolodny A, Ginosar R. A clock tuning circuit for system-on-chip European Solid-State Circuits Conference. 607-610. DOI: 10.1109/Tvlsi.2003.812371 |
0.412 |
|
1986 |
Kolodny A, Nieh STK, Eitan B, Shappir J. Analysis and Modeling of Floating-Gate EEPROM Cells Ieee Transactions On Electron Devices. 33: 835-844. DOI: 10.1109/T-Ed.1986.22576 |
0.357 |
|
1979 |
Kolodny A. Current Gain of Shallow-Junction Lateral Transistors Ieee Transactions On Electron Devices. 26: 987-989. DOI: 10.1109/T-Ed.1979.19530 |
0.308 |
|
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