Year |
Citation |
Score |
2019 |
Moon T, Choi HW, Keezer DC, Chatterjee A. Efficient Built-In Test and Calibration of High Speed Serial I/O Systems Using Monobit Signal Acquisition Journal of Electronic Testing. 35: 809-822. DOI: 10.1007/S10836-019-05842-8 |
0.473 |
|
2015 |
Telikepalli S, Swaminathan M, Keezer D. A Simple Technique for Power Distribution With Better Characteristics Than Electromagnetic Bandgap Structures Ieee Transactions On Components, Packaging and Manufacturing Technology. 5: 797-805. DOI: 10.1109/Tcpmt.2015.2432837 |
0.318 |
|
2015 |
Zhang DC, Swaminathan M, Keezer D. Application of a New Power Distribution Scheme for Complex Printed Circuit Boards for High-Speed Signaling Ieee Transactions On Components, Packaging and Manufacturing Technology. 5: 806-817. DOI: 10.1109/Tcpmt.2015.2431191 |
0.383 |
|
2015 |
Keezer DC, Chen TH, Moon T, Stonecypher DT, Chatterjee A, Choi HW, Kim SY, Yoo H. An FPGA-based ATE extension module for low-cost multi-GHz memory test Proceedings - 2015 20th Ieee European Test Symposium, Ets 2014. DOI: 10.1109/ETS.2015.7138756 |
0.312 |
|
2014 |
Moon T, Choi HW, Keezer DC, Chatterjee A. Multi-channel testing architecture for high-speed eye-diagram using pin electronics and subsampling monobit reconstruction algorithms Proceedings of the Ieee Vlsi Test Symposium. DOI: 10.1109/VTS.2014.6818768 |
0.306 |
|
2013 |
Keezer DC, Gray CE, Chen TH, Majid A. Practical methods for extending ATE to 40 and 50Gbps Proceedings - International Test Conference. DOI: 10.1109/TEST.2013.6651876 |
0.657 |
|
2013 |
Telikepalli S, Zhang DC, Swaminathan M, Keezer D. Constant Voltage-Based Power Delivery Scheme for 3-D ICs and Interposers Ieee Transactions On Components, Packaging and Manufacturing Technology. 3: 1907-1916. DOI: 10.1109/Tcpmt.2013.2272938 |
0.337 |
|
2012 |
Keezer DC, Chen TH, Gray CE, Choi HW, Kim S, Lee S, Yoo H. Multi-gigahertz arbitrary timing generator and data pattern serializer/formatter Proceedings - International Test Conference. DOI: 10.1109/TEST.2012.6401544 |
0.607 |
|
2012 |
Keezer DC, Chen TH, Gray CE, Choi H, Kim S, Lee S, Yoo H. Multi-gigahertz test signal synthesis with "timing-on-the-fly" Proceedings of the 2012 Ieee 18th International Mixed-Signal, Sensors, and Systems Test Workshop, Ims3tw 2012. 61-66. DOI: 10.1109/IMS3TW.2012.22 |
0.662 |
|
2012 |
Chang HM, Keezer DC. Guest editorial: Special issue on analog, mixed-signal, RF, and MEMS testing Journal of Electronic Testing: Theory and Applications (Jetta). 28: 555-556. DOI: 10.1007/S10836-012-5330-3 |
0.563 |
|
2011 |
Majid AM, Keezer DC. Multi-function multi-GHz ATE extension using state-of-the-art FPGAs Proceedings - International Test Conference. DOI: 10.1109/TEST.2011.6139161 |
0.741 |
|
2011 |
Keezer DC, Gray CE. Extending low-cost test signal synthesis to 40 Gbps Proceedings - 2011 Ieee 17th International Mixed-Signals, Sensors and Systems Test Workshop, Ims3tw 2011. 64-66. DOI: 10.1109/IMS3TW.2011.37 |
0.699 |
|
2011 |
Gray C, Keezer DC, Wang H, Bergman K. Burst-mode transmission and data recovery for multi-GHz optical packet switching network testing Proceedings of the Asian Test Symposium. 545-551. DOI: 10.1109/ATS.2011.81 |
0.399 |
|
2011 |
Gray CE, Keezer DC. Extending a DWDM optical network test system to 12 Gbps x4 channels Journal of Electronic Testing: Theory and Applications (Jetta). 27: 351-361. DOI: 10.1007/S10836-011-5216-9 |
0.667 |
|
2011 |
Keezer DC, Gray CE. Two methods for 24 Gbps test signal synthesis Proceedings -Design, Automation and Test in Europe, Date. 579-582. |
0.607 |
|
2010 |
Keezer DC, Gray CE. Extending a DWDM optical network test system to 10 Gbps x4 Proceedings of the 2010 Ieee 16th International Mixed-Signals, Sensors and Systems Test Workshop, Ims3tw 2010. DOI: 10.1109/IMS3TW.2010.5503000 |
0.579 |
|
2010 |
Keezer D, Gray C, Minier D, Ducharme P. Low-Cost 20 Gbps Digital Test Signal Synthesis Using SiGe and InP Logic Journal of Electronic Testing. 26: 87-96. DOI: 10.1007/S10836-009-5124-4 |
0.73 |
|
2010 |
Majid AM, Keezer DC. Stretching the limits of FPGA SerDes for enhanced ATE performance Proceedings -Design, Automation and Test in Europe, Date. 202-207. |
0.77 |
|
2009 |
Keezer DC, Gray C, Majid A, Minier D, Ducharme P. A development platform and electronic modules for automated test up to 20 Gbps Proceedings - International Test Conference. DOI: 10.1109/TEST.2009.5355701 |
0.309 |
|
2009 |
Majid AM, Keezer DC. A 5-Gbps test system for wafer-level packaged devices Ieee Transactions On Electronics Packaging Manufacturing. 32: 144-151. DOI: 10.1109/Tepm.2009.2017773 |
0.767 |
|
2009 |
Keezer DC, Gray C, Minier D, Ducharme P. Demonstration of 20 Gbps digital test signal synthesis using sige and InP logic 2009 Ieee 15th International Mixed-Signals, Sensors, and Systems Test Workshop, Ims3tw '09. DOI: 10.1109/IMS3TW.2009.5158693 |
0.455 |
|
2008 |
Keezer DC, Minier D, Ducharme P, Viens D, Flynn G, McKillop J. MEMS switches and SiGe logic for multi-GHz loopback testing Vlsi Design. 2008. DOI: 10.1155/2008/291686 |
0.567 |
|
2008 |
Keezer DC, Minier D, Ducharme P, Majid A. An electronic module for 12.8 Gbps multiplexing and loopback test Proceedings - International Test Conference. DOI: 10.1109/TEST.2008.4700624 |
0.477 |
|
2008 |
Gray CE, Liboiron-Ladouceur O, Keezer DC, Bergman K. Co-development of test electronics and PCI express interface for a multi-Gbps optical switching network Proceedings - International Test Conference. DOI: 10.1109/TEST.2007.4437623 |
0.636 |
|
2008 |
Keezer DC, Minier D, Ducharme P, Viens D, Flynn G, McKillop JS. Multi-GHz loopback testing using MEMs switches and SiGe logic Proceedings - International Test Conference. DOI: 10.1109/TEST.2007.4437581 |
0.503 |
|
2008 |
Keezer DC, Minier D, Ducharme P. Picosecond delay adjustment for 12.8 Gbps multiplexed testing 2008 Ieee 14th International Mixed-Signals, Sensors, and Systems Test Workshop, Ims3tw. DOI: 10.1109/IMS3TW.2008.4581626 |
0.494 |
|
2008 |
Keezer DC, Minier D, Ducharme P. Variable delay of multi-gigahertz digital signals for deskew and jitter-injection test applications Proceedings -Design, Automation and Test in Europe, Date. 1486-1491. DOI: 10.1109/DATE.2008.4484884 |
0.403 |
|
2007 |
Majid AM, Keezer DC, Jayabalan J, Rotaru MR. Multi-gigahertz testing of wafer-level packaged devices Proceedings - International Test Conference. DOI: 10.1109/TEST.2006.297669 |
0.704 |
|
2007 |
Keezer DC, Minier D, Ducharme P. Method for reducing jitter in multi-gigahertz ATE Proceedings -Design, Automation and Test in Europe, Date. 701-706. DOI: 10.1109/DATE.2007.364677 |
0.41 |
|
2006 |
Keezer DC, Minier D, Ducharme P. Source-synchronous testing of multilane PCI Express and HyperTransport buses Ieee Design and Test of Computers. 23: 46-57. DOI: 10.1109/Mdt.2006.23 |
0.427 |
|
2006 |
Liboiron-Ladouceur O, Gray C, Keezer DC, Bergman K. Bit-parallel message exchange and data recovery in optical packet switched interconnection networks Ieee Photonics Technology Letters. 18: 779-781. DOI: 10.1109/Lpt.2006.871651 |
0.6 |
|
2006 |
Gray CE, Liboiron-Ladouceur O, Keezer DC, Bergman K. Test electronics for a multi-Gbps optical packet switching network Proceedings of the Electronic Packaging Technology Conference, Eptc. 373-378. DOI: 10.1109/EPTC.2006.342745 |
0.59 |
|
2005 |
Keezer DC, Gray C, Majid A, Taher N. Low-cost multi-gigahertz test systems using CMOS FPGAs and PECL Proceedings -Design, Automation and Test in Europe, Date '05. 152-157. DOI: 10.1109/DATE.2005.203 |
0.451 |
|
2005 |
Majid AM, Keezer DC, Karia JV. A 5 Gbps wafer-level tester Proceedings of the Asian Test Symposium. 2005: 58-63. DOI: 10.1109/ATS.2005.5 |
0.771 |
|
2005 |
Majid AM, Keezer DC. An improved low-cost 6.4 gbps wafer-level tester Proceedings of 7th Electronics Packaging Technology Conference, Eptc 2005. 2: 814-819. |
0.766 |
|
2004 |
Keezer DC, Minier D, Caron MC. Multiplexing ATE channels for production testing at 2.5 Gbps Ieee Design and Test of Computers. 21: 288-301. DOI: 10.1109/Mdt.2004.37 |
0.571 |
|
2004 |
Majid AM, Keezer DC, Taher N, Gray C, Ahmad J. Performance characteristics of a 5 Gbps functional test module Proceedings of 6th Electronics Packaging Technology Conference, Eptc 2004. 244-248. |
0.752 |
|
2003 |
Keezer DC, Patel CS, Bakir MS, Zhou Q, Meindl JD. Electrical test strategies for a wafer-level packaging technology [Abstracts of Forthcoming Manuscripts] Ieee Transactions On Electronics Packaging Manufacturing. 26: 264-264. DOI: 10.1109/Tepm.2003.823162 |
0.368 |
|
2003 |
Keezer DC, Patel CS, Bakir MS, Zhou Q, Meindl JD. Electrical test strategies for a wafer-level packaging technology Ieee Transactions On Electronics Packaging Manufacturing. 26: 267-272. DOI: 10.1109/TEPM.2003.822063 |
0.308 |
|
2003 |
Keezer DC, Davis JS, Bezos S, Minier D, Caron MC, Bergman K, Liboiron-Labouceur O. Low-cost strategies for testing multi-gigahertz SOPs and components Proceedings of 5th Electronics Packaging Technology Conference, Eptc 2003. 410-414. DOI: 10.1109/EPTC.2003.1271556 |
0.442 |
|
2003 |
Davis JS, Keezer DC, Liboiron-Ladouceur O, Bergman K. Application and Demonstration of a Digital Test Core: Optoelectronic Test Bed and Wafer-level Prober Ieee International Test Conference (Tc). 166-174. |
0.476 |
|
2003 |
Keezer DC, Minier D, Caron MC. A Production-Oriented Multiplexing System for Testing above 2.5 Gbps Ieee International Test Conference (Tc). 191-200. |
0.478 |
|
2002 |
Keezer DC, Davis JS, Ang S, Rotaru M. A test strategy for nanoscale wafer level packaged circuits Proceedings of 4th Electronics Packaging Technology Conference, Eptc 2002. 175-179. DOI: 10.1109/EPTC.2002.1185663 |
0.462 |
|
2002 |
Davis JS, Keezer DC. Multi-purpose digital test core utilizing programmable logic Ieee International Test Conference (Tc). 438-445. |
0.466 |
|
2002 |
Thacker HD, Bakir MS, Keezer DC, Martin KP, Meindl JD. Compliant probe substrates for testing high pin-count chip scale packages Proceedings - Electronic Components and Technology Conference. 1188-1193. |
0.437 |
|
2001 |
Venkataratnam A, Newman KE, Keezer DC. A prototype for time-based parallel inspection of substrate networks Proceedings of Spie - the International Society For Optical Engineering. 4428: 26-30. |
0.375 |
|
2001 |
Keezer DC, Zhou Q, Bair C, Kuan J, Poole B. Terabit-per-second automated digital testing Ieee International Test Conference (Tc). 1143-1151. |
0.498 |
|
1999 |
Keezer DC, Zhou Q. Test support processors for enhanced testability of high performance circuits Ieee International Test Conference (Tc). 801-809. |
0.441 |
|
1998 |
Newman KE, Keezer DC. Prototype test system for massively-parallel electrical testing of high density interconnect substrates Proceedings of the International Symposium and Exhibition On Advanced Packaging Materials Processes, Properties and Interfaces. 138. |
0.381 |
|
1998 |
Newman KE, Keezer DC, Davis JS. A Parallel Test Method for MCM Substrate Interconnection Networks International Journal of Microcircuits and Electronic Packaging. 21: 197-204. |
0.389 |
|
1998 |
Keezer DC, Zhou Q. Alternative interface methods for testing high speed bidirectional signals Ieee International Test Conference (Tc). 824-830. |
0.47 |
|
1997 |
Newman KE, Keezer DC. Low-cost massively-parallel interconnect test method for MCM substrates Ieee International Test Conference (Tc). 370-378. |
0.329 |
|
1997 |
Keezer DC, Wenzel RJ. Low cost ATE pin electronics for multigigabit-per-second at-speed test Ieee International Test Conference (Tc). 94-100. |
0.403 |
|
1995 |
Keezer DC. Fault isolation and performance characterization of high speed digital multichip modules Proceedings of the Ieee Multi-Chip Module Conference. 26-31. DOI: 10.1109/96.475266 |
0.391 |
|
1992 |
Keezer DC, Wenzel RJ. Calibration techniques for a gigahertz test system Proceedings - International Test Conference. 1992: 530-537. DOI: 10.1109/TEST.1992.527865 |
0.378 |
|
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