Bevan M. Baas - Publications

Affiliations: 
Electrical and Computer Engineering University of California, Davis, Davis, CA 
Area:
Electronics and Electrical Engineering, Computer Engineering

45 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Ogunfunmi T, McAllister J, Baas B, Chakraborty M. Correction to: Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop Journal of Signal Processing Systems. 92: 1043-1043. DOI: 10.1007/S11265-020-01589-0  0.32
2020 Ogunfunmi T, McAllister J, Baas B, Chakraborty M. Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop Journal of Signal Processing Systems. 92: 1039-1041. DOI: 10.1007/S11265-020-01580-9  0.32
2017 Bohnenstiehl B, Stillmaker A, Pimentel J, Andreas T, Liu B, Tran A, Adeagbo E, Baas B. KiloCore: A Fine-Grained 1,000-Processor Array for Task-Parallel Applications Ieee Micro. 37: 63-69. DOI: 10.1109/Mm.2017.34  0.32
2016 Pimentel JJ, Bohnenstiehl B, Baas BM. Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2580142  1
2016 Pimentel JJ, Stillmaker A, Bohnenstiehl B, Baas BM. Area efficient backprojection computation with reduced floating-point word width for SAR image formation Conference Record - Asilomar Conference On Signals, Systems and Computers. 2016: 732-736. DOI: 10.1109/ACSSC.2015.7421230  1
2015 Liu B, Foroozannejad MH, Ghiasi S, Baas BM. Optimizing power of many-core systems by exploiting dynamic voltage, frequency and core scaling Midwest Symposium On Circuits and Systems. 2015. DOI: 10.1109/MWSCAS.2015.7282189  1
2015 Liu B, Bohnenstiehl B, Baas BM. Scalable hardware-based power management for many-core systems Conference Record - Asilomar Conference On Signals, Systems and Computers. 2015: 1834-1838. DOI: 10.1109/ACSSC.2014.7094785  1
2015 Pimentel JJ, Baas BM. Hybrid floating-point modules with low area overhead on a fine-grained processing core Conference Record - Asilomar Conference On Signals, Systems and Computers. 2015: 1829-1833. DOI: 10.1109/ACSSC.2014.7094784  1
2014 Tran AT, Baas BM. Achieving high-performance on-chip networks with shared-buffer routers Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 1391-1403. DOI: 10.1109/Tvlsi.2013.2268548  1
2014 Xiao Z, Baas BM. Processor tile shapes and interconnect topologies for dense on-chip networks Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 1377-1390. DOI: 10.1109/Tvlsi.2013.2265937  1
2014 Foroozannejad MH, Hashemi M, Mahini A, Baas BM, Ghiasi S. Time-scalable mapping for circuit-switched GALS chip multiprocessor platforms Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 752-762. DOI: 10.1109/Tcad.2014.2299958  1
2013 Mohsenin T, Shirani-Mehr H, Baas BM. LDPC decoder with an adaptive wordwidth datapath for energy and BER co-optimization Vlsi Design. 2013. DOI: 10.1155/2013/913018  1
2013 Liu B, Baas BM. Parallel aes encryption engines for many-core processor arrays Ieee Transactions On Computers. 62: 536-547. DOI: 10.1109/Tc.2011.251  1
2013 Topaloglu RO, Baas B. Guest Editors' Introduction to Practical Parallel EDA Ieee Design & Test of Computers. 30: 6-7. DOI: 10.1109/Mdat.2012.2237138  0.32
2011 Xiao Z, Baas BM. A 1080p H.264/AVC baseline residual encoder for a fine-grained many-core system Ieee Transactions On Circuits and Systems For Video Technology. 21: 890-902. DOI: 10.1109/Tcsvt.2011.2133290  1
2011 Tran AT, Baas BM. RoShaQ: High-performance on-chip router with shared queues Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 232-238. DOI: 10.1109/ICCD.2011.6081402  1
2011 Liu B, Baas BM. A high-performance area-efficient AES cipher on a many-core platform Conference Record - Asilomar Conference On Signals, Systems and Computers. 2058-2062. DOI: 10.1109/ACSSC.2011.6190389  1
2010 Truong DN, Baas BM. Circuit modeling for practical many-core architecture design exploration Proceedings - Design Automation Conference. 627-628. DOI: 10.1145/1837274.1837432  1
2010 Yu Z, Baas BM. A low-area multi-link interconnect architecture for GALS chip multiprocessors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 750-762. DOI: 10.1109/Tvlsi.2009.2017912  1
2010 Mohsenin T, Truong DN, Baas BM. A low-complexity message-passing algorithm for reduced routing congestion in LDPC decoders Ieee Transactions On Circuits and Systems I: Regular Papers. 57: 1048-1061. DOI: 10.1109/Tcsi.2010.2046957  1
2010 Tran AT, Truong DN, Baas B. A reconfigurable source-synchronous on-chip network for GALS many-core platforms Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 897-910. DOI: 10.1109/Tcad.2010.2048594  1
2010 Tran AT, Baas BM. DLABS: A dual-lane buffer-sharing router architecture for networks on chip Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 327-332. DOI: 10.1109/SIPS.2010.5624812  1
2010 Tran AT, Baas BM. Design of an energy-efficient 32-bit adder operating at subthreshold voltages in 45-nm CMOS Icce 2010 - 3rd International Conference On Communications and Electronics. 87-91. DOI: 10.1109/ICCE.2010.5670687  1
2010 Truong DN, Baas BM. Massively parallel processor array for mid-/back-end ultrasound signal processing 2010 Ieee Biomedical Circuits and Systems Conference, Biocas 2010. 274-277. DOI: 10.1109/BIOCAS.2010.5709624  1
2010 Mohsenin T, Baas BM. A split-decoding message passing algorithm for low density parity check decoders Journal of Signal Processing Systems. 61: 329-345. DOI: 10.1007/s11265-010-0456-y  1
2009 Yu Z, Baas BM. High performance, energy efficiency, and scalability with GALS chip multiprocessors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 66-79. DOI: 10.1109/Tvlsi.2008.2001947  1
2009 Tran AT, Truong DN, Baas BM. A gals many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network Proceedings - 2009 3rd Acm/Ieee International Symposium On Networks-On-Chip, Nocs 2009. 214-223. DOI: 10.1109/NOCS.2009.5071470  1
2009 Truong DN, Cheng WH, Mohsenin T, Yu Z, Jacobson AT, Landge G, Meeuwsen MJ, Watnik C, Tran AT, Xiao Z, Work EW, Webb JW, Mejia PV, Baas BM. A 167-processor computational platform in 65 nm CMOS Ieee Journal of Solid-State Circuits. 44: 1130-1144. DOI: 10.1109/Jssc.2009.2013772  1
2009 Jacobson AT, Truong DN, Baas BM. The design of a reconfigurable continuous-flow mixed-radix FFT processor Proceedings - Ieee International Symposium On Circuits and Systems. 1133-1136. DOI: 10.1109/ISCAS.2009.5117960  1
2009 Tran AT, Truong DN, Baas BM. A low-cost high-speed source-synchronous interconnection technique for GALS chip multiprocessors Proceedings - Ieee International Symposium On Circuits and Systems. 996-999. DOI: 10.1109/ISCAS.2009.5117926  1
2008 Yu Z, Meeuwsen MJ, Apperson RW, Sattari O, Lai M, Webb JW, Work EW, Truong D, Mohsenin T, Baas BM. AsAP: An asynchronous array of simple processors Ieee Journal of Solid-State Circuits. 43: 695-705. DOI: 10.1109/Jssc.2007.916616  1
2008 Yu Z, Baas BM. A low-area interconnect architecture for chip multiprocessors Proceedings - Ieee International Symposium On Circuits and Systems. 2857-2860. DOI: 10.1109/ISCAS.2008.4542053  1
2008 Cheng WH, Baas BM. Dynamic voltage and frequency scaling circuits with two supply voltages Proceedings - Ieee International Symposium On Circuits and Systems. 1236-1239. DOI: 10.1109/ISCAS.2008.4541648  1
2008 Tran AT, Truong DN, Baas BM. A complete real-time 802.11a baseband receiver implemented on an array of programmable processors Conference Record - Asilomar Conference On Signals, Systems and Computers. 165-170. DOI: 10.1109/ACSSC.2008.5074384  1
2008 Yu Z, Meeuwsen MJ, Apperson RW, Sattari O, Lai MA, Webb JW, Work EW, Mohsenin T, Baas BM. Architecture and evaluation of an asynchronous array of simple processors Journal of Signal Processing Systems. 53: 243-259. DOI: 10.1007/s11265-008-0162-1  1
2007 Meeuwsen MJ, Yu Z, Baas BM. A shared memory module for asynchronous arrays of processors Eurasip Journal On Embedded Systems. 2007. DOI: 10.1155/2007/86273  1
2007 Apperson RW, Yu Z, Meeuwsen MJ, Mohsenin T, Baas BM. A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 1125-1134. DOI: 10.1109/Tvlsi.2007.903938  1
2007 Baas B, Yu Z, Meeuwsen M, Sattari O, Apperson R, Work E, Webb J, Lai M, Mohsenin T, Truong D, Cheung J. AsAP: A fine-grained many-core platform for DSP applications Ieee Micro. 27: 34-45. DOI: 10.1109/Mm.2007.29  1
2007 Mohsenin T, Baas BM. High-throughput LDPC decoders using a multiple split-row method Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 2. DOI: 10.1109/ICASSP.2007.366160  1
2006 Yu Z, Baas BM. Performance and power analysis of globally asynchronous locally synchronous multi-processor systems Proceedings - Ieee Computer Society Annual Symposium On Emerging Vlsi Technologies and Architectures 2006. 2006: 378-383. DOI: 10.1109/ISVLSI.2006.72  1
2006 Mohsenin T, Baas BM. Split-row: A reduced complexity, high throughput LDPC decoder architecture Ieee International Conference On Computer Design, Iccd 2006. 320-325. DOI: 10.1109/ICCD.2006.4380835  1
2005 Baas BM. A generalized cached-FFT algorithm Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. DOI: 10.1109/ICASSP.2005.1416247  1
2004 Meeuwsen MJ, Sattari O, Baas BM. A full-rate software implementation of an IEEE 802.11A compliant digital baseband transmitter Ieee Workshop On Signal Processing Systems, Sips: Design and Implementation. 124-129.  1
2003 Baas BM. A parallel programmable energy-efficient architecture for computationally-intensive DSP systems Conference Record of the Asilomar Conference On Signals, Systems and Computers. 2: 2185-2192.  1
1999 Baas BM. A Low-Power, High-Performance, 1024-Point FFT Processor Ieee Journal of Solid-State Circuits. 34: 380-387. DOI: 10.1109/4.748190  1
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