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Anand Raghunathan - Publications

Affiliations: 
Electrical and Computer Engineering Purdue University, West Lafayette, IN, United States 
Area:
Brain-inspired computing, Computing with post-CMOS devices, System-on-Chips, Embedded Systems, Electronic Design Automation
Website:
https://engineering.purdue.edu/ECE/Academics/Undergraduates/UGO/People/ptProfile?resource_id=46143
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129 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Ranjan A, Raha A, Raghunathan V, Raghunathan A. Approximate Memory Compression Ieee Transactions On Very Large Scale Integration Systems. 28: 980-991. DOI: 10.1109/Tvlsi.2020.2970041  0.372
2019 Jain S, Ankit A, Chakraborty I, Gokmen T, Rasch M, Haensch W, Roy K, Raghunathan A. Neural network accelerator design with resistive crossbars: Opportunities and challenges Ibm Journal of Research and Development. 63: 10:1-10:13. DOI: 10.1147/Jrd.2019.2947011  0.485
2019 Chen M, Ranjan A, Raghunathan A, Roy K. Cache Memory Design With Magnetic Skyrmions in a Long Nanotrack Ieee Transactions On Magnetics. 55: 1-9. DOI: 10.1109/Tmag.2019.2909188  0.412
2019 Venkataramani S, Kozhikkottu V, Sabne A, Roy K, Raghunathan A. Logic Synthesis of Approximate Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2019.2940680  0.774
2019 Sen S, Jain S, Venkataramani S, Raghunathan A. SparCE : Spar sity Aware General-Purpose C ore E xtensions to Accelerate Deep Neural Networks Ieee Transactions On Computers. 68: 912-925. DOI: 10.1109/Tc.2018.2879434  0.484
2018 Sarwar SS, Venkataramani S, Ankit A, Raghunathan A, Roy K. Energy-Efficient Neural Computing with Approximate Multipliers Acm Journal On Emerging Technologies in Computing Systems. 14: 16. DOI: 10.1145/3097264  0.434
2018 Jain S, Ranjan A, Roy K, Raghunathan A. Computing in Memory With Spin-Transfer Torque Magnetic RAM Ieee Transactions On Very Large Scale Integration Systems. 26: 470-483. DOI: 10.1109/Tvlsi.2017.2776954  0.442
2018 Behroozi S, Raghunathan V, Raghunathan A, Kim Y. A Quality-Configurable Approximate Serial Bus for Energy-Efficient Sensory Data Transfer Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 8: 379-390. DOI: 10.1109/Jetcas.2018.2856085  0.35
2018 Sarwar SS, Srinivasan G, Han B, Wijesinghe P, Jaiswal A, Panda P, Raghunathan A, Roy K. Energy Efficient Neural Computing: A Study of Cross-Layer Approximations Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 8: 796-809. DOI: 10.1109/Jetcas.2018.2835809  0.395
2017 Goud AA, Venkatesan R, Raghunathan A, Roy K. Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes Acm Journal On Emerging Technologies in Computing Systems. 13: 23. DOI: 10.1145/2967615  0.32
2017 Pajouhi Z, Fong X, Raghunathan A, Roy K. Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC Acm Journal On Emerging Technologies in Computing Systems. 13: 1-20. DOI: 10.1145/2934685  0.436
2017 Gala N, Venkataramani S, Raghunathan A, Kamakoti V. Approximate Error Detection With Stochastic Checkers Ieee Transactions On Very Large Scale Integration Systems. 25: 2258-2270. DOI: 10.1109/Tvlsi.2017.2684816  0.396
2017 Mosenia A, Sur-Kolay S, Raghunathan A, Jha NK. CABA: Continuous Authentication Based on BioAura Ieee Transactions On Computers. 66: 759-772. DOI: 10.1109/Tc.2016.2622262  0.343
2016 Raha A, Venkataramani S, Raghunathan V, Raghunathan A. Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2586379  0.458
2016 Kozhikkottu VJ, Venkatesan R, Raghunathan A, Dey S. Emulation-Based Analysis of System-on-Chip Performance Under Variations Ieee Transactions On Very Large Scale Integration Systems. 24: 3401-3414. DOI: 10.1109/Tvlsi.2016.2551243  0.786
2016 Liu J, Venkataramani S, Venkatakrishnan SV, Pan Y, Bouman CA, Raghunathan A. EMBIRA: An Accelerator for Model-Based Iterative Reconstruction Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2551204  0.49
2016 Akkala AG, Venkatesan R, Raghunathan A, Roy K. Asymmetric Underlapped Sub-10-nm n-FinFETs for High-Speed and Low-Leakage 6T SRAMs Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2015.2512227  0.331
2016 Fong X, Kim Y, Yogendra K, Fan D, Sengupta A, Raghunathan A, Roy K. Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1-22. DOI: 10.1109/Tcad.2015.2481793  0.331
2016 Venkatesan R, Kozhikkottu VJ, Sharad M, Augustine C, Raychowdhury A, Roy K, Raghunathan A. Cache Design with Domain Wall Memory Ieee Transactions On Computers. 65: 1010-1024. DOI: 10.1109/Tc.2015.2506581  0.793
2016 Roy K, Jung B, Peroulis D, Raghunathan A. Integrated Systems in the More-Than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components Ieee Design and Test. 33: 56-65. DOI: 10.1109/Mdt.2011.49  0.492
2015 Mozaffari-Kermani M, Sur-Kolay S, Raghunathan A, Jha NK. Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare. Ieee Journal of Biomedical and Health Informatics. 19: 1893-905. PMID 25095272 DOI: 10.1109/Jbhi.2014.2344095  0.509
2015 Mirtar A, Dey S, Raghunathan A. An application adaptation approach to mitigate the impact of dynamic thermal management on video encoding Acm Transactions On Design Automation of Electronic Systems. 20. DOI: 10.1145/2753758  0.385
2015 Kim Y, Lee WS, Raghunathan V, Jha NK, Raghunathan A. Vibration-based secure side channel for medical devices Proceedings - Design Automation Conference. 2015. DOI: 10.1145/2744769.2744928  0.413
2015 Venkatesan R, Sharad M, Roy K, Raghunathan A. Energy-efficient all-spin cache hierarchy using shift-based writes and multilevel storage Acm Journal On Emerging Technologies in Computing Systems. 12. DOI: 10.1145/2723165  0.456
2015 Fong X, Venkatesan R, Lee D, Raghunathan A, Roy K. Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2439733  0.405
2015 Mirtar A, Dey S, Raghunathan A. Joint work and voltage/frequency scaling for quality-optimized dynamic thermal management Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 1017-1030. DOI: 10.1109/Tvlsi.2014.2333741  0.409
2015 Fan D, Shim Y, Raghunathan A, Roy K. STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks Ieee Transactions On Nanotechnology. 14: 1013-1023. DOI: 10.1109/Tnano.2015.2437902  0.348
2015 Pajouhi Z, Venkataramani S, Yogendra K, Raghunathan A, Roy K. Exploring Spin-Transfer-Torque Devices for Logic Applications Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 1441-1454. DOI: 10.1109/Tcad.2015.2413852  0.405
2015 Kim Y, Lee W, Raghunathan A, Raghunathan V, Jha NK. Reliability and security of implantable and wearable medical devices Implantable Biomedical Microsystems: Design Principles and Applications. 167-199. DOI: 10.1016/B978-0-323-26208-8.00008-X  0.41
2014 Chippa VK, Mohapatra D, Roy K, Chakradhar ST, Raghunathan A. Scalable effort hardware design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 2004-2016. DOI: 10.1109/Tvlsi.2013.2276759  0.825
2014 Venkatesan R, Chippa VK, Augustine C, Roy K, Raghunathan A. Domain-Specific Many-core Computing using Spin-based Memory Ieee Transactions On Nanotechnology. 13: 881-894. DOI: 10.1109/Tnano.2014.2306958  0.801
2014 Fong X, Venkatesan R, Raghunathan A, Roy K. Non-Volatile Complementary Polarizer Spin-Transfer Torque On-Chip Caches: A Device/Circuit/Systems Perspective Ieee Transactions On Magnetics. 50. DOI: 10.1109/Tmag.2014.2326858  0.418
2014 Zhang M, Raghunathan A, Jha NK. A defense framework against malware and vulnerability exploits International Journal of Information Security. 13: 439-452. DOI: 10.1007/S10207-014-0233-1  0.458
2013 Zhang M, Raghunathan A, Jha NK. MedMon: securing medical devices through wireless monitoring and anomaly detection. Ieee Transactions On Biomedical Circuits and Systems. 7: 871-81. PMID 24473551 DOI: 10.1109/Tbcas.2013.2245664  0.531
2013 Chippa VK, Roy K, Chakradhar ST, Raghunathan A. Managing the quality vs. efficiency trade-off using dynamic effort scaling Transactions On Embedded Computing Systems. 12. DOI: 10.1145/2465787.2465792  0.809
2013 Gupta V, Mohapatra D, Raghunathan A, Roy K. Low-Power Digital Signal Processing Using Approximate Adders Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 124-137. DOI: 10.1109/Tcad.2012.2217962  0.438
2013 Li C, Raghunathan A, Jha NK. Improving the trustworthiness of medical device software with formal verification methods Ieee Embedded Systems Letters. 5: 50-53. DOI: 10.1109/Les.2013.2276434  0.522
2013 Chuah JW, Raghunathan A, Jha NK. ROBESim: A retrofit-oriented building energy simulator based on EnergyPlus Energy and Buildings. 66: 88-103. DOI: 10.1016/J.Enbuild.2013.07.020  0.772
2013 Venkataramani S, Roy K, Raghunathan A. Substitute-and-simplify: A unified design paradigm for approximate and quality configurable circuits Proceedings -Design, Automation and Test in Europe, Date. 1367-1372.  0.347
2012 Arora D, Aaraj N, Raghunathan A, Jha NK. INVISIOS: A Lightweight, Minimally Intrusive Secure Execution Environment Acm Transactions in Embedded Computing Systems. 11: 60. DOI: 10.1145/2345770.2345772  0.798
2012 Kozhikkottu V, Dey S, Raghunathan A. Recovery-based design for variation-tolerant SoCs Proceedings - Design Automation Conference. 826-833. DOI: 10.1145/2228360.2228510  0.34
2012 Li C, Jha NK, Raghunathan A. Secure reconfiguration of software-defined radio Transactions On Embedded Computing Systems. 11. DOI: 10.1145/2146417.2146427  0.593
2012 Griffin WP, Raghunathan A, Roy K. CLIP: Circuit level IC protection through direct injection of process variations Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 791-803. DOI: 10.1109/Tvlsi.2011.2135868  0.412
2012 Chandra S, Raghunathan A, Dey S. Variation-Aware Voltage Level Selection Ieee Transactions On Very Large Scale Integration Systems. 20: 925-936. DOI: 10.1109/Tvlsi.2011.2126050  0.32
2012 Li C, Raghunathan A, Jha NK. A trusted virtual machine in an untrusted management environment Ieee Transactions On Services Computing. 5: 472-483. DOI: 10.1109/Tsc.2011.30  0.595
2012 Pienaar JA, Chakradhar S, Raghunathan A. Automatic generation of software pipelines for heterogeneous parallel systems International Conference For High Performance Computing, Networking, Storage and Analysis, Sc. DOI: 10.1109/SC.2012.22  0.817
2011 Pienaar JA, Raghunathan A, Chakradhar S. MDR: Performance model driven runtime for heterogeneous parallel platforms Proceedings of the International Conference On Supercomputing. 225-234. DOI: 10.1145/1995896.1995933  0.81
2011 Aaraj N, Raghunathan A, Jha NK. A framework for defending embedded systems against software attacks Acm Transactions in Embedded Computing Systems. 10: 33. DOI: 10.1145/1952522.1952526  0.802
2010 Chakradhar ST, Raghunathan A. Best-effort computing: Re-thinking parallel software and hardware Proceedings - Design Automation Conference. 865-870. DOI: 10.1145/1837274.1837492  0.397
2010 Chandra S, Lahiri K, Raghunathan A, Dey S. Variation-aware system-level power analysis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1173-1184. DOI: 10.1109/Tvlsi.2009.2021478  0.369
2010 Meng J, Raghunathan A, Chakradhar S, Byna S. Exploiting the forgiving nature of applications for scalable parallel execution Proceedings of the 2010 Ieee International Symposium On Parallel and Distributed Processing, Ipdps 2010. DOI: 10.1109/IPDPS.2010.5470469  0.412
2009 Chandra S, Lahiri K, Raghunathan A, Dey S. Variation-Tolerant Dynamic Power Management at the System-Level Ieee Transactions On Very Large Scale Integration Systems. 17: 1220-1232. DOI: 10.1109/Tvlsi.2009.2019803  0.362
2009 Sundaram N, Raghunathan A, Chakradhar ST. A framework for efficient and scalable execution of domain-specific templates on GPUs Ipdps 2009 - Proceedings of the 2009 Ieee International Parallel and Distributed Processing Symposium. DOI: 10.1109/IPDPS.2009.5161039  0.398
2008 Aaraj N, Raghunathan A, Jha NK. Analysis and design of a hardware/software trusted platform module for embedded systems Transactions On Embedded Computing Systems. 8. DOI: 10.1145/1457246.1457254  0.821
2008 Sekar K, Lahiri K, Raghunathan A, Dey S. Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication Ieee Transactions On Very Large Scale Integration Systems. 16: 1413-1426. DOI: 10.1109/Tvlsi.2008.2000727  0.455
2008 Thoguluva J, Raghunathan A, Chakradhar ST. Efficient software architecture for IPSec acceleration using a programmable security processor Proceedings -Design, Automation and Test in Europe, Date. 1148-1153. DOI: 10.1109/DATE.2008.4484833  0.456
2008 Aaraj N, Raghunathan A, Jha NK. Dynamic binary instrumentation-based framework for malware defense Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5137: 64-87. DOI: 10.1007/978-3-540-70542-0_4  0.338
2007 Fei Y, Ravi S, Raghunathan A, Jha NK. Energy-optimizing source code transformations for operating system-driven embedded software Acm Transactions in Embedded Computing Systems. 7: 2. DOI: 10.1145/1324969.1324971  0.6
2007 Huang C, Ravi S, Raghunathan A, Jha NK. Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 1191-1204. DOI: 10.1109/Tvlsi.2007.904096  0.471
2007 Arora D, Raghunathan A, Ravi S, Sankaradass M, Jha NK, Chakradhar ST. Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC Ieee Transactions On Very Large Scale Integration Systems. 15: 699-710. DOI: 10.1109/Tvlsi.2007.898740  0.511
2007 Arora D, Ravi S, Raghunathan A, Jha NK. Architectural Support for Run-Time Validation of Program Data Properties Ieee Transactions On Very Large Scale Integration Systems. 15: 546-559. DOI: 10.1109/Tvlsi.2007.896913  0.469
2007 Potlapally NR, Ravi S, Raghunathan A, Lee RB, Jha NK. Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution Ieee Transactions On Very Large Scale Integration Systems. 15: 605-609. DOI: 10.1109/Tvlsi.2007.896912  0.69
2007 Potlapally NR, Raghunathan A, Ravi S, Jha NK, Lee RB. Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis Ieee Transactions On Very Large Scale Integration Systems. 15: 465-470. DOI: 10.1109/Tvlsi.2007.893665  0.612
2007 Aaraj N, Ravi S, Raghunathan A, Jha NK. Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems Ieee Transactions On Very Large Scale Integration Systems. 15: 296-308. DOI: 10.1109/Tvlsi.2007.893608  0.803
2007 Sun F, Ravi S, Raghunathan A, Jha NK. A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 2035-2045. DOI: 10.1109/Tcad.2007.906457  0.671
2007 Muttreja A, Raghunathan A, Ravi S, Jha NK. Hybrid simulation for energy estimation of embedded software Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1843-1854. DOI: 10.1109/Tcad.2007.895760  0.605
2007 Schaumont P, Raghunathan A. Guest editors' introduction: Security and trust in embedded-systems design Ieee Design and Test of Computers. 24: 518-520. DOI: 10.1109/Mdt.2007.188  0.453
2007 Sun F, Ravi S, Raghunathan A, Jha NK. A framework for extensible processor based MPSoC design Designing Embedded Processors: a Low Power Perspective. 65-95. DOI: 10.1007/978-1-4020-5869-1_4  0.439
2006 Sun F, Ravi S, Raghunathan A, Jha NK. Hybrid custom instruction and co-processor synthesis methodology for extensible processors Proceedings of the Ieee International Conference On Vlsi Design. 2006: 473-476. DOI: 10.1109/VLSID.2006.100  0.405
2006 Psarakis M, Gizopoulos D, Hatzimihail M, Paschalis A, Raghunathan A, Ravi S. Systematic software-based self-test for pipelined processors Proceedings - Design Automation Conference. 393-398. DOI: 10.1109/Tvlsi.2008.2000866  0.42
2006 Arora D, Ravi S, Raghunathan A, Jha NK. Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors Ieee Transactions On Very Large Scale Integration Systems. 14: 1295-1308. DOI: 10.1109/Tvlsi.2006.887799  0.606
2006 Sun F, Ravi S, Raghunathan A, Jha NK. A Scalable Synthesis Methodology for Application-Specific Processors Ieee Transactions On Very Large Scale Integration Systems. 14: 1175-1188. DOI: 10.1109/Tvlsi.2006.886410  0.685
2006 Lahiri K, Raghunathan A, Lakshminarayana G. The LOTTERYBUS on-chip communication architecture Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 596-608. DOI: 10.1109/Tvlsi.2006.878210  0.447
2006 Potlapally NR, Ravi S, Raghunathan A, Jha NK. A study of the energy consumption characteristics of cryptographic algorithms and security protocols Ieee Transactions On Mobile Computing. 5: 128-143. DOI: 10.1109/Tmc.2006.16  0.636
2006 Huang C, Ravi S, Raghunathan A, Jha N. Use of Computation-Unit Integrated Memories in High-Level Synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1969-1989. DOI: 10.1109/Tcad.2005.862749  0.446
2006 Lingappan L, Ravi S, Raghunathan A, Jha NK, Chakradhar ST. Test-volume reduction in systems-on-a-chip using heterogeneous and multilevel compression techniques Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2193-2205. DOI: 10.1109/Tcad.2005.862735  0.803
2006 Zhong L, Ravi S, Raghunathan A, Jha NK. RTL-aware cycle-accurate functional power estimation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2103-2116. DOI: 10.1109/Tcad.2005.859504  0.57
2006 Sun F, Ravi S, Raghunathan A, Jha NK. Application-specific heterogeneous multiprocessor synthesis using extensible processors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1589-1602. DOI: 10.1109/Tcad.2005.858269  0.674
2006 Sekar K, Lahiri K, Raghunathan A, Dey S. Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms Proceedings -Design, Automation and Test in Europe, Date. 1.  0.416
2006 Stanley-Marbell P, Lahiri K, Raghunathan A. Adaptive data placement in an embedded multiprocessor thread library Proceedings -Design, Automation and Test in Europe, Date. 1.  0.407
2005 Tan TK, Raghunathan A, Jha NK. Energy macromodeling of embedded operating systems Acm Transactions in Embedded Computing Systems. 4: 231-254. DOI: 10.1145/1053271.1053281  0.426
2005 Wang W, Raghunathan A, Lakshminarayana G, Jha NK. Input space-adaptive optimization for embedded-software synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1677-1692. DOI: 10.1109/Tcad.2005.852282  0.564
2005 Huang C, Ravi S, Raghunathan A, Jha NK. Generation of distributed logic-memory architectures through high-level synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1694-1711. DOI: 10.1109/Tcad.2005.852276  0.488
2005 Sun F, Ravi S, Raghunathan A, Jha NK. Synthesis of application-specific heterogeneous multiprocessor architectures using extensible processors Proceedings of the Ieee International Conference On Vlsi Design. 551-556. DOI: 10.1109/ICVD.2005.155  0.304
2005 Lahiri K, Dey S, Raghunathan A. Design of Communication Architectures for High-Performance and Energy-Efficient Systems-on-Chips Multiprocessor Systems-On-Chips. 187-222. DOI: 10.1016/B978-012385251-9/50021-9  0.304
2005 Muttreja A, Raghunathan A, Ravi S, Jha NK. Hybrid simulation for embedded software energy estimation Proceedings - Design Automation Conference. 23-26.  0.311
2005 Gupta P, Ravi S, Raghunathan A, Jha NK. Efficient fingerprint-based user authentication for embedded systems Proceedings - Design Automation Conference. 244-247.  0.344
2004 Ravi S, Raghunathan A, Kocher P, Hattangady S. Security in embedded systems Acm Transactions On Embedded Computing Systems. 3: 461-491. DOI: 10.1145/1015047.1015049  0.636
2004 Wang W, Raghunathan A, Lakshminarayana G, Jha NK. Input space adaptive design: a high-level methodology for optimizing energy and performance Ieee Transactions On Very Large Scale Integration Systems. 12: 590-602. DOI: 10.1109/Tvlsi.2004.827592  0.549
2004 Muttreja A, Raghunathan A, Ravi S, Jha NK. Automated energy/performance macromodeling of embedded software Proceedings - Design Automation Conference. 99-102. DOI: 10.1109/Tcad.2006.883914  0.49
2004 Wang W, Raghunathan A, Jha NK, Dey S. Resource budgeting for Multiprocess High-level synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1010-1019. DOI: 10.1109/Tcad.2004.829806  0.583
2004 Lahiri K, Raghunathan A, Dey S. Efficient power profiling for battery-driven embedded system design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 919-932. DOI: 10.1109/Tcad.2004.828137  0.387
2004 Lahiri K, Raghunathan A, Dey S. Design space exploration for optimizing on-chip communication architectures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 952-961. DOI: 10.1109/Tcad.2004.828127  0.384
2004 Lahiri K, Raghunathan A, Lakshminarayana G, Dey S. Design of high-performance system-on-chips using communication architecture tuners Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 620-636. DOI: 10.1109/Tcad.2004.826585  0.364
2004 Fei Y, Ravi S, Raghunathan A, Jha NK. A hybrid energy-estimation technique for extensible processors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 652-664. DOI: 10.1109/Tcad.2004.826546  0.649
2004 Sun F, Ravi S, Raghunathan A, Jha NK. Custom-instruction synthesis for extensible-processor platforms Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 216-228. DOI: 10.1109/Tcad.2003.822133  0.635
2004 Lakshminarayana G, Raghunathan A, Khouri KS, Jha NK, Dey S. Common-Case Computation: A High-Level Energy and Performance Optimization Technique Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 33-49. DOI: 10.1109/Tcad.2003.819893  0.789
2004 Wang W, Raghunathan A, Jha NK. Profiling driven computation reuse: An embedded software synthesis technique for energy and performance optimization Proceedings of the Ieee International Conference On Vlsi Design. 17: 267-272.  0.327
2003 Raghunathan A, Dey S, Jha NK. High-Level Macro-Modeling and Estimation Techniques for Switching Activity and Power Consumption Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 538-557. DOI: 10.1109/Tvlsi.2003.812295  0.349
2003 Tan TK, Raghunathan A, Jha NK. A simulation framework for energy-consumption analysis of OS-driven embedded applications Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1284-1294. DOI: 10.1109/Tcad.2003.816207  0.725
2003 Dick RP, Lakshminarayana G, Raghunathan A, Jha NK. Analysis of power dissipation in embedded systems using real-time operating systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 615-627. DOI: 10.1109/Tcad.2003.810745  0.424
2003 Raghunathan A, Ravi S, Hattangady S, Quisquater JJ. Securing mobile appliances: New challenges for the system designer Proceedings -Design, Automation and Test in Europe, Date. 176-181. DOI: 10.1109/DATE.2003.1253605  0.354
2003 Potlapally NR, Ravi S, Raghunathan A, Jha NK. Analyzing the Energy Consumption of Security Protocols Proceedings of the International Symposium On Low Power Electronics and Design. 30-35.  0.341
2002 Sun F, Ravi S, Raghunathan A, Jha NK. Synthesis of custom processors based on extensible platforms Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 641-648. DOI: 10.1145/774572.774667  0.352
2002 Lajolo M, Raghunathan A, Dey S, Lavagno L. Cosimulation-based power estimation for system-on-chip design Ieee Transactions On Very Large Scale Integration Systems. 10: 253-266. DOI: 10.1109/Tvlsi.2002.1043328  0.384
2002 Tan TK, Raghunathan A, Lakshminarayana G, Jha NK. High-level energy macromodeling of embedded software Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 1037-1050. DOI: 10.1109/Tcad.2002.801094  0.726
2002 Lahiri K, Raghunathan A, Dey S. Communication-based power management Ieee Design and Test of Computers. 19: 118-130. DOI: 10.1109/Mdt.2002.1018140  0.347
2002 Raghunathan V, Raghunathan A, Srivastava MB, Ercegovac MD. High-level synthesis with SIMD units Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference On Vlsi Design, Asp-Dac/Vlsi Design 2002. 407-413. DOI: 10.1109/ASPDAC.2002.994955  0.316
2002 Lahiri K, Raghunathan A, Dey S. Fast system-level power profiling for battery-efficient system design Hardware/Software Codesign - Proceedings of the International Workshop. 157-162.  0.339
2002 Lahiri K, Raghunathan A, Dey S. Battery-efficient architecture for an 802.11 MAC processor Ieee International Conference On Communications. 2: 669-674.  0.33
2002 Chang J, Ravi S, Raghunathan A. FLEXBAR: A crossbar switching fabric with improved performance and utilization Proceedings of the Custom Integrated Circuits Conference. 405-408.  0.336
2002 Lahiri K, Raghunathan A, Dey S. Communication architecture based power management for battery efficient system design Proceedings - Design Automation Conference. 691-696.  0.317
2002 Tan TK, Raghunathan A, Jha NK. EMSIM: An energy simulation framework for an embedded operating system Proceedings - Ieee International Symposium On Circuits and Systems. 2.  0.342
2002 Ravi S, Raghunathan A, Potlapally N, Sankaradass M. System design methodologies for a wireless security processing platform Proceedings - Design Automation Conference. 777-782.  0.466
2002 Ravi S, Raghunathan A, Potlapally N. Securing wireless data: System architecture challenges Proceedings of the International Symposium On System Synthesis. 195-200.  0.351
2001 Lahiri K, Raghunathan A, Dey S. System-level performance analysis for designing on-chip communication architectures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 768-783. DOI: 10.1109/43.924830  0.38
2001 Panigrahi D, Raghunathan A, Lakshminarayana G, Dey S. Energy modeling for wireless internet access Proceedings - 2001 International Conference On Third Generation Wireless and Beyond. 332-337.  0.313
2001 Wang W, Raghunathan A, Lakshminarayana G, Jha NK. Input space adaptive design: A high-level methodology for energy and performance optimization Proceedings - Design Automation Conference. 738-743.  0.317
2001 Tan TK, Raghunathan A, Lakshminarayana G, Jha NK. High-level software energy macro-modeling Proceedings - Design Automation Conference. 605-610.  0.324
2000 Lakshminarayana G, Raghunathan A, Jha NK. Incorporating speculative execution into scheduling of control-flow-intensive designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 308-324. DOI: 10.1109/43.833200  0.435
2000 Lakshminarayana G, Raghunathan A, Jha NK. Behavioral synthesis of fault secure controller/datapaths based on aliasing probability analysis Ieee Transactions On Computers. 49: 865-885. DOI: 10.1109/12.869319  0.408
1999 Lakshminarayana G, Raghunathan A, Jha NK, Dey S. Power management in high-level synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 7: 7-15. DOI: 10.1109/92.748195  0.352
1999 Dey S, Raghunathan A, Jha NK, Wakabayashi K. Controller-based power management for control-flow intensive designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1496-1508. DOI: 10.1109/43.790626  0.311
1999 Raghunathan A, Dey S, Jha NK. Register transfer level power optimization with emphasis on glitch analysis and reduction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1114-1131. DOI: 10.1109/43.775632  0.362
1998 Ghosh I, Raghunathan A, Jha NK. A design-for-testability technique for register-transfer level circuits using control/data flow extraction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 706-723. DOI: 10.1109/43.712102  0.382
1998 Dey S, Raghunathan A, Wagner KD. Design for Testability Techniques at the Behavioraland Register-Transfer Levels Journal of Electronic Testing. 13: 79-91. DOI: 10.1023/A:1008397519162  0.403
1997 Raghunathan A, Jha NK. SCALP: An iterative-improvement-based low-power data path synthesis system Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 1260-1277. DOI: 10.1109/43.663817  0.407
1997 Ghosh I, Raghunathan A, Jha NK. Design for hierarchical testability of RTL circuits obtained by behavioral synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 1001-1014. DOI: 10.1109/43.658568  0.404
1995 Raghunathan A, Malik S, Ashar P. Test Generation for Cyclic Combinational Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 1408-1414. DOI: 10.1109/43.469666  0.342
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