| Year |
Citation |
Score |
| 2020 |
Dolabella S, Frison R, Chahine GA, Richter C, Schulli TU, Tasdemir Z, Alaca BE, Leblebici Y, Dommann A, Neels A. Real- and -space travelling: multi-dimensional distribution maps of crystal-lattice strain (∊) and tilt of suspended monolithic silicon nanowire structures. Journal of Applied Crystallography. 53: 58-68. PMID 32047404 DOI: 10.1107/S1600576719015504 |
0.329 |
|
| 2020 |
Kim G, Kossel M, Cevrero A, Ozkaya I, Burg A, Toifl T, Leblebici Y, Kull L, Luu D, Braendli M, Menolfi C, Francese P, Yueksel H, Aprile C, Morf T. A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET Ieee Journal of Solid-State Circuits. 55: 38-48. DOI: 10.1109/Jssc.2019.2938414 |
0.357 |
|
| 2019 |
Shahrabi E, LaGrange T, Demirci T, Leblebici Y. Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization Microelectronic Engineering. 214: 74-80. DOI: 10.1016/J.Mee.2019.04.018 |
0.417 |
|
| 2018 |
Boybat I, Le Gallo M, Nandakumar SR, Moraitis T, Parnell T, Tuma T, Rajendran B, Leblebici Y, Sebastian A, Eleftheriou E. Neuromorphic computing with multi-memristive synapses. Nature Communications. 9: 2514. PMID 29955057 DOI: 10.1038/S41467-018-04933-Y |
0.323 |
|
| 2018 |
Tasdemir Z, Peric O, Sacchetto D, Fantner GE, Leblebici Y, Alaca BE. Monolithic Fabrication of Silicon Nanowires Bridging Thick Silicon Structures Ieee Transactions On Nanotechnology. 17: 1299-1302. DOI: 10.1109/Tnano.2018.2868712 |
0.33 |
|
| 2018 |
Aprile C, Ture K, Baldassarre L, Shoaran M, Yilmaz G, Maloberti F, Dehollain C, Leblebici Y, Cevher V. Adaptive Learning-Based Compressive Sampling for Low-power Wireless Implants Ieee Transactions On Circuits and Systems I-Regular Papers. 65: 3929-3941. DOI: 10.1109/Tcsi.2018.2853983 |
0.373 |
|
| 2018 |
Aprile C, Cevrero A, Francese PA, Menolfi C, Braendli M, Kossel M, Morf T, Kull L, Oezkaya I, Leblebici Y, Cevher V, Toifl T. An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels Ieee Journal of Solid-State Circuits. 53: 861-872. DOI: 10.1109/Jssc.2017.2783679 |
0.331 |
|
| 2018 |
Ozkaya I, Cevrero A, Francese PA, Menolfi C, Morf T, Brandli M, Kuchta DM, Kull L, Baks CW, Proesel JE, Kossel M, Luu D, Lee BG, Doany FE, Meghelli M, ... Leblebici Y, et al. A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET Ieee Journal of Solid-State Circuits. 53: 1227-1237. DOI: 10.1109/Jssc.2017.2778286 |
0.392 |
|
| 2018 |
Fumarola A, Sidler S, Moon K, Jang J, Shelby RM, Narayanan P, Leblebici Y, Hwang H, Burr GW. Bidirectional Non-Filamentary RRAM as an Analog Neuromorphic Synapse, Part II: Impact of Al/Mo/Pr 0.7 Ca 0.3 MnO 3 Device Characteristics on Neural Network Training Accuracy Ieee Journal of the Electron Devices Society. 6: 169-178. DOI: 10.1109/Jeds.2017.2782184 |
0.308 |
|
| 2018 |
Nasr Esfahani M, Kilinc Y, Çagatay Karakan M, Orhan E, Hanay MS, Leblebici Y, Erdem Alaca B. Piezoresistive silicon nanowire resonators as embedded building blocks in thick SOI Journal of Micromechanics and Microengineering. 28: 045006. DOI: 10.1088/1361-6439/Aaab2F |
0.384 |
|
| 2018 |
Kilic M, Mavrogordatos TG, Leblebici Y. A hybrid CDAC-threshold configuring SAR ADC in 28nm FDSOI CMOS Analog Integrated Circuits and Signal Processing. 97: 397-404. DOI: 10.1007/S10470-018-1222-5 |
0.432 |
|
| 2017 |
Yılmaz M, Wollschläger N, Esfahani MN, Österle W, Leblebici Y, Alaca BE. Superplastic behavior of silica nanowires obtained by direct patterning of silsesquioxane-based precursors. Nanotechnology. 28: 115302. PMID 28205512 DOI: 10.1088/1361-6528/Aa5B80 |
0.321 |
|
| 2017 |
Yilmaz M, Kilinc Y, Nadar G, Tasdemir Z, Wollschläger N, Österle W, Leblebici Y, Alaca BE. Top-down technique for scaling to nano in silicon MEMS Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena. 35: 22001. DOI: 10.1116/1.4978047 |
0.363 |
|
| 2017 |
Wozniak S, Pantazi A, Sidler S, Papandreou N, Leblebici Y, Eleftheriou E. Neuromorphic Architecture With 1M Memristive Synapses for Detection of Weakly Correlated Inputs Ieee Transactions On Circuits and Systems Ii-Express Briefs. 64: 1342-1346. DOI: 10.1109/Tcsii.2017.2697457 |
0.31 |
|
| 2017 |
Kim G, Barailler T, Cao C, Gharibdoust K, Leblebici Y. Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme Ieee Transactions On Circuits and Systems I-Regular Papers. 64: 3192-3201. DOI: 10.1109/Tcsi.2017.2737642 |
0.33 |
|
| 2017 |
Ozkaya I, Cevrero A, Francese PA, Menolfi C, Morf T, Brandli M, Kuchta DM, Kull L, Baks CW, Proesel JE, Kossel M, Luu D, Lee BG, Doany FE, Meghelli M, ... Leblebici Y, et al. A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET Ieee Journal of Solid-State Circuits. 52: 3458-3473. DOI: 10.1109/Jssc.2017.2734913 |
0.35 |
|
| 2017 |
Esfahani MN, Leblebici Y, Alaca BE. A Monolithic Approach to Downscaling Silicon Piezoresistive Sensors Ieee\/Asme Journal of Microelectromechanical Systems. 26: 624-631. DOI: 10.1109/Jmems.2017.2679219 |
0.396 |
|
| 2017 |
Baltacı C, Leblebici Y. Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies Integration. 58: 421-429. DOI: 10.1016/J.Vlsi.2017.03.001 |
0.384 |
|
| 2017 |
Esfahani MN, Yilmaz M, Wollschläger N, Rangelow IW, Leblebici Y, Alaca BE. Monolithic technology for silicon nanowires in high-topography architectures Microelectronic Engineering. 2017: 42-47. DOI: 10.1016/J.Mee.2017.10.001 |
0.378 |
|
| 2016 |
Cogal O, Leblebici Y. An Insect Eye Inspired Miniaturized Multi-Camera System for Endoscopic Imaging. Ieee Transactions On Biomedical Circuits and Systems. PMID 27249836 DOI: 10.1109/Tbcas.2016.2547388 |
0.305 |
|
| 2016 |
Tasdemir Z, Wollschläger N, Österle W, Leblebici Y, Alaca BE. A deep etching mechanism for trench-bridging silicon nanowires. Nanotechnology. 27: 095303. PMID 26854570 DOI: 10.1088/0957-4484/27/9/095303 |
0.368 |
|
| 2016 |
Wollschläger N, Tasdemir Z, Häusler I, Leblebici Y, Österle W, Alaca BE. Determination of the Elastic Behavior of Silicon Nanowires within a Scanning Electron Microscope Journal of Nanomaterials. 2016. DOI: 10.1155/2016/4905838 |
0.353 |
|
| 2016 |
Kull L, Pliva J, Toifl T, Schmatz M, Francese PA, Menolfi C, Brandli M, Kossel M, Morf T, Andersen TM, Leblebici Y. Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS Ieee Journal of Solid-State Circuits. DOI: 10.1109/Jssc.2016.2519397 |
0.385 |
|
| 2016 |
Gharibdoust K, Tajalli A, Leblebici Y. A 4 × 9 Gb/s 1 pJ/b Hybrid NRZ/Multi-Tone I/O with Crosstalk and ISI Reduction for Dense Interconnects Ieee Journal of Solid-State Circuits. 51: 992-1002. DOI: 10.1109/Jssc.2015.2504410 |
0.39 |
|
| 2016 |
Sandrini J, Barlas M, Thammasack M, Demirci T, De Marchi M, Sacchetto D, Gaillardon PE, De Micheli G, Leblebici Y. Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology Ieee Journal On Emerging and Selected Topics in Circuits and Systems. DOI: 10.1109/Jetcas.2016.2547746 |
0.431 |
|
| 2016 |
Lulec SZ, Adiyan U, Yaralioglu GG, Leblebici Y, Urey H. MEMS cantilever sensor array oscillators: Theory and experiments Sensors and Actuators, a: Physical. 237: 147-154. DOI: 10.1016/J.Sna.2015.11.028 |
0.327 |
|
| 2016 |
Beanato G, Cevrero A, De Micheli G, Leblebici Y. Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors Microelectronics Journal. 51: 38-45. DOI: 10.1016/J.Mejo.2015.12.004 |
0.319 |
|
| 2016 |
Beanato G, Gharibdoust K, Cevrero A, De Micheli G, Leblebici Y. Design and analysis of jitter-aware low-power and high-speed TSV link for 3D ICs Microelectronics Journal. 48: 50-59. DOI: 10.1016/J.Mejo.2015.12.003 |
0.396 |
|
| 2015 |
Seyid K, Popovic V, Cogal O, Akin A, Afshari H, Schmid A, Leblebici Y. A real-time multiaperture omnidirectional visual sensor based on an interconnected network of smart cameras Ieee Transactions On Circuits and Systems For Video Technology. 25: 314-324. DOI: 10.1109/Tcsvt.2014.2355713 |
0.357 |
|
| 2015 |
Shoaran M, Tajalli A, Alioto M, Schmid A, Leblebici Y. Analysis and characterization of variability in subthreshold source-coupled logic circuits Ieee Transactions On Circuits and Systems I: Regular Papers. 62: 458-467. DOI: 10.1109/Tcsi.2014.2364101 |
0.434 |
|
| 2015 |
Ozsema HG, Kostak D, Demirci T, Leblebici Y. Full swing 20 GHz frequency divider with 1 v supply voltage in FD-SOI 28 nm technology 2015 Nordic Circuits and Systems Conference, Norcas 2015: Norchip and International Symposium On System-On-Chip, Soc 2015. DOI: 10.1109/NORCHIP.2015.7364385 |
0.309 |
|
| 2015 |
Gharibdoust K, Tajalli A, Leblebici Y. Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces Ieee Journal of Solid-State Circuits. 50: 3133-3144. DOI: 10.1109/Jssc.2015.2483904 |
0.364 |
|
| 2015 |
Katic N, Popovic V, Cojbasic R, Schmid A, Leblebici Y. A relative imaging CMOS image sensor for high dynamic range and high frame-rate machine vision imaging applications Ieee Sensors Journal. 15: 4121-4129. DOI: 10.1109/Jsen.2015.2413896 |
0.395 |
|
| 2015 |
Sandrini J, Demirci T, Thammasack M, Sacchetto D, Leblebici Y. Low-voltage read/write circuit design for transistorless ReRAM crossbar arrays in 180nm CMOS technology Proceedings - Ieee International Symposium On Circuits and Systems. 2015: 9-12. DOI: 10.1109/ISCAS.2015.7168557 |
0.327 |
|
| 2015 |
Katic N, Cojbasic R, Schmid A, Leblebici Y. A sub-mW pulse-based 5-bit flash ADC with a time-domain fully-digital reference ladder Microelectronics Journal. DOI: 10.1016/J.Mejo.2015.09.017 |
0.445 |
|
| 2015 |
Katic N, Schmid A, Leblebici Y. A comparative experimental investigation on responsivity and response speed of photo-diode and photo-BJT structures integrated in a low-cost standard CMOS process Microelectronics Journal. 46: 997-1001. DOI: 10.1016/J.Mejo.2015.08.004 |
0.367 |
|
| 2015 |
Nyffeler C, Hanay MS, Sacchetto D, Leblebici Y. Graphene field effect devices operating in differential circuit configuration Microelectronic Engineering. 145: 149-152. DOI: 10.1016/J.Mee.2015.03.012 |
0.358 |
|
| 2015 |
Sandrini J, Thammasack M, Demirci T, Gaillardon PE, Sacchetto D, De Micheli G, Leblebici Y. Heterogeneous integration of ReRAM crossbars in 180 nm CMOS BEoL process Microelectronic Engineering. 145: 62-65. DOI: 10.1016/J.Mee.2015.03.011 |
0.409 |
|
| 2015 |
Katic N, Kazi I, Tajalli A, Schmid A, Leblebici Y. A subthreshold current-sensing ΣΔ modulator for low-voltage and low-power sensor interfaces International Journal of Circuit Theory and Applications. 43: 1597-1614. DOI: 10.1002/Cta.2026 |
0.318 |
|
| 2015 |
Katic N, Kamal MH, Schmid A, Vandergheynst P, Leblebici Y. Compressive image acquisition in modern CMOS IC design International Journal of Circuit Theory and Applications. 43: 722-741. DOI: 10.1002/Cta.1969 |
0.345 |
|
| 2014 |
Krasnozhon D, Lembke D, Nyffeler C, Leblebici Y, Kis A. MoS2 transistors operating at gigahertz frequencies. Nano Letters. 14: 5905-11. PMID 25243885 DOI: 10.1021/Nl5028638 |
0.403 |
|
| 2014 |
Puppo F, Dave A, Doucey MA, Sacchetto D, Baj-Rossi C, Leblebici Y, De Micheli G, Carrara S. Memristive biosensors under varying humidity conditions. Ieee Transactions On Nanobioscience. 13: 19-30. PMID 24594511 DOI: 10.1109/Tnb.2013.2295517 |
0.387 |
|
| 2014 |
Cogal O, Akin A, Seyid K, Popovic V, Schmid A, Ott B, Wellig P, Leblebici Y. A new omni-directional multi-camera system for high resolution surveillance Proceedings of Spie - the International Society For Optical Engineering. 9120. DOI: 10.1117/12.2049698 |
0.316 |
|
| 2014 |
De Marchi M, Sacchetto D, Zhang J, Frache S, Gaillardon PE, Leblebici Y, De Micheli G. Top-down fabrication of gate-all-around vertically stacked silicon nanowire fets with controllable polarity Ieee Transactions On Nanotechnology. 13: 1029-1038. DOI: 10.1109/Tnano.2014.2363386 |
0.418 |
|
| 2014 |
Zhang J, De Marchi M, Sacchetto D, Gaillardon PE, Leblebici Y, De Micheli G. Polarity-controllable silicon nanowire transistors with dual threshold voltages Ieee Transactions On Electron Devices. 61: 3654-3660. DOI: 10.1109/Ted.2014.2359112 |
0.446 |
|
| 2014 |
Popovic V, Pignat E, Leblebici Y. Performance optimization and FPGA implementation of real-time tone mapping Ieee Transactions On Circuits and Systems Ii: Express Briefs. 61: 803-807. DOI: 10.1109/Tcsii.2014.2345306 |
0.342 |
|
| 2014 |
Kazi I, Meinerzhagen P, Gaillardon PE, Sacchetto D, Leblebici Y, Burg A, De Micheli G. Energy/reliability trade-offs in low-voltage ReRAM-based non-volatile flip-flop design Ieee Transactions On Circuits and Systems I: Regular Papers. 61: 3155-3164. DOI: 10.1109/Tcsi.2014.2334891 |
0.362 |
|
| 2014 |
Marchi MD, Zhang J, Frache S, Sacchetto D, Gaillardon PE, Leblebici Y, Micheli GD. Configurable logic gates using polarity-controlled silicon nanowire gate-all-around FETs Ieee Electron Device Letters. 35: 880-882. DOI: 10.1109/Led.2014.2329919 |
0.435 |
|
| 2014 |
Beanato G, Cevrero A, De Michel G, Leblebici Y. 3D serial TSV link for low-power chip-to-chip communication Icicdt 2014 - Ieee International Conference On Integrated Circuit Design and Technology. DOI: 10.1109/ICICDT.2014.6838583 |
0.31 |
|
| 2014 |
Akin A, Baz I, Schmid A, Leblebici Y. Dynamically adaptive real-time disparity estimation hardware using iterative refinement Integration, the Vlsi Journal. 47: 365-376. DOI: 10.1016/J.Vlsi.2013.11.002 |
0.305 |
|
| 2014 |
Erarslan RB, Adiyan U, Lulec SZ, Olcer S, Temiz Y, Leblebici Y, Torun H, Urey H. Design and characterization of micromachined sensor array integrated with CMOS based optical readout Sensors and Actuators, a: Physical. 215: 44-50. DOI: 10.1016/J.Sna.2013.10.014 |
0.374 |
|
| 2013 |
Kheradmand-Boroujeni B, Piguet C, Leblebici Y. A scalable and adaptive technique for compensating process variations and controlling leakage and delay in the FPGA Journal of Low Power Electronics. 9: 1-8. DOI: 10.1166/Jolpe.2013.1235 |
0.424 |
|
| 2013 |
Katic N, Kamal MH, Kilic M, Schmid A, Vandergheynst P, Leblebici Y. High frame-rate low-power compressive sampling CMOS image sensor architecture [extended abstract] Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 313-314. DOI: 10.1145/2483028.2483118 |
0.305 |
|
| 2013 |
Hosseini Kamal M, Afshari H, Leblebici Y, Schmid A, Vandergheynst P. Interconnected network of cameras Proceedings of Spie - the International Society For Optical Engineering. 8659. DOI: 10.1117/12.2004736 |
0.314 |
|
| 2013 |
Temiz Y, Guiducci C, Leblebici Y. Post-CMOS processing and 3-D integration based on dry-film lithography Ieee Transactions On Components, Packaging and Manufacturing Technology. 3: 1458-1466. DOI: 10.1109/Tcpmt.2012.2228004 |
0.383 |
|
| 2013 |
Sacchetto D, Gaillardon PE, Zervas M, Carrara S, De Micheli G, Leblebici Y. Applications of multi-terminal memristive devices: A review Ieee Circuits and Systems Magazine. 13: 23-41. DOI: 10.1109/Mcas.2013.2256258 |
0.4 |
|
| 2013 |
Kull L, Toifl T, Schmatz M, Francese PA, Menolfi C, Brändli M, Kossel M, Morf T, Andersen TM, Leblebici Y. A 3.1 mW 8b 1.2 GS/s single-Channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS Ieee Journal of Solid-State Circuits. 48: 3049-3058. DOI: 10.1109/JSSC.2013.2279571 |
0.306 |
|
| 2013 |
Köklü G, Ghaye J, Etienne-Cummings R, Leblebici Y, De Micheli G, Carrara S. Empowering Low-Cost CMOS Cameras by Image Processing to Reach Comparable Results with Costly CCDs Bionanoscience. 3: 403-414. DOI: 10.1007/S12668-013-0106-5 |
0.338 |
|
| 2013 |
Gaillardon PE, Amarù LG, Bobba S, De Marchi M, Sacchetto D, Leblebici Y, De Micheli G. Vertically-stacked double-gate nanowire FETs with controllable polarity: From devices to regular ASICs Proceedings -Design, Automation and Test in Europe, Date. 625-630. |
0.308 |
|
| 2013 |
Kull L, Toifl T, Schmatz M, Francese PA, Menolfi C, Braendli M, Kossel M, Morf T, Andersen T, Leblebici Y. A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. |
0.307 |
|
| 2012 |
Akgun OC, Rodrigues JN, Leblebici Y, Öwall V. High-level energy estimation in the sub-VT domain: simulation and measurement of a cardiac event detector. Ieee Transactions On Biomedical Circuits and Systems. 6: 15-27. PMID 23852741 DOI: 10.1109/Tbcas.2011.2157505 |
0.332 |
|
| 2012 |
Temiz Y, Ferretti A, Leblebici Y, Guiducci C. A comparative study on fabrication techniques for on-chip microelectrodes. Lab On a Chip. 12: 4920-8. PMID 23042440 DOI: 10.1039/C2Lc40582B |
0.331 |
|
| 2012 |
Sadeghian RB, Leblebici Y, Shakouri A. Simulation and design of a silicon nanowire based phase change memory cell Materials Research Society Symposium Proceedings. 1431: 20-25. DOI: 10.1557/Opl.2012.1135 |
0.391 |
|
| 2012 |
Leblebici Y. Nanometer-scale system design challenges: Bridging the gap from devices to architectures 2012 13th International Conference On Ultimate Integration On Silicon, Ulis 2012. 181-182. DOI: 10.1109/ULIS.2012.6193387 |
0.313 |
|
| 2012 |
Garetto D, Randriamihaja YM, Rideau D, Zaka A, Schmid A, Leblebici Y, Jaouen H. Modeling stressed MOS oxides using a multiphonon-assisted quantum approach-Part I: Impedance analysis Ieee Transactions On Electron Devices. 59: 610-620. DOI: 10.1109/Ted.2011.2181388 |
0.305 |
|
| 2012 |
Tajalli A, Leblebici Y. Wide-range dynamic power management in low-voltage low-power subthreshold SCL Ieee Transactions On Circuits and Systems Ii: Express Briefs. 59: 903-907. DOI: 10.1109/Tcsii.2012.2231032 |
0.37 |
|
| 2012 |
Afshari H, Popovic V, Tasci T, Schmid A, Leblebici Y. A spherical multi-camera system with real-time omnidirectional video acquisition capability Ieee Transactions On Consumer Electronics. 58: 1110-1118. DOI: 10.1109/Tce.2012.6414975 |
0.373 |
|
| 2012 |
Sacchetto D, Leblebici Y, De Micheli G. Ambipolar gate-controllable SiNW FETs for configurable logic circuits with improved expressive capability Ieee Electron Device Letters. 33: 143-145. DOI: 10.1109/Led.2011.2174410 |
0.421 |
|
| 2012 |
Beanato G, Giovannini P, Cevrero A, Athanasopoulos P, Zervas M, Temiz Y, Leblebici Y. Design and testing strategies for modular 3-D-multiprocessor systems using die-level through silicon via technology Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 2: 295-306. DOI: 10.1109/Jetcas.2012.2193837 |
0.395 |
|
| 2012 |
Carrara S, Sacchetto D, Doucey MA, Baj-Rossi C, De Micheli G, Leblebici Y. Memristive-biosensors: A new detection method by using nanofabricated memristors Sensors and Actuators, B: Chemical. 171: 449-457. DOI: 10.1016/J.Snb.2012.04.089 |
0.354 |
|
| 2012 |
Sacchetto D, Xie S, Savu V, Zervas M, De Micheli G, Brugger J, Leblebici Y. Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-μm gates patterned by nanostencil lithography Microelectronic Engineering. 98: 355-358. DOI: 10.1016/J.Mee.2012.07.048 |
0.411 |
|
| 2012 |
Arian A, Saberi M, Hosseini-Khayat S, Lotfi R, Leblebici Y. A 10-bit 50-MS/s redundant SAR ADC with split capacitive-array DAC Analog Integrated Circuits and Signal Processing. 71: 583-589. DOI: 10.1007/S10470-011-9812-5 |
0.419 |
|
| 2012 |
Tajalli A, Leblebici Y. Power and area efficient MOSFET-C filter for very low frequency applications Analog Integrated Circuits and Signal Processing. 70: 123-132. DOI: 10.1007/S10470-011-9640-7 |
0.367 |
|
| 2012 |
Bobba S, Gaillardon PE, Zhang J, De Marchi M, Sacchetto D, Leblebici Y, De Micheli G. Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors Proceedings of the 2012 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2012. 55-60. |
0.328 |
|
| 2011 |
Majidzadeh V, Schmid A, Leblebici Y. Energy efficient low-noise neural recording amplifier with enhanced noise efficiency factor. Ieee Transactions On Biomedical Circuits and Systems. 5: 262-71. PMID 23851477 DOI: 10.1109/Tbcas.2010.2078815 |
0.391 |
|
| 2011 |
Joye N, Schmid A, Leblebici Y. Amplitude modulation based readout for very dense active microelectrode arrays Ieice Electronics Express. 8: 38-44. DOI: 10.1587/Elex.8.38 |
0.388 |
|
| 2011 |
Ben-Jamaa MH, Gaillardon PE, Clermidy F, O'Connor I, Sacchetto D, De Micheli G, Leblebici Y. Silicon nanowire arrays and crossbars: Top-down fabrication techniques and circuit applications Science of Advanced Materials. 3: 466-476. DOI: 10.1166/Sam.2011.1172 |
0.427 |
|
| 2011 |
Kheradmand-Boroujeni B, Piguet C, Leblebici Y. Optimal logic architecture and supply voltage selection method to reduce the impact of the threshold voltage variation on the timing Journal of Low Power Electronics. 7: 285-293. DOI: 10.1166/Jolpe.2011.1137 |
0.398 |
|
| 2011 |
Temiz Y, Zervas M, Guiducci C, Leblebici Y. Die-level TSV fabrication platform for CMOS-MEMS integration 2011 16th International Solid-State Sensors, Actuators and Microsystems Conference, Transducers'11. 1799-1802. DOI: 10.1109/TRANSDUCERS.2011.5969555 |
0.308 |
|
| 2011 |
Jamaa MHB, Cerofolini G, De Micheli G, Leblebici Y. Polysilicon nanowire transistors and arrays fabricated with the multispacer technique Ieee Transactions On Nanotechnology. 10: 891-899. DOI: 10.1109/Tnano.2010.2089532 |
0.377 |
|
| 2011 |
Tajalli A, Leblebici Y. Low-power and widely tunable linearized biquadratic low-pass transconductor-C filter Ieee Transactions On Circuits and Systems Ii: Express Briefs. 58: 159-163. DOI: 10.1109/Tcsii.2011.2111530 |
0.316 |
|
| 2011 |
Tajalli A, Leblebici Y. Design trade-offs in ultra-low-power digital nanoscale CMOS Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 2189-2200. DOI: 10.1109/Tcsi.2011.2112595 |
0.46 |
|
| 2011 |
Sacchetto D, De Marchi M, De Micheli G, Leblebici Y. Alternative design methodologies for the next generation logic switch Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 231-234. DOI: 10.1109/ICCAD.2011.6105331 |
0.308 |
|
| 2011 |
Arkan EF, Sacchetto D, Yildiz I, Leblebici Y, Alaca BE. Monolithic integration of Si nanowires with metallic electrodes: NEMS resonator and switch applications Journal of Micromechanics and Microengineering. 21. DOI: 10.1088/0960-1317/21/12/125018 |
0.415 |
|
| 2011 |
Temiz Y, Kilchenmann S, Leblebici Y, Guiducci C. 3D integration technology for lab-on-a-chip applications Electronics Letters. 47. DOI: 10.1049/El.2011.2683 |
0.351 |
|
| 2011 |
Zervas M, Sacchetto D, De Micheli G, Leblebici Y. Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget Microelectronic Engineering. 88: 3127-3132. DOI: 10.1016/J.Mee.2011.06.013 |
0.384 |
|
| 2011 |
Sacchetto D, Savu V, De Micheli G, Brugger J, Leblebici Y. Ambipolar silicon nanowire FETs with stenciled-deposited metal gate Microelectronic Engineering. 88: 2732-2735. DOI: 10.1016/J.Mee.2010.12.117 |
0.384 |
|
| 2011 |
Sacchetto D, Doucey MA, de Micheli G, Leblebici Y, Carrara S. New Insight on Bio-sensing by Nano-fabricated Memristors Bionanoscience. 1: 1-3. DOI: 10.1007/S12668-011-0002-9 |
0.317 |
|
| 2011 |
Majidzadeh V, Silay KM, Schmid A, Dehollain C, Leblebici Y. A fully on-chip LDO voltage regulator with 37 dB PSRR at 1 MHz for remotely powered biomedical implants Analog Integrated Circuits and Signal Processing. 67: 157-168. DOI: 10.1007/S10470-010-9556-7 |
0.382 |
|
| 2010 |
Tajalli A, Leblebici Y. Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits Journal of Low Power Electronics. 6: 211-217. DOI: 10.1166/Jolpe.2010.1072 |
0.423 |
|
| 2010 |
Sacchetto D, Ben-Jamaa MH, De Micheli G, Leblebici Y. Design aspects of carry lookahead adders with vertically-stacked nanowire transistors Iscas 2010 - 2010 Ieee International Symposium On Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 1715-1718. DOI: 10.1109/ISCAS.2010.5537526 |
0.311 |
|
| 2010 |
Stanisavljevic M, Schmid A, Leblebici Y. Selective redundancy-based design techniques for the minimization of local delay variations Iscas 2010 - 2010 Ieee International Symposium On Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2486-2489. DOI: 10.1109/ISCAS.2010.5537130 |
0.318 |
|
| 2010 |
Karakoyunlu D, Gurkaynak FK, Sunar B, Leblebici Y. Efficient and side-channel-aware implementations of elliptic curve cryptosystems over prime fields Iet Information Security. 4: 30-43. DOI: 10.1049/Iet-Ifs.2009.0038 |
0.307 |
|
| 2010 |
Alioto M, Badel S, Leblebici Y. Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff Microelectronics Journal. 41: 669-679. DOI: 10.1016/J.Mejo.2010.06.005 |
0.362 |
|
| 2009 |
Cevrero A, Athanasopoulos P, Parandeh-Afshar H, Verma AK, Niaki HSA, Nicopoulos C, Gurkaynak FK, Brisk P, Leblebici Y, Ienne P. Field programmable compressor trees: Acceleration of multi-input addition on FPGAs Acm Transactions On Reconfigurable Technology and Systems. 2. DOI: 10.1145/1534916.1534923 |
0.37 |
|
| 2009 |
Stanisavljevic M, Schmid A, Leblebici Y. Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies Ieee Transactions On Nanotechnology. 8: 379-390. DOI: 10.1109/Tnano.2008.2009761 |
0.358 |
|
| 2009 |
Tajalli A, Leblebici Y. Leakage Current Reduction Using Subthreshold Source-Coupled Logic Ieee Transactions On Circuits and Systems Ii-Express Briefs. 56: 374-378. DOI: 10.1109/Tcsil.2009.2019167 |
0.414 |
|
| 2009 |
Tajalli A, Alioto M, Leblebici Y. Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits Ieee Transactions On Circuits and Systems Ii-Express Briefs. 56: 127-131. DOI: 10.1109/Tcsii.2008.2011603 |
0.38 |
|
| 2009 |
Tajalli A, Leblebici Y. A Slew Controlled LVDS Output Driver Circuit in 0.18 $\mu$ m CMOS Technology Ieee Journal of Solid-State Circuits. 44: 538-548. DOI: 10.1109/Jssc.2008.2010788 |
0.422 |
|
| 2009 |
Ozsun O, Alaca BE, Leblebici Y, Yalcinkaya AD, Yildiz I, Yilmaz M, Zervas M. Monolithic integration of silicon nanowires with a microgripper Journal of Microelectromechanical Systems. 18: 1335-1344. DOI: 10.1109/Jmems.2009.2034340 |
0.366 |
|
| 2009 |
Tajalli A, Brauer EJ, Leblebici Y. Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5fJ/stage PDP Microelectronics Journal. 40: 973-978. DOI: 10.1016/J.Mejo.2009.01.005 |
0.393 |
|
| 2008 |
Jamaa MHB, Moselund KE, Atienza D, Bouvet D, Ionescu AM, Leblebici Y, Micheli GD. Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 2053-2067. DOI: 10.1109/Tcad.2008.2006076 |
0.343 |
|
| 2008 |
Tajalli A, Brauer EJ, Leblebici Y, Vittoz E. Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications Ieee Journal of Solid-State Circuits. 43: 1699-1710. DOI: 10.1109/Jssc.2008.922709 |
0.463 |
|
| 2008 |
Tajalli A, Leblebici Y, Brauer EJ. Implementing Ultra-high-Value Floating Tunable CMOS Resistors Electronics Letters. 44: 349-350. DOI: 10.1049/El:20082538 |
0.412 |
|
| 2008 |
Badel S, Schmid A, Leblebici Y. CMOS realization of two-dimensional mixed analog-digital Hamming distance discriminator circuits for real-time imaging applications Microelectronics Journal. 39: 1817-1828. DOI: 10.1016/J.Mejo.2008.02.004 |
0.396 |
|
| 2008 |
Moselund KE, Bouvet D, Jamaa MHB, Atienza D, Leblebici Y, Micheli GD, Ionescu AM. Prospects for logic-on-a-wire Microelectronic Engineering. 85: 1406-1409. DOI: 10.1016/J.Mee.2008.01.022 |
0.417 |
|
| 2007 |
Tajalli A, Muller P, Leblebici Y. Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits Journal of Low Power Electronics. 3: 345-354. DOI: 10.1166/Jolpe.2007.145 |
0.444 |
|
| 2007 |
Deniz ZT, Leblebici Y, Vittoz EA. On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation Ieee Journal of Solid-State Circuits. 42: 1593-1606. DOI: 10.1109/Jssc.2007.896694 |
0.334 |
|
| 2007 |
Tajalli A, Vittoz E, Leblebici Y, Brauer E. Ultra-low power subthreshold current-mode logic utilising PMOS load device Electronics Letters. 43: 911-913. DOI: 10.1049/El:20071208 |
0.416 |
|
| 2006 |
Coskun AK, Rosing TS, Mihic K, Micheli GD, Leblebici Y. Analysis and Optimization of MPSoC Reliability Journal of Low Power Electronics. 2: 56-69. DOI: 10.1166/Jolpe.2006.007 |
0.348 |
|
| 2004 |
Ünlü MS, Emsley MK, Dosunmu OI, Muller P, Leblebici Y. High-speed Si resonant cavity enhanced photodetectors and arrays Journal of Vacuum Science and Technology a: Vacuum, Surfaces and Films. 22: 781-787. DOI: 10.1116/1.1647591 |
0.367 |
|
| 2004 |
Schmid A, Leblebici Y. Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors Ieee Transactions On Very Large Scale Integration Systems. 12: 1156-1166. DOI: 10.1109/Tvlsi.2004.836292 |
0.408 |
|
| 2000 |
Hatirnaz I, Gürkaynak FK, Leblebici Y. A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic Vlsi Design. 11: 115-128. DOI: 10.1155/2000/98945 |
0.377 |
|
| 1998 |
Schmid A, Leblebici Y, Mlynek D. Compact charge-based 4 bit flash ADC circuit architecture for ANN applications Electronics Letters. 34: 784-786. DOI: 10.1049/El:19980592 |
0.383 |
|
| 1996 |
Leblebici Y, Ozdemir H, Kepkep A, Cilingiroglu U. A compact high-speed (31,5) parallel counter circuit based on capacitive threshold-logic gates Ieee Journal of Solid-State Circuits. 31: 1177-1183. DOI: 10.1109/4.508266 |
0.44 |
|
| 1996 |
Ozdemir H, Kepkep A, Pamir B, Leblebici Y, Cilingiroglu U. A capacitive threshold-logic gate Ieee Journal of Solid-State Circuits. 31: 1141-1150. DOI: 10.1109/4.508261 |
0.395 |
|
| 1996 |
Leblebici Y. Design considerations for CMOS digital circuits with improved hot-carrier reliability Ieee Journal of Solid-State Circuits. 31: 1014-1024. DOI: 10.1109/4.508215 |
0.432 |
|
| 1995 |
Leblebici Y, Unlu MS, Kang S, Onat BM. Transient simulation of heterojunction photodiodes-part I: computational methods Journal of Lightwave Technology. 13: 396-405. DOI: 10.1109/50.376717 |
0.646 |
|
| 1995 |
Unlu MS, Onat BM, Leblebici Y. Transient simulation of heterojunction photodiodes-part II: analysis of resonant cavity enhanced photodetectors Journal of Lightwave Technology. 13: 406-415. DOI: 10.1109/50.372435 |
0.341 |
|
| 1994 |
Leblebici Y, Kang SM. Simulation of hot-carrier induced MOS circuit degradation for VLSI reliability analysis Ieee Transactions On Reliability. 43: 197-206. DOI: 10.1109/24.294990 |
0.368 |
|
| 1993 |
Shih Y-, Leblebici Y, Kang S-. ILLIADS: a fast timing and reliability simulator for digital MOS circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 1387-1402. DOI: 10.1109/43.240086 |
0.39 |
|
| 1993 |
Leblebici Y, Kang S-. Modeling and simulation of hot-carrier-induced device degradation in MOS circuits Ieee Journal of Solid-State Circuits. 28: 585-595. DOI: 10.1109/4.229396 |
0.384 |
|
| 1993 |
Leblebici Y, Sun W, Kang SM. Parametric macro-modeling of hot-carrier-induced dynamic degradation in MOS VLSI circuits Ieee Transactions On Electron Devices. 40: 673-676. DOI: 10.1109/16.199342 |
0.429 |
|
| 1992 |
Unlu M, Leblebici Y, Kang S, Morkoc H. Transient simulation of resonant cavity enhanced heterojunction photodiodes Ieee Photonics Technology Letters. 4: 1366-1369. DOI: 10.1109/68.180578 |
0.378 |
|
| 1992 |
Leblebici Y, Kang S-. Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 11: 235-246. DOI: 10.1109/43.124402 |
0.352 |
|
| 1991 |
Diaz CH, Kang S-, Leblebici Y. An accurate analytical delay model for BiCMOS driver circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 10: 577-588. DOI: 10.1109/43.79495 |
0.394 |
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