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John P. Hayes - Publications

Affiliations: 
University of Michigan, Ann Arbor, Ann Arbor, MI 
Website:
http://web.eecs.umich.edu/~jhayes/
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67 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Chen T, Hayes JP. Equivalence Among Stochastic Logic Circuits and its Application to Synthesis Ieee Transactions On Emerging Topics in Computing. 7: 67-79. DOI: 10.1109/Tetc.2016.2623796  0.334
2019 Ting P, Hayes JP. Removing constant-induced errors in stochastic circuits Iet Computers and Digital Techniques. 13: 187-197. DOI: 10.1049/Iet-Cdt.2018.5017  0.409
2018 Alaghi A, Qian W, Hayes JP. The Promise and Challenge of Stochastic Computing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1515-1531. DOI: 10.1109/Tcad.2017.2778107  0.323
2018 Alaghi A, Hayes JP. Computing with Randomness Ieee Spectrum. 55: 46-51. DOI: 10.1109/Mspec.2018.8302387  0.301
2018 Neugebauer F, Polian I, Hayes JP. S-box-based random number generation for stochastic computing Microprocessors and Microsystems. 61: 316-326. DOI: 10.1016/J.Micpro.2018.06.009  0.374
2017 Alaghi A, Chan WJ, Hayes JP, Kahng AB, Li J. Trading Accuracy for Energy in Stochastic Circuit Design Acm Journal On Emerging Technologies in Computing Systems. 13: 1-30. DOI: 10.1145/2990503  0.385
2015 Alaghi A, Hayes JP. STRAUSS: Spectral Transform Use in Stochastic Circuit Synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 1770-1783. DOI: 10.1109/Tcad.2015.2432138  0.391
2014 Chen T, Alaghi A, Hayes JP. Behavior of stochastic circuits under severe error conditions Information Technology. 56: 182-191. DOI: 10.1515/Itit-2013-1042  0.376
2013 Alaghi A, Hayes JP. Survey of Stochastic Computing Acm Transactions in Embedded Computing Systems. 12: 92. DOI: 10.1145/2465787.2465794  0.381
2012 Yi J, Hayes JP. Robust Coupling Delay Test Sets Journal of Electronic Testing. 28: 375-388. DOI: 10.1007/S10836-012-5292-5  0.426
2011 Polian I, Hayes JP, Reddy SM, Becker B. Modeling and Mitigating Transient Errors in Logic Circuits Ieee Transactions On Dependable and Secure Computing. 8: 537-547. DOI: 10.1109/Tdsc.2010.26  0.509
2011 Polian I, Hayes JP. Selective Hardening: Toward Cost-Effective Error Tolerance Ieee Design & Test of Computers. 28: 54-63. DOI: 10.1109/Mdt.2010.120  0.354
2009 Krishnaswamy S, Plaza SM, Markov IL, Hayes JP. Signature-based SER analysis and design of logic circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 74-86. DOI: 10.1109/Tcad.2008.2009139  0.429
2008 Krishnaswamy S, Viamontes GF, Markov IL, Hayes JP. Probabilistic transfer matrices in symbolic reliability analysis of logic circuits Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1297666.1297674  0.411
2007 Krishnaswamy S, Markov IL, Hayes JP. Tracking uncertainty with probabilistic logic circuit testing Ieee Design and Test of Computers. 24: 312-321. DOI: 10.1109/Mdt.2007.146  0.455
2006 Prasad AK, Shende VV, Markov IL, Hayes JP, Patel KN. Data structures and algorithms for simplifying reversible circuits Acm Journal On Emerging Technologies in Computing Systems. 2: 277-293. DOI: 10.1145/1216396.1216399  0.402
2006 Gao F, Hayes JP. Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2564-2571. DOI: 10.1109/Tcad.2006.875711  0.364
2006 Yi J, Hayes JP. High-level delay test generation for modular circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 576-590. DOI: 10.1109/Tcad.2005.853697  0.525
2005 Kandasamy N, Hayes JP, Murray BT. Time-constrained failure diagnosis in distributed embedded systems: Application to actuator diagnosis Ieee Transactions On Parallel and Distributed Systems. 16: 258-270. DOI: 10.1109/Tpds.2005.37  0.351
2005 Yi J, Hayes JP. The coupling model for function and delay faults Journal of Electronic Testing. 21: 631-649. DOI: 10.1007/S10836-005-3476-Y  0.477
2004 Viamontes GF, Markov IL, Hayes JP. Graph-based simulation of quantum computation in the density matrix representation Proceedings of Spie - the International Society For Optical Engineering. 5436: 285-296. DOI: 10.1117/12.542767  0.326
2003 Blanton RD(, Hayes JP. On the properties of the input pattern fault model Acm Transactions On Design Automation of Electronic Systems. 8: 108-124. DOI: 10.1145/606603.606609  0.74
2003 Patel KN, Hayes JP, Markov IL. Fault testing for reversible circuits Proceedings of the Ieee Vlsi Test Symposium. 2003: 410-416. DOI: 10.1109/Tcad.2004.831576  0.466
2003 Shende VV, Prasad AK, Markov IL, Hayes JP. Synthesis of reversible logic circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 710-722. DOI: 10.1109/Tcad.2003.811448  0.38
2003 Kandasamy N, Hayes JP, Murray BT. Transparent recovery from intermittent faults in time-triggered distributed systems Ieee Transactions On Computers. 52: 113-125. DOI: 10.1109/Tc.2003.1176980  0.352
2003 Kandasamy N, Hayes JP, Murray BT. Dependable communication synthesis for distributed embedded systems Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2788: 275-288. DOI: 10.1016/J.Ress.2004.08.008  0.35
2002 Chowdhary A, Hayes JP. General technology mapping for field-programmable gate arrays based on lookup tables Acm Transactions On Design Automation of Electronic Systems. 7: 1-32. DOI: 10.1145/504914.504915  0.368
2001 Yalcin H, Mortazavi M, Palermo R, Bamji C, Sakallah KA, Hayes JP. Fast and accurate timing characterization using functional information Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 315-331. DOI: 10.1109/43.908474  0.382
2000 Gupta A, Hayes JP. CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells Acm Transactions On Design Automation of Electronic Systems. 5: 510-547. DOI: 10.1145/348019.348234  0.334
2000 Van Campenhout D, Mudge T, Hayes JP. Collection and analysis of microprocessor design errors Ieee Design and Test of Computers. 17: 51-60. DOI: 10.1109/54.895006  0.53
2000 Al-Asaad H, Hayes JP. Logic Design Validation via Simulation and Automatic Test Pattern Generation Journal of Electronic Testing. 16: 575-589. DOI: 10.1023/A:1008302118244  0.48
1998 Campenhout DV, Al-Asaad H, Hayes JP, Mudge T, Brown RB. High-level design verification of microprocessors via error modeling Acm Transactions On Design Automation of Electronic Systems (Todaes). 3: 581-599. DOI: 10.1145/296333.296347  0.584
1998 Chakrabarty K, Hayes J. Zero-aliasing space compaction of test responses using multiple parity signatures Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 309-313. DOI: 10.1109/92.678893  0.617
1998 Chakrabarty K, Murray B, Hayes J. Optimal zero-aliasing space compaction of test responses Ieee Transactions On Computers. 47: 1171-1187. DOI: 10.1109/12.736427  0.559
1998 Al-Asaad H, Hayes JP, Murray BT. Scalable Test Generators for High-Speed Datapath Circuits Journal of Electronic Testing. 12: 111-125. DOI: 10.1023/A:1008242108853  0.505
1997 Yalcin H, Hayes JP. Event propagation conditions in circuit delay computation Acm Transactions On Design Automation of Electronic Systems. 2: 249-280. DOI: 10.1145/264995.264998  0.385
1997 Chakrabarty K, Hayes J. On the quality of accumulator-based compaction of test responses Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 916-922. DOI: 10.1109/43.644618  0.625
1997 Ku H, Hayes JP. Systematic design of fault-tolerant multiprocessors with shared buses Ieee Transactions On Computers. 46: 439-455. DOI: 10.1109/12.588058  0.494
1997 Blanton RD(, Hayes JP. Testability Properties of Divergent Trees Journal of Electronic Testing. 11: 197-209. DOI: 10.1023/A:1008262321471  0.727
1997 Dutt S, Hayes JP. A Local-Sparing Design Methodology for Fault-Tolerant Multiprocessors Computers and Mathematics With Applications. 34: 25-50. DOI: 10.1016/S0898-1221(97)00217-4  0.382
1996 Chakrabarty K, Hayes J. Test response compaction using multiplexed parity trees Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 1399-1408. DOI: 10.1109/43.543772  0.635
1996 Murray BT, Hayes JP. Testing ICs: getting to the core of the problem Ieee Computer. 29: 32-38. DOI: 10.1109/2.544235  0.342
1996 Blanton RD, Hayes JP. Testability of convergent tree circuits Ieee Transactions On Computers. 45: 950-963. DOI: 10.1109/12.536237  0.481
1996 Chakrabarty K, Hayes JP. Balance testing and balance-testable design of logic circuits Journal of Electronic Testing. 8: 71-86. DOI: 10.1007/Bf00136077  0.641
1996 Harary F, Hayes JP. Node fault tolerance in graphs Networks. 27: 19-23. DOI: 10.1002/Net.3230230207  0.301
1996 Ku HK, Hayes JP. Optimally edge fault-tolerant trees Networks. 27: 203-214. DOI: 10.1002/(Sici)1097-0037(199605)27:3<203::Aid-Net5>3.0.Co;2-M  0.37
1995 Chakrabarty K, Hayes J. Cumulative balance testing of logic circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 3: 72-83. DOI: 10.1109/92.365455  0.64
1992 Lee TC, Hayes JP. A fault-tolerant communication scheme for hypercube computers Ieee Transactions On Computers. 41: 1242-1256. DOI: 10.1109/12.166602  0.405
1992 Dutt S, Hayes JP. Some Practical Issues in the Design of Fault-Tolerant Multiprocessors Ieee Transactions On Computers. 41: 588-598. DOI: 10.1109/12.142685  0.432
1992 Lee TC, Hayes JP. Design of gracefully degradable hypercube-connected systems Journal of Parallel and Distributed Computing. 14: 390-401. DOI: 10.1016/0743-7315(92)90077-Z  0.42
1991 Dutt S, Hayes JP. Designing fault-tolerant systems using automorphisms Journal of Parallel and Distributed Computing. 12: 249-268. DOI: 10.1016/0743-7315(91)90129-W  0.47
1990 Bhattacharya D, Hayes JP. Designing for High-Level Test Generation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 9: 752-766. DOI: 10.1109/43.55212  0.45
1990 Maziasz RL, Hayes JP. Layout optimization of static CMOS functional cells Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 9: 708-719. DOI: 10.1109/43.55210  0.301
1990 Murray BT, Hayes JP. Hierarchical test generation using precomputed tests for modules Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 9: 594-603. DOI: 10.1109/43.55189  0.441
1990 Dutt S, Hayes JP. On Designing and Reconfiguring K-Fault-Tolerant Tree Architectures Ieee Transactions On Computers. 39: 490-503. DOI: 10.1109/12.54842  0.37
1990 Bhattacharya D, Hayes JP. A hierarchical test generation methodology for digital circuits Journal of Electronic Testing. 1: 103-123. DOI: 10.1007/Bf00137388  0.527
1989 Bhattacharya D, Murray BT, Hayes JP. High-level test generation for VLSI Ieee Computer. 22: 16-24. DOI: 10.1109/2.25379  0.461
1987 Hayes JP. An Introduction to Switch-Level Modeling Ieee Design & Test of Computers. 4: 18-25. DOI: 10.1109/Mdt.1987.295145  0.344
1986 Hayes JP. Digital Simulation with Multiple Logic Values Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 5: 274-283. DOI: 10.1109/Tcad.1986.1270196  0.333
1986 Hayes JP, Mudge T, Stout QF, Colley S, Palmer J. A Microprocessor-based Hypercube Supercomputer Ieee Micro. 6: 6-17. DOI: 10.1109/Mm.1986.304707  0.511
1986 Mudge TN, Hayes JP, Buzzard GD, Winsor DC. Analysis of multiple-bus interconnection networks Journal of Parallel and Distributed Computing. 3: 328-343. DOI: 10.1016/0743-7315(86)90019-5  0.512
1985 You Y, Hayes JP. A Self-Testing Dynamic RAM Chip Ieee Transactions On Electron Devices. 32: 508-515. DOI: 10.1109/T-Ed.1985.21971  0.396
1985 You Y, Hayes JP. A Self-Testing Dynamic RAM Chip Ieee Journal of Solid-State Circuits. 20: 428-435. DOI: 10.1109/Jssc.1985.1052325  0.417
1984 Hayes JP. Fault Modeling for Digital MOS Integrated Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 3: 200-208. DOI: 10.1109/Tcad.1984.1270076  0.495
1975 Hayes JP. Detection oF Pattern-Sensitive Faults in Random-Access Memories Ieee Transactions On Computers. 24: 150-157. DOI: 10.1109/T-C.1975.224182  0.342
1974 Hayes JP, Friedman AD. Test Point Placement to Simplify Fault Detection Ieee Transactions On Computers. 23: 727-735. DOI: 10.1109/T-C.1974.224021  0.434
1974 Hayes JP. On Modifying Logic Networks to Improve Their Diagnosability Ieee Transactions On Computers. 23: 56-62. DOI: 10.1109/T-C.1974.223777  0.348
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