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Xin Zhao - Publications

Affiliations: 
2012 Georgia Institute of Technology, Atlanta, GA 
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7 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2023 Luo G, Xiong G, Huang X, Zhao X, Tong Y, Chen Q, Zhu Z, Lei H, Lin J. Geometry Sampling-Based Adaption to DCGAN for 3D Face Generation. Sensors (Basel, Switzerland). 23. PMID 36850534 DOI: 10.3390/s23041937  0.342
2015 Kim DH, Athikulwongse K, Healy MB, Hossain MM, Jung M, Khorosh I, Kumar G, Lee YJ, Lewis DL, Lin TW, Liu C, Panth S, Pathak M, Ren M, Shen G, ... ... Zhao X, et al. Design and analysis of 3D-MAPS (3D Massively parallel processor with stacked memory) Ieee Transactions On Computers. 64: 112-125. DOI: 10.1109/Tc.2013.192  0.369
2014 Zhao X, Scheuermann MR, Lim SK. Analysis and modeling of dc current crowding for tsv-based 3-d connections and power integrity Ieee Transactions On Components, Packaging and Manufacturing Technology. 4: 123-133. DOI: 10.1109/Tcpmt.2013.2276779  0.37
2013 Chae K, Zhao X, Lim SK, Mukhopadhyay S. Tier Adaptive Body Biasing: A Post-Silicon Tuning Method to Minimize Clock Skew Variations in 3-D ICs Ieee Transactions On Components, Packaging and Manufacturing Technology. 3: 1720-1730. DOI: 10.1109/Tcpmt.2013.2238581  0.377
2012 Zhao X, Tolbert JR, Mukhopadhyay S, Lim SK. Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1222-1234. DOI: 10.1109/Tcad.2012.2190825  0.335
2011 Zhao X, Minz J, Lim SK. Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs Ieee Transactions On Components, Packaging and Manufacturing Technology. 1: 247-259. DOI: 10.1109/Tcpmt.2010.2099590  0.527
2011 Zhao X, Lewis DL, Lee HHS, Lim SK. Low-power clock tree design for pre-bond testing of 3-D stacked ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 732-745. DOI: 10.1109/Tcad.2010.2098130  0.434
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