Yongchan (James) Ban - Publications

Affiliations: 
2011 University of Texas at Austin, Austin, Texas, U.S.A. 

15 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Ban Y. Analysis of the Impact of Variations on Signal Electro-Migration and Optimization of Interconnects in FinFET Designs. Journal of Nanoscience and Nanotechnology. 16: 4684-91. PMID 27483808  0.01
2016 Ban Y, Han SM, Choi E, Gbondo-Tugbawa T, Chen KH. Model-based CMP aware RC extraction of interconnects in 16nm designs Proceedings of Spie. 9781. DOI: 10.1117/12.2219118  0.01
2016 Ban Y, Kang Y, Paik W. Model-based CMP (Chemical-Mechanical Polishing) proximity correction for mitigating systematic process variations Isocc 2015 - International Soc Design Conference: Soc For Internet of Everything (Ioe). 7-8. DOI: 10.1109/ISOCC.2015.7401685  1
2014 Ban Y, Sweis J, Hurat P, Lai Y, Kang Y, Paik WH, Xu W, Song H. Layout induced variability and manufacturability checks in FinFETs process Proceedings of Spie. 9053. DOI: 10.1117/12.2046284  1
2014 Ban Y, Choi C, Shin H, Kang Y, Paik WH. Analysis and optimization of process-induced electromigration on signal interconnects in 16nm FinFET SoC (system-on-chip) Proceedings of Spie. 9053. DOI: 10.1117/12.2046207  1
2014 Ban Y, Pan DZ. Self-aligned double-patterning layout decomposition for two-dimensional random metals for sub-10-nm node design Journal of Micro-Nanolithography Mems and Moems. 14: 11004-11004. DOI: 10.1117/1.Jmm.14.1.011004  1
2011 Ban Y, Miloslavsky A, Lucas K, Choi SH, Park CH, Pan DZ. Layout decomposition of self-aligned double patterning for 2D random logic patterning Proceedings of Spie - the International Society For Optical Engineering. 7974. DOI: 10.1117/12.879500  1
2011 Ban Y, Pan DZ. Modeling of Layout Aware Line-Edge Roughness and Poly Optimization for Leakage Minimization Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 150-159. DOI: 10.1109/Jetcas.2011.2159286  1
2010 Ban Y, Sundareswaran S, Pan DZ. Total sensitivity based DFM optimization of standard library cells Proceedings of the International Symposium On Physical Design. 113-120. DOI: 10.1145/1735023.1735053  1
2010 Ban Y, Ma Y, Levinson HJ, Deng Y, Kye J, Pan DZ. Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations in 32-nm node standard cell Proceedings of Spie. 7641. DOI: 10.1117/12.846654  1
2010 Ban Y, Ma Y, Levinson HJ, Pan DZ. Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations Journal of Micro-Nanolithography Mems and Moems. 9: 41211. DOI: 10.1117/1.3504697  1
2010 Ban Y, Sundareswaran S, Pan DZ. Electrical impact of line-edge roughness on sub-45-nm node standard cells Journal of Micro/Nanolithography, Mems, and Moems. 9. DOI: 10.1117/1.3500746  1
2009 Ban Y, Sundareswaran S, Panda R, Pan DZ. Electrical impact of line-edge roughness on sub-45nm node standard cell Proceedings of Spie - the International Society For Optical Engineering. 7275. DOI: 10.1117/12.814355  1
2009 Cho M, Yuan K, Ban Y, Pan DZ. ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1006-1016. DOI: 10.1109/Tcad.2009.2018876  1
2000 Ying J, Ye YL, Ban Y, Liu HT, Zhu ZM, Zhu ZY, Chen T, Ma JG, Qian SJ. Study of an avalanche-mode resistive plate chamber Journal of Physics G. 26: 1291-1298. DOI: 10.1088/0954-3899/26/8/315  1
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