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Subhendu Roy - Publications

Affiliations: 
2015 University of Texas at Austin, Austin, Texas, U.S.A. 
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8 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Ma Y, Roy S, Miao J, Chen J, Yu B. Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 2298-2311. DOI: 10.1109/Tcad.2018.2878129  0.618
2018 Miao J, Li M, Roy S, Ma Y, Yu B. SD-PUF: Spliced Digital Physical Unclonable Function Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 927-940. DOI: 10.1109/Tcad.2017.2740296  0.584
2016 Roy S, Liu D, Singh J, Um J, Pan DZ. OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations under Multiple Operating Conditions Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1618-1629. DOI: 10.1109/Tcad.2016.2523439  0.535
2016 Roy S, Choudhury M, Puri R, Pan DZ. Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 820-831. DOI: 10.1109/Tcad.2015.2481794  0.544
2016 Yu B, Xu X, Roy S, Lin Y, Ou J, Pan DZ. Design for manufacturability and reliability in extreme-scaling VLSI Science China Information Sciences. 1-23. DOI: 10.1007/S11432-016-5560-6  0.449
2015 Roy S, Mattheakis PM, Masse-Navette L, Pan DZ. Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 589-602. DOI: 10.1109/Tcad.2015.2394310  0.466
2014 Yu B, Roy S, Gao J, Pan DZ. Triple patterning lithography layout decomposition using end-cutting Journal of Micro-Nanolithography Mems and Moems. 14: 11002-11002. DOI: 10.1117/1.Jmm.14.1.011002  0.555
2014 Roy S, Choudhury M, Puri R, Pan DZ. Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 1517-1530. DOI: 10.1109/Tcad.2014.2341926  0.467
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