Yibo Lin, Ph.D. - Publications

Affiliations: 
2019- Department of Computer Science Peking University, Beijing, Beijing Shi, China 
Area:
physical design, machine learning applications, emerging technology in VLSI CAD, hardware security
Website:
http://yibolin.com/

24 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Lu K, Jin Q, Lin Y, Lu W, Li S, Zhou C, Jin J, Jiang Q, Ling L, Xiao M. Cell-Free Fermentation Broth of Strain S3-1 Improves Pak Choi Nutritional Quality and Changes the Bacterial Community Structure of the Rhizosphere Soil. Frontiers in Microbiology. 11: 2043. PMID 33071994 DOI: 10.3389/fmicb.2020.02043  0.56
2020 Chen Y, Lin Y, Chen R, Dong L, Wu R, Gai T, Ma L, Su Y, Wei Y. EUV multilayer defect characterization via cycle-consistent learning. Optics Express. 28: 18493-18506. PMID 32680047 DOI: 10.1364/Oe.394590  0.32
2020 Lin Y, Jiang Z, Gu J, Li W, Dhar S, Ren H, Khailany B, Pan DZ. DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2020.3003843  0.96
2020 Cai J, Yan C, Tao Y, Lin Y, Wang S, Pan DZ, Zeng X. A Novel and Unified Full-chip CMP Model Aware Dummy Fill Insertion Framework with SQP-Based Optimization Method Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2020.3001380  0.96
2020 Alawieh MB, Lin Y, Zhang Z, Li M, Huang Q, Pan DZ. GAN-SRAF: Sub-Resolution Assist Feature Generation using Generative Adversarial Networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2020.2995338  0.96
2020 Lin Y, Li W, Gu J, Ren H, Khailany B, Pan DZ. ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2020.2971531  0.96
2020 Chen Y, Lin Y, Gai T, Su Y, Wei Y, Pan DZ. Semisupervised Hotspot Detection With Self-Paced Multitask Learning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 1511-1523. DOI: 10.1109/Tcad.2019.2912948  0.96
2020 Chen H, Liu M, Xu B, Zhu K, Tang X, Li S, Lin Y, Sun N, Pan DZ. MAGICAL: An Open-Source Fully Automated Analog IC Layout System from Netlist to GDSII Ieee Design & Test of Computers. 1-1. DOI: 10.1109/Mdat.2020.3024153  0.96
2020 Chen J, Alawieh MB, Lin Y, Zhang M, Zhang J, Guo Y, Pan DZ. Automatic Selection of Structure Parameters of Silicon on Insulator Lateral Power Device Using Bayesian Optimization Ieee Electron Device Letters. 41: 1288-1291. DOI: 10.1109/Led.2020.3013571  0.96
2020 Chen J, Alawieh MB, Lin Y, Zhang M, Zhang J, Guo Y, Pan DZ. Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks Ieee Access. 8: 25372-25382. DOI: 10.1109/Access.2020.2970966  0.96
2019 Chen Y, Lin Y, Dong L, Gai T, Chen R, Su Y, Wei Y, Pan DZ. SoulNet: ultrafast optical source optimization utilizing generative neural networks for advanced lithography Journal of Micro-Nanolithography Mems and Moems. 18: 43506. DOI: 10.1117/1.Jmm.18.4.043506  0.96
2019 Chen J, Lin Y, Guo Y, Zhang M, Alawieh MB, Pan DZ. Lithography hotspot detection using a double inception module architecture Journal of Micro-Nanolithography Mems and Moems. 18: 13507. DOI: 10.1117/1.Jmm.18.1.013507  0.96
2019 Li M, Yu B, Lin Y, Xu X, Li W, Pan DZ. A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 1585-1598. DOI: 10.1109/Tcad.2018.2859402  0.96
2018 Lin Y, Yu B, Li M, Pan DZ. Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1574-1587. DOI: 10.1109/Tcad.2017.2760511  0.96
2018 Xu X, Lin Y, Li M, Matsunawa T, Nojima S, Kodama C, Kotani T, Pan DZ. Subresolution Assist Feature Generation With Supervised Data Learning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1225-1236. DOI: 10.1109/Tcad.2017.2748029  0.96
2018 Lin Y, Yu B, Xu X, Gao J, Viswanathan N, Liu W, Li Z, Alpert CJ, Pan DZ. MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1237-1250. DOI: 10.1109/Tcad.2017.2748025  0.96
2017 Lin Y, Xu X, Yu B, Baldick R, Pan DZ. Triple/quadruple patterning layout decomposition via linear programming and iterative rounding Journal of Micro-Nanolithography Mems and Moems. 16: 23507-23507. DOI: 10.1117/1.Jmm.16.2.023507  0.96
2017 Xu X, Lin Y, Li M, Ou J, Cline B, Pan DZ. Redundant Local-Loop Insertion for Unidirectional Routing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1113-1125. DOI: 10.1109/Tcad.2017.2651811  0.96
2017 Lin Y, Yu B, Xu B, Pan DZ. Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1140-1152. DOI: 10.1109/Tcad.2017.2648843  0.96
2017 Lin Y, Yu B, Pan DZ. High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1532-1544. DOI: 10.1109/Tcad.2016.2638452  0.96
2016 Lin Y, Xu X, Yu B, Baldick R, Pan DZ. Triple/quadruple patterning layout decomposition via novel linear programming and iterative rounding Proceedings of Spie. 9781. DOI: 10.1117/12.2218628  0.96
2016 Lin Y, Yu B, Xu B, Pan DZ. Triple patterning aware detailed placement toward zero cross-row middle-of-line conflict 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 396-403. DOI: 10.1109/ICCAD.2015.7372597  0.96
2016 Yu B, Xu X, Roy S, Lin Y, Ou J, Pan DZ. Design for manufacturability and reliability in extreme-scaling VLSI Science China Information Sciences. 1-23. DOI: 10.1007/S11432-016-5560-6  0.96
2015 Yu B, Xu X, Gao J, Lin Y, Li Z, Alpert CJ, Pan DZ. Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 726-739. DOI: 10.1109/Tcad.2015.2401571  0.96
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