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Shaolan Li, Ph.D. - Publications

Affiliations: 
2019- School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA 
Area:
analog mixed-signal integrated systems
Website:
https://gamma.ece.gatech.edu/people/
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10 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Chen H, Liu M, Xu B, Zhu K, Tang X, Li S, Lin Y, Sun N, Pan DZ. MAGICAL: An Open-Source Fully Automated Analog IC Layout System from Netlist to GDSII Ieee Design & Test of Computers. 1-1. DOI: 10.1109/Mdat.2020.3024153  0.46
2020 Tang X, Yang X, Zhao W, Hsu C, Liu J, Shen L, Mukherjee A, Shi W, Li S, Pan DZ, Sun N. A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier Ieee Journal of Solid-State Circuits. 1-1. DOI: 10.1109/Jssc.2020.3020194  0.508
2020 Tang X, Li S, Yang X, Shen L, Zhao W, Williams RP, Liu J, Tan Z, Hall NA, Pan DZ, Sun N. An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter Ieee Journal of Solid-State Circuits. 1-1. DOI: 10.1109/Jssc.2020.3005812  0.421
2020 Zhong Y, Li S, Tang X, Shen L, Zhao W, Wu S, Sun N. A Second-Order Purely VCO-Based CT $\Delta\Sigma$ ADC Using a Modified DPLL Structure in 40-nm CMOS Ieee Journal of Solid-State Circuits. 55: 356-368. DOI: 10.1109/Jssc.2019.2948008  0.575
2020 Li S, Pan DZ, Sun N. An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback Ieee Journal of Solid-State Circuits. 55: 1337-1350. DOI: 10.1109/Jssc.2019.2941007  0.56
2019 Liu J, Hsu C, Tang X, Li S, Wen G, Sun N. Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters Ieee Transactions On Circuits and Systems I-Regular Papers. 66: 1342-1354. DOI: 10.1109/Tcsi.2018.2879582  0.452
2019 Shen L, Sun N, Shen Y, Li Z, Shi W, Tang X, Li S, Zhao W, Zhang M, Zhu Z. A Two-Step ADC With a Continuous-Time SAR-Based First Stage Ieee Journal of Solid-State Circuits. 54: 3375-3385. DOI: 10.1109/Jssc.2019.2933951  0.56
2019 Liu J, Li S, Guo W, Wen G, Sun N. A 0.029-mm 2 17-fJ/Conversion-Step Third-Order CT $\Delta\Sigma$ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer Ieee Journal of Solid-State Circuits. 54: 428-440. DOI: 10.1109/Jssc.2018.2879955  0.557
2018 Li S, Qiao B, Gandara M, Pan DZ, Sun N. A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure Ieee Journal of Solid-State Circuits. 53: 3484-3496. DOI: 10.1109/Jssc.2018.2871081  0.566
2017 Li S, Mukherjee A, Sun N. A 174.3-dB FoM VCO-Based CT $\Delta \Sigma $ Modulator With a Fully-Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130-nm CMOS Ieee Journal of Solid-State Circuits. 52: 1940-1952. DOI: 10.1109/Jssc.2017.2693244  0.554
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