| Year |
Citation |
Score |
| 2015 |
Hamzaoglu F, Arslan U, Bisnik N, Ghosh S, Lal MB, Lindert N, Meterelliyoz M, Osborne RB, Park J, Tomishima S, Wang Y, Zhang K. A 1 Gb 2 GHz 128 GB/s bandwidth embedded DRAM in 22 nm tri-gate CMOS technology Ieee Journal of Solid-State Circuits. 50: 150-157. DOI: 10.1109/Jssc.2014.2353793 |
0.523 |
|
| 2014 |
Hamzaoglu F, Arslan U, Bisnik N, Ghosh S, Lal MB, Lindert N, Meterelliyoz M, Osborne RB, Park J, Tomishima S, Wang Y, Zhang K. 13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 57: 230-231. DOI: 10.1109/ISSCC.2014.6757412 |
0.387 |
|
| 2013 |
Wang Y, Arslan U, Bisnik N, Brain R, Ghosh S, Hamzaoglu F, Lindert N, Meterelliyoz M, Park J, Tomishima S, Zhang K. Retention time optimization for eDRAM in 22nm tri-gate CMOS technology Technical Digest - International Electron Devices Meeting, Iedm. 9.5.1-9.5.4. DOI: 10.1109/IEDM.2013.6724595 |
0.471 |
|
| 2013 |
Brain R, Baran A, Bisnik N, Chen HP, Choi SJ, Chugh A, Fradkin M, Glassman T, Hamzaoglu F, Hoggan E, Jahan R, Jamil M, Jan CH, Jopling J, Kan H, ... ... Lindert N, et al. A 22nm high performance embedded DRAM SoC technology featuring tri-gate transistors and MIMCAP COB Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. T16-T17. |
0.448 |
|
| 2010 |
Van Der Voorn P, Agostinelli M, Choi SJ, Curello G, Deshpande H, El-Tanani MA, Hafez W, Jalan U, Janbay L, Kang M, Koh KJ, Komeyli K, Lakdawala H, Lin J, Lindert N, et al. A 32nm low power RF CMOS SOC technology featuring high-k/metal gate Digest of Technical Papers - Symposium On Vlsi Technology. 137-138. DOI: 10.1109/VLSIT.2010.5556201 |
0.448 |
|
| 2008 |
Jan CH, Bai P, Biswas S, Buehler M, Chen ZP, Curello G, Gannavaram S, Hafez W, He J, Hicks J, Jalan U, Lazo N, Lin J, Lindert N, Litteken C, et al. A 45nm low power system-on-chip technology with dual gate (Logic and I/O) high-k/ metal gate strained silicon transistors Technical Digest - International Electron Devices Meeting, Iedm. DOI: 10.1109/IEDM.2008.4796772 |
0.473 |
|
| 2006 |
Post I, Akbar M, Curello G, Gannavaram S, Hafez W, Jalan U, Komeyll K, Lin J, Lindert N, Park J, Rizk J, Sacks G, Tsai C, Yeh D, Bai P, et al. A 65nm CMOS SOC technology featuring strained silicon transistors for RF applications Technical Digest - International Electron Devices Meeting, Iedm. DOI: 10.1109/IEDM.2006.346816 |
0.404 |
|
| 2005 |
Tyagi S, Auth C, Bai P, Curello G, Deshpande H, Gamavaram S, Golonzka O, Heussner R, James R, Kenyon C, Lee SH, Lindert N, Liu M, Nagisetty R, Natarajan S, et al. An advanced low power, high performance, strained channel 65nm technology Technical Digest - International Electron Devices Meeting, Iedm. 2005: 245-247. |
0.404 |
|
| 2005 |
Jan CH, Bai P, Choi J, Curello G, Jacobs S, Jeong J, Johnson K, Jones D, Klopcic S, Lin J, Lindert N, Lio A, Natarajan S, Neirynck J, Packan P, et al. A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors Technical Digest - International Electron Devices Meeting, Iedm. 2005: 60-63. |
0.401 |
|
| 2004 |
Bai P, Auth C, Balakrishnan S, Bost M, Brain R, Chikarmane V, Heussner R, Hussein M, Hwang J, Ingerly D, James R, Jeong J, Kenyon C, Lee E, Lee SH, ... Lindert N, et al. A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm2 SRAM cell Technical Digest - International Electron Devices Meeting, Iedm. 657-660. |
0.486 |
|
| 2003 |
Chang L, Choi YK, Kedzierski J, Lindert N, Xuan P, Bokor J, Hu C, King TJ. Moore's law lives on Ieee Circuits and Devices Magazine. 19: 35-42. DOI: 10.1109/Mcd.2003.1175106 |
0.592 |
|
| 2001 |
Lindert N, Chang L, Choi YK, Anderson EH, Lee WC, King TJ, Bokor J, Hu C. Sub-60-nm quasi-planar FinFETs fabricated using a simplified process Ieee Electron Device Letters. 22: 487-489. DOI: 10.1109/55.954920 |
0.596 |
|
| 2001 |
Choi YK, Lindert N, Xuan P, Tang S, Ha D, Anderson E, King TJ, Bokor J, Hu C. Sub-20nm CMOS FinFET technologies Technical Digest - International Electron Devices Meeting. 421-424. |
0.356 |
|
| 2001 |
Lindert N, Choi YK, Chang L, Anderson E, Lee W, King TJ, Bokor J, Hu C. Quasi-planar NMOS FinFETs with sub-100nm gate lengths Annual Device Research Conference Digest. 26-27. |
0.637 |
|
| 2001 |
Tang SH, Chang L, Lindert N, Choi YK, Lee WC, Huang X, Subramanian V, Bokor J, King TJ, Hu C. FinFET - A quasi-planar double-gate MOSFET Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 118-119+437. |
0.567 |
|
| 2001 |
Lindert N, Choi YK, Chang L, Anderson E, Lee WC, King TJ, Bokor J, Hu C. Quasi-planar FinFETs with selectively grown germanium raised source/drain Ieee International Soi Conference. 111-112. |
0.459 |
|
| 2000 |
Choi YK, Asano K, Lindert N, Subramanian V, King TJ, Bokor J, Chenming H. Ultrathin-body SOI MOSFET for deep-sub-tenth micron era Ieee Electron Device Letters. 21: 254-255. DOI: 10.1109/55.841313 |
0.601 |
|
| 1999 |
Lindert N, Sugii T, Tang S, Hu C. Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages Ieee Journal of Solid-State Circuits. 34: 85-89. DOI: 10.1109/4.736659 |
0.531 |
|
| 1999 |
Subramanian V, Kedzierski J, Lindert N, Tam H, Su Y, McHale J, Cao K, King TJ, Bokor J, Hu C. Bulk-Si-compatible ultrathin-body SOI technology for sub-100 nm MOSFETs Annual Device Research Conference Digest. 28-29. |
0.547 |
|
| 1999 |
Choi YK, Asano K, Lindert N, Subramanian V, King TJ, Bokor J, Hu C. Ultra-thin body SOI MOSFET for deep-sub-tenth micron era Technical Digest - International Electron Devices Meeting. 919-921. |
0.452 |
|
| 1996 |
Lindert N, Yoshida M, Wann C, Hu C. Comparison of GIDL in p+-poly PMOS and n+-poly PMOS Devices Ieee Electron Device Letters. 17: 285-287. DOI: 10.1109/55.496459 |
0.57 |
|
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