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Chien-In H. Chen - Publications

Affiliations: 
Wright State University, Fairborn, OH, United States 
Area:
Electronics and Electrical Engineering
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10 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Benson S, Chen CH, Lin DM, Liou LL. Digital linear chirp receiver for high chirp rates with high resolution time-of-arrival and time-of-departure estimation Ieee Transactions On Aerospace and Electronic Systems. 52: 1146-1154. DOI: 10.1109/Taes.2016.140656  0.325
2015 Chen J, Chen CH. Process Variation Aware Wide Tuning Band Pass Filter for Steep Roll-Off High Rejection Vlsi Design. 2015: 1-9. DOI: 10.1155/2015/408035  0.303
2012 Yelamarthi K, Chen CH. Timing Optimization and Noise Tolerance for Dynamic CMOS Susceptible to Process Variations Ieee Transactions On Semiconductor Manufacturing. 25: 255-265. DOI: 10.1109/Tsm.2012.2185961  0.328
2011 George K, Chen CH. A Hybrid Computing Platform Digital Wideband Receiver Design and Performance Measurement Ieee Transactions On Instrumentation and Measurement. 60: 3956-3958. DOI: 10.1109/Tim.2011.2152590  0.352
2009 Lee Y-G, Chen CH. Dynamic Kernel Function Fast Fourier Transform With Variable Truncation Scheme for Wideband Coarse Frequency Detection Ieee Transactions On Instrumentation and Measurement. 58: 1555-1562. DOI: 10.1109/Tim.2009.2012962  0.346
2008 Yelamarthi K, Chen CH. Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization Journal of Computers. 3: 21-28. DOI: 10.4304/Jcp.3.2.21-28  0.303
2007 Wang M, Chen CH, Radhakrishnan S. Low-Power 4-b 2.5-GSPS Pipelined Flash Analog-to-Digital Converter in 130-nm CMOS Ieee Transactions On Instrumentation and Measurement. 56: 1064-1073. DOI: 10.1109/Tim.2006.887404  0.585
2002 Chen CH, Wagh M. Testability Synthesis for Jumping Carry Adders Vlsi Design. 2002: 155-169. DOI: 10.1080/10655140290010079  0.326
2002 Huang JA, Chen CH. Timing-Driven-Testable Convergent Tree Adders Vlsi Design. 2002: 637-645. DOI: 10.1080/1065514021000012255  0.318
1994 Chen CH, Kumar A. Comments on "Area-time optimal adder design" Ieee Transactions On Computers. 43: 507-512. DOI: 10.1109/12.278491  0.314
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