Lih-yih Chiou, Ph.D. - Publications

Affiliations: 
2003 Purdue University, West Lafayette, IN, United States 
Area:
Electronics and Electrical Engineering

14 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2018 Chien T, Chiou L, Chang C, Huang J, Wu C, Lee H, Sheu S. Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F 2 /Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM Ieee Transactions On Circuits and Systems Ii-Express Briefs. 65: 1234-1238. DOI: 10.1109/Tcsii.2017.2778246  0.311
2018 Lu L, Chiou L. Temperature Gradient Exploration Method for Determining the Appropriate Number of Cells in Mesh-Based Thermal Analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 3216-3220. DOI: 10.1109/Tcad.2018.2801225  0.313
2017 Yang C, Chang C, Lee S, Chang S, Chiou L. Efficient Four-Coil Wireless Power Transfer for Deep Brain Stimulation Ieee Transactions On Microwave Theory and Techniques. 65: 2496-2507. DOI: 10.1109/Tmtt.2017.2658560  0.334
2016 Chien TK, Chiou LY, Sheu SS, Lin JC, Lee CC, Ku TK, Tsai MJ, Wu CI. Low-Power MCU With Embedded ReRAM Buffers as Sensor Hub for IoT Applications Ieee Journal On Emerging and Selected Topics in Circuits and Systems. DOI: 10.1109/Jetcas.2016.2547778  0.364
2015 Wang Y, Tsai ML, Chiou LY, Pan MH, Ho CT. Antitumor activity of garcinol in human prostate cancer cells and xenograft mice. Journal of Agricultural and Food Chemistry. PMID 26442822 DOI: 10.1021/Acs.Jafc.5B03851  0.395
2010 Luo S, Chiou L. A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing Ieee Transactions On Circuits and Systems Ii-Express Briefs. 57: 440-445. DOI: 10.1109/Tcsii.2010.2048360  0.345
2009 Chiou L, Luo S. Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics Ieee Transactions On Very Large Scale Integration Systems. 17: 1659-1663. DOI: 10.1109/Tvlsi.2008.2007959  0.359
2009 Chiou L, Chen Y, Lee C. System-Level Bus-Based Communication Architecture Exploration Using a Pseudoparallel Algorithm Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1213-1223. DOI: 10.1109/Tcad.2009.2021733  0.372
2006 Chang M, Chiou L, Wen K. Crosstalk-insensitive via-programming ROMs using content-aware design framework Ieee Transactions On Circuits and Systems Ii-Express Briefs. 53: 443-447. DOI: 10.1109/Tcsii.2006.873640  0.314
2006 Chang M, Chiou L, Wen K-. A full code-patterns coverage high-speed embedded ROM using dynamic virtual guardian technique Ieee Journal of Solid-State Circuits. 41: 496-506. DOI: 10.1109/Jssc.2005.862343  0.301
2005 Chiou L, Bhunia S, Roy K. Synthesis of application-specific highly efficient multi-mode cores for embedded systems Acm Transactions On Embedded Computing Systems (Tecs). 4: 168-188. DOI: 10.1145/1053271.1053278  0.518
2002 Johnson MC, Somasekhar D, Chiou L, Roy K. Leakage control with efficient use of transistor stacks in single threshold CMOS Ieee Transactions On Very Large Scale Integration Systems. 10: 1-5. DOI: 10.1109/92.988724  0.455
2001 Chiou L, Muhammand K, Roy K. Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications Vlsi Design. 12: 233-243. DOI: 10.1155/2001/35832  0.442
2000 Krishnamoorthy AV, Chiou L, Rozier RG, Kibar O. Concentrator circuit with multiple priority levels Electronics Letters. 36: 500-501. DOI: 10.1049/El:20000287  0.325
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