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Sri H. Choday, Ph.D. - Publications

Affiliations: 
2014 Electrical and Computer Engineering Purdue University, West Lafayette, IN, United States 
Area:
Electronics and Electrical Engineering, Computer Engineering
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20 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2018 Davies M, Srinivasa N, Lin T, Chinya G, Cao Y, Choday SH, Dimou G, Joshi P, Imam N, Jain S, Liao Y, Lin C, Lines A, Liu R, Mathaikutty D, et al. Loihi: A Neuromorphic Manycore Processor with On-Chip Learning Ieee Micro. 38: 82-99. DOI: 10.1109/Mm.2018.112130359  0.32
2016 Fong X, Kim Y, Venkatesan R, Choday SH, Raghunathan A, Roy K. Spin-Transfer Torque Memories: Devices, Circuits, and Systems Proceedings of the Ieee. DOI: 10.1109/JPROC.2016.2521712  0.789
2015 Choday SH, Kwon KW, Roy K. Workload dependent evaluation of thin-film thermoelectric devices for on-chip cooling and energy harvesting Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2015: 535-541. DOI: 10.1109/ICCAD.2014.7001402  0.507
2015 Sengupta A, Choday SH, Kim Y, Roy K. Spin orbit torque based electronic neuron Applied Physics Letters. 106: 143701. DOI: 10.1063/1.4917011  0.555
2015 Fong X, Choday SH, Roy K. Design and optimization of spin-transfer torque MRAMs More Than Moore Technologies For Next Generation Computer Design. 49-72. DOI: 10.1007/978-1-4939-2163-8_3  0.805
2014 Kwon KW, Choday SH, Kim Y, Roy K. AWARE (Asymmetric Write Architecture with REdundant Blocks): A high write speed STT-MRAM cache architecture Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 712-720. DOI: 10.1109/Tvlsi.2013.2256945  0.653
2014 Fong X, Kim Y, Choday SH, Roy K. Failure mitigation techniques for 1T-1MTJ spin-transfer torque MRAM bit-cells Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 384-395. DOI: 10.1109/Tvlsi.2013.2239671  0.769
2014 Choday SH, Gupta SK, Roy K. Write-optimized STT-MRAM bit-cells using asymmetrically doped transistors Ieee Electron Device Letters. 35: 1100-1102. DOI: 10.1109/Led.2014.2358998  0.732
2014 Kwon KW, Choday SH, Kim Y, Fong X, Park SP, Roy K. SHE-NVFF: Spin hall effect-based nonvolatile flip-flop for power gating architecture Ieee Electron Device Letters. 35: 488-490. DOI: 10.1109/Led.2014.2304683  0.782
2013 Mojumder NN, Fong X, Augustine C, Gupta SK, Choday SH, Roy K. Dual pillar spin-transfer torque MRAMs for low power applications Acm Journal On Emerging Technologies in Computing Systems. 9. DOI: 10.1145/2463585.2463590  0.755
2013 Choday SH, Lundstrom MS, Roy K. Prospects of thin-film thermoelectric devices for hot-spot cooling and on-chip energy harvesting Ieee Transactions On Components, Packaging and Manufacturing Technology. 3: 2059-2067. DOI: 10.1109/Tcpmt.2013.2273873  0.477
2013 Choday SH, Lu C, Raghunathan V, Roy K. On-chip energy harvesting using thin-film thermoelectric materials Annual Ieee Semiconductor Thermal Measurement and Management Symposium. 99-104. DOI: 10.1109/SEMI-THERM.2013.6526812  0.332
2013 Kim Y, Choday SH, Roy K. DSH-MRAM: Differential spin hall MRAM for on-chip memories Ieee Electron Device Letters. 34: 1259-1261. DOI: 10.1109/Led.2013.2279153  0.683
2013 Goud AA, Gupta SK, Choday SH, Roy K. Atomistic tight-binding based evaluation of impact of gate underlap on source to drain tunneling in 5 nm gate length Si FinFETs Device Research Conference - Conference Digest, Drc. 51-52. DOI: 10.1109/DRC.2013.6633788  0.517
2013 Choday SH, Roy K. Sensitivity analysis and optimization of thin-film thermoelectric coolers Journal of Applied Physics. 113. DOI: 10.1063/1.4807282  0.433
2012 Fong X, Choday SH, Roy K. Bit-cell level optimization for non-volatile memories using magnetic tunnel junctions and spin-transfer torque switching Ieee Transactions On Nanotechnology. 11: 172-181. DOI: 10.1109/Tnano.2011.2169456  0.797
2012 Augustine C, Mojumder NN, Fong X, Choday SH, Park SP, Roy K. Spin-transfer torque MRAMs for low power memories: Perspective and prospective Ieee Sensors Journal. 12: 756-766. DOI: 10.1109/Jsen.2011.2124453  0.771
2011 Mojumder NN, Gupta SK, Choday SH, Nikonov DE, Roy K. A three-terminal dual-pillar STT-MRAM for high-performance robust memory applications Ieee Transactions On Electron Devices. 58: 1508-1516. DOI: 10.1109/Ted.2011.2116024  0.793
2011 Fong X, Gupta SK, Mojumder NN, Choday SH, Augustine C, Roy K. KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells International Conference On Simulation of Semiconductor Processes and Devices, Sispad. 51-54. DOI: 10.1109/SISPAD.2011.6035047  0.717
2011 Gupta SK, Choday SH, Roy K. Exploration of device-circuit interactions in FinFET-based memories for sub-15nm technologies using a mixed mode quantum simulation framework: Atoms to systems Technical Digest - International Electron Devices Meeting, Iedm. 32.5.1-32.5.4. DOI: 10.1109/IEDM.2011.6131659  0.639
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