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Chifeng Wang, Ph.D. - Publications

Affiliations: 
2012 Electrical and Computer Engineering - Ph.D. University of California, Irvine, Irvine, CA 
Area:
Computer Engineering, Electronics and Electrical Engineering
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8 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2015 Hu W, Wang C, Bagherzadeh N. Design and analysis of a mesh-based wireless network-on-chip The Journal of Supercomputing. 71: 2830-2846. DOI: 10.1007/S11227-014-1341-4  0.579
2014 Wang C. An adaptive algorithm based on wireless sensor network to predict traffic hazard Wit Transactions On Information and Communication Technologies. 59: 569-576. DOI: 10.2495/ICACC130761  0.325
2014 Wang C, Bagherzadeh N. Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip Microprocessors and Microsystems. 38: 304-315. DOI: 10.1016/J.Micpro.2013.09.006  0.561
2013 Wang C, Hu W, Bagherzadeh N. Scalable load balancing congestion-aware Network-on-Chip router architecture Journal of Computer and System Sciences. 79: 421-439. DOI: 10.1016/J.Jcss.2012.09.007  0.709
2012 Wang C, Bagherzadeh N. High-throughput differentiated service provision router architecture for wireless network-on-chip International Journal of High Performance Systems Architecture. 4: 38-56. DOI: 10.1504/Ijhpsa.2012.047578  0.677
2012 Alhussien A, Wang C, Bagherzadeh N. Design and evaluation of a high throughput robust router for network-on-chip Iet Computers and Digital Techniques. 6: 173-179. DOI: 10.1049/Iet-Cdt.2011.0082  0.509
2012 Wang C, Hu W, Bagherzadeh N. A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms Microprocessors and Microsystems. 36: 555-570. DOI: 10.1016/J.Micpro.2011.10.002  0.703
2011 Wang C, Hu W, Lee SE, Bagherzadeh N. Area and power-efficient innovative congestion-aware Network-on-Chip architecture Journal of Systems Architecture. 57: 24-38. DOI: 10.1016/J.Sysarc.2010.10.009  0.696
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