☰

Eui-Young Chung, Ph.D. - Publications

Affiliations: 
2002 Stanford University, Palo Alto, CA 
Area:
Electronics and Electrical Engineering
Tree Info Similar researchers PubMed Report error

50 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Oh M, Kim K, Choi D, Lee H, Chung E. Per-Operation Reusability Based Allocation and Migration Policy for Hybrid Cache Ieee Transactions On Computers. 69: 158-171. DOI: 10.1109/Tc.2019.2944163  0.359
2019 Kim M, Jung W, Lee H, Chung E. A Novel NAND Flash Memory Architecture for Maximally Exploiting Plane-Level Parallelism Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 27: 1957-1961. DOI: 10.1109/Tvlsi.2019.2905626  0.386
2019 Hong J, Kim J, Han S, Chung E. A Locality-Aware Compression Scheme for Highly Reliable Embedded Systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 453-465. DOI: 10.1109/Tcad.2018.2818692  0.398
2018 Hong J, Han S, Park YM, Chung E. ICS: Interrupt-Based Channel Sneaking for Maximally Exploiting Die-Level Parallelism of NAND Flash-Based Storage Devices Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 1802-1806. DOI: 10.1109/Tvlsi.2018.2824818  0.346
2018 Lee B, Kim K, Chung E. Replacement Policy Adaptable Miss Curve Estimation for Efficient Cache Partitioning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 445-457. DOI: 10.1109/Tcad.2017.2712666  0.313
2018 Shin HH, Park YM, Choi D, Kim BJ, Cho D, Chung E. EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory Ieee Transactions On Computers. 67: 32-44. DOI: 10.1109/Tc.2017.2723392  0.379
2017 Kim T, Lim J, Kim J, Cho W, Chung E, Lee H. Scalable Bandwidth Shaping Scheme via Adaptively Managed Parallel Heaps in Manycore-Based Network Processors Acm Transactions On Design Automation of Electronic Systems. 22: 1-26. DOI: 10.1145/3065926  0.436
2017 Kim J, You T, Seo H, Yoon S, Gaudiot J, Chung E. An effective pre-store/pre-load method exploiting intra-request idle time of NAND flash-based storage devices Microprocessors and Microsystems. 50: 222-236. DOI: 10.1016/J.Micpro.2017.03.007  0.59
2016 Won S, Chung E. Power Optimization Method Using Peak Current Modeling for NAND Flash-based Storage Devices Journal of the Institute of Electronics and Information Engineers. 53: 43-50. DOI: 10.5573/Ieie.2016.53.1.043  0.365
2016 Won S, Chung E. SLC Buffer Performance Improvement using Page Overwriting Method in TLC NAND Flash-based Storage Devices Journal of the Institute of Electronics and Information Engineers. 53: 36-42. DOI: 10.5573/Ieie.2016.53.1.036  0.427
2016 Joo HW, Chung EY. DHL-cache: Dynamic per history length adjustment for low-power L2 cache Electronics Letters. 52: 1297-1298. DOI: 10.1049/El.2016.1465  0.323
2015 Kim JY, Park SH, Seo H, Song KW, Yoon S, Chung EY. NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2409055  0.573
2014 Yu S, Yoon S, Chung EY, Lee HJ. Design of a bitmap-based QoS-aware memory controller for a packet memory Ieice Electronics Express. 11. DOI: 10.1587/Elex.11.20130983  0.456
2014 Kim SH, Lee SH, Jun M, Lee B, Ro WW, Chung EY, Gaudiot JL. C-Lock: Energy efficient synchronization for embedded multicore systems Ieee Transactions On Computers. 63: 1962-1974. DOI: 10.1109/Tc.2013.84  0.375
2014 Jun M, Ro WW, Chung EY. Exploiting implementation diversity and partial connection of routers in application-specific network-on-chip topology synthesis Ieee Transactions On Computers. 63: 1433-1444. DOI: 10.1109/Tc.2012.294  0.365
2014 Park SH, Kim DG, Bang K, Lee HJ, Yoo S, Chung EY. An adaptive idle-time exploiting method for low latency NAND flash-based storage devices Ieee Transactions On Computers. 63: 1085-1096. DOI: 10.1109/Tc.2012.281  0.418
2014 Chou YL, Liu S, Chung EY, Gaudiot JL. An energy and performance efficient DVFS scheme for irregular parallel divide-and-conquer algorithms on the intel SCC Ieee Computer Architecture Letters. 13: 13-16. DOI: 10.1109/L-Ca.2013.1  0.373
2013 Jeon Y, Jung E, Min H, Chung EY, Yoon S. GPU-based acceleration of an RNA tertiary structure prediction algorithm. Computers in Biology and Medicine. 43: 1011-22. PMID 23816173 DOI: 10.1016/J.Compbiomed.2013.05.007  0.527
2013 Bang K, Kim DG, Park SH, Chung EY, Lee HJ. Application-aware design parameter exploration of NAND flash memory Journal of Semiconductor Technology and Science. 13: 291-302. DOI: 10.5573/Jsts.2013.13.4.291  0.345
2013 Bang K, Park S, Lee H, Chung E. A Cache buffer and Read Request-aware Request Scheduling Method for NAND flash-based Solid-state Disks Journal of the Institute of Electronics and Information Engineers. 50: 143-150. DOI: 10.5573/Ieek.2013.50.8.143  0.398
2013 Bang K, Park S, Lee H, Chung E. Flash Translation Layer for Heterogeneous NAND Flash-based Storage Devices Based on Access Patterns of Logical Blocks Journal of the Institute of Electronics Engineers of Korea. 50: 94-101. DOI: 10.5573/Ieek.2013.50.5.094  0.377
2013 Jun M, Chung E. On-Chip Crossbar Network Topology Synthesis using Mixed Integer Linear Programming Journal of the Institute of Electronics Engineers of Korea. 50: 166-173. DOI: 10.5573/Ieek.2013.50.1.166  0.313
2013 Lee HJ, Kim SC, Chung EY. A low-power packet memory architecture with a latency-aware packet mapping method Ieice Transactions On Information and Systems. 963-966. DOI: 10.1587/Transinf.E96.D.963  0.385
2013 Bang K, Im KI, Kim DG, Park SH, Chung EY. Power failure protection scheme for reliable high-performance solid state disks Ieice Transactions On Information and Systems. 1078-1085. DOI: 10.1587/Transinf.E96.D.1078  0.378
2013 Won S, Chung EY, Kim D, Chung J, Han B, Lee H. Page overwritingmethod for performance improvement of NAND flash memories Ieice Electronics Express. 10. DOI: 10.1587/Elex.10.20130039  0.326
2012 Lee HJ, Cho WC, Chung EY. Analytical memory bandwidth model for many-core processor based systems Ieice Electronics Express. 9: 1461-1466. DOI: 10.1587/Elex.9.1461  0.38
2012 Lee JB, Kim MJ, Yoon S, Chung EY. Application-support particle filter for dynamic voltage scaling of multimedia applications Ieee Transactions On Computers. 61: 1256-1269. DOI: 10.1109/Tc.2011.148  0.541
2012 Jun M, Woo D, Chung EY. Partial connection-aware topology synthesis for on-chip cascaded crossbar network Ieee Transactions On Computers. 61: 73-86. DOI: 10.1109/Tc.2010.211  0.343
2010 Kim D, Bang K, Ha SH, Yoon S, Chung EY. Architecture exploration of high-performance pcs with a solid-state disk Ieee Transactions On Computers. 59: 878-890. DOI: 10.1109/Tc.2010.66  0.55
2010 Jun M, Chung EY. Design of on-chip crossbar network topology using chained edge partitioning Computer Journal. 53: 904-917. DOI: 10.1093/Comjnl/Bxq020  0.314
2009 Kim J, Yu S, Shim B, Kim H, Min H, Chung EY, Das R, Yoon S. A robust peak detection method for RNA structure inference by high-throughput contact mapping. Bioinformatics (Oxford, England). 25: 1137-44. PMID 19246511 DOI: 10.1093/Bioinformatics/Btp110  0.536
2009 Kim D, Bang K, Ha SH, Park C, Chung SW, Chung EY. Solid-State disk with Double Data Rate DRAM interface for high-performance PCS Ieice Transactions On Information and Systems. 727-731. DOI: 10.1587/Transinf.E92.D.727  0.37
2009 Roh JH, Jun M, Bang K, Chung EY. Jitter-conscious bus arbitration scheme for real-time systems Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 643-647. DOI: 10.1587/Transfun.E92.A.643  0.344
2009 Lee T, Kim SJ, Chung EY, Yoon S. K-maximin clustering: A maximin correlation approach to partition-based clustering Ieice Electronics Express. 6: 1205-1211. DOI: 10.1587/Elex.6.1205  0.488
2009 Park SH, Ha SH, Bang K, Chung EY. Design and analysis of flash translation layers for multi-channel NAND flash-based storage devices Ieee Transactions On Consumer Electronics. 55: 1392-1400. DOI: 10.1109/Tce.2009.5278005  0.364
2009 Bang SY, Bang K, Yoon S, Chung EY. Run-time adaptive workload estimation for dynamic voltage scaling Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1334-1347. DOI: 10.1109/Tcad.2009.2024706  0.55
2009 Kim MJ, Chung EY, Yoon S. High-speed post-layout logic simulation using quasi-static clock event evaluation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1274-1278. DOI: 10.1109/Tcad.2009.2020716  0.529
2009 Jun M, Yoo S, Chung EY. Topology synthesis of cascaded crossbar switches Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 926-930. DOI: 10.1109/Tcad.2009.2017079  0.351
2009 Won SK, Ha SH, Chung EY. Fast performance analysis of NAND flash-based storage device Electronics Letters. 45: 1219-1221. DOI: 10.1049/El.2009.2166  0.388
2008 Lee HJ, Chung EY. Scalable QoS-aware memory controller for high-bandwidth packet memory Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 289-301. DOI: 10.1109/Tvlsi.2007.915367  0.384
2008 Joo Y, Choi Y, Park J, Park C, Chung SW, Chung EY, Chang N. Energy and performance optimization of demand paging with OneNAND flash Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1969-1982. DOI: 10.1109/Tcad.2008.2006081  0.393
2008 Shin SH, Chung SW, Chung EY, Jhon CS. Adopting the drowsy technique for instruction caches: A soft error perspective Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 1772-1779. DOI: 10.1093/Ietfec/E91-A.7.1772  0.3
2008 Bang K, Bang SY, Chung EY. Extended MPEG video format for efficient dynamic voltage scaling Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 1283-1287. DOI: 10.1093/Ietfec/E91-A.5.1283  0.347
2007 Yoon S, Ebert JC, Chung EY, De Micheli G, Altman RB. Clustering protein environments for function prediction: finding PROSITE motifs in 3D. Bmc Bioinformatics. 8: S10. PMID 17570144 DOI: 10.1186/1471-2105-8-S4-S10  0.64
2007 Jun M, Bang K, Lee HJ, Chung EY. Latency-aware bus arbitration for real-time embedded systems Ieice Transactions On Information and Systems. 676-679. DOI: 10.1093/Ietisy/E90-D.3.676  0.392
2007 Chung EY, Lee HJ, Chung SW. Scenario-aware bus functional modeling for architecture-level performance analysis Ieice Transactions On Fundamentals of Electronics, Communications and Computer Sciences. 875-878. DOI: 10.1093/Ietfec/E90-A.4.875  0.351
2006 Joo Y, Choi Y, Park C, Chung SW, Chung EY, Chang N. Demand paging for OneNANDâ„¢ Flash eXecute-in-place Codes+Isss 2006: Proceedings of the 4th International Conference On Hardware Software Codesign and System Synthesis. 229-234. DOI: 10.1145/1176254.1176310  0.326
2006 Son CI, Yoon S, Chung SW, Park CI, Chung EY. Variability-insensitive scheme for NAND flash memory interfaces Electronics Letters. 42: 1335-1337. DOI: 10.1049/El:20062239  0.492
2002 Chung EY, Benini L, DeMicheli G, Luculli G, Carilli M. Value-sensitive automatic code specialization for embedded software Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 1051-1067. DOI: 10.1109/Tcad.2002.801096  0.304
2002 Chung E, Benini L, Bogliolo A, Lu Y, Micheli GD. Dynamic power management for nonstationary service requests Ieee Transactions On Computers. 51: 1345-1361. DOI: 10.1109/Tc.2002.1047758  0.644
Show low-probability matches.