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Jae-Joon Kim, Ph.D. - Publications

Affiliations: 
2004 Purdue University, West Lafayette, IN, United States 
Area:
Electronics and Electrical Engineering
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33 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Koo J, Kim J, Ryu S, Kim C, Kim J. Area-efficient Transposable Crossbar Synapse Memory Using 6T SRAM Bit Cell for Fast Online Learning of Neuromorphic Processors Journal of Semiconductor Technology and Science. 20: 195-203. DOI: 10.5573/Jsts.2020.20.2.195  0.302
2019 Yoo H, Park H, Yoo S, On S, Seong H, Im SG, Kim JJ. Highly stacked 3D organic integrated circuits with via-hole-less multilevel metal interconnects. Nature Communications. 10: 2424. PMID 31160606 DOI: 10.1038/S41467-019-10412-9  0.429
2019 Yoo H, On S, Lee SB, Cho K, Kim JJ. Negative Transconductance Heterojunction Organic Transistors and their Application to Full-Swing Ternary Circuits. Advanced Materials (Deerfield Beach, Fla.). e1808265. PMID 31116897 DOI: 10.1002/Adma.201808265  0.427
2019 Yin S, Seo J, Kim Y, Han X, Barnaby H, Yu S, Luo Y, He W, Sun X, Kim J. Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning Ieee Micro. 39: 54-63. DOI: 10.1109/Mm.2019.2943047  0.455
2019 Yoo H, On S, Lee SB, Cho K, Kim J. Heterojunction Transistors: Negative Transconductance Heterojunction Organic Transistors and their Application to Full‐Swing Ternary Circuits (Adv. Mater. 29/2019) Advanced Materials. 31: 1970206. DOI: 10.1002/Adma.201970206  0.403
2018 Kim J, Koo J, Kim T, Kim JJ. Efficient Synapse Memory Structure for Reconfigurable Digital Neuromorphic Hardware. Frontiers in Neuroscience. 12: 829. PMID 30515074 DOI: 10.3389/Fnins.2018.00829  0.369
2018 Yoo H, Hong S, On S, Ahn H, Lee HK, Hong YK, Kim S, Kim JJ. Chemical Doping Effects in Multilayer MoS2 and its Application in Complementary Inverter. Acs Applied Materials & Interfaces. PMID 29916693 DOI: 10.1021/Acsami.8B08773  0.401
2018 Sung C, Lim S, Kim H, Kim T, Moon K, Song J, Kim JJ, Hwang H. Effect of Conductance Linearity and Multi-level Cell Characteristics of TaOx-based Synapse Device on Pattern Recognition Accuracy of Neuromorphic System. Nanotechnology. PMID 29328054 DOI: 10.1088/1361-6528/Aaa733  0.376
2018 Lim S, Sung C, Kim H, Kim T, Song J, Kim J, Hwang H. Improved Synapse Device With MLC and Conductance Linearity Using Quantized Conduction for Neuromorphic Systems Ieee Electron Device Letters. 39: 312-315. DOI: 10.1109/Led.2018.2789425  0.339
2018 Yoo H, Nakano M, On S, Ahn H, Lee H, Takimiya K, Kim J. Air-stable and balanced split-gate organic transistors Organic Electronics. 63: 200-206. DOI: 10.1016/J.Orgel.2018.09.022  0.333
2017 Yoo H, Ghittorelli M, Lee DK, Smits ECP, Gelinck GH, Ahn H, Lee HK, Torricelli F, Kim JJ. Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors. Scientific Reports. 7: 5015. PMID 28694528 DOI: 10.1038/S41598-017-04933-W  0.346
2017 Kim T, Kim H, Kim J, Kim J. Input Voltage Mapping Optimized for Resistive Memory-Based Deep Neural Network Hardware Ieee Electron Device Letters. 38: 1228-1231. DOI: 10.1109/Led.2017.2730959  0.359
2016 Kwon J, Kyung S, Yoon S, Kim JJ, Jung S. Solution-Processed Vertically Stacked Complementary Organic Circuits with Inkjet-Printed Routing. Advanced Science (Weinheim, Baden-Wurttemberg, Germany). 3: 1500439. PMID 27812468 DOI: 10.1002/Advs.201500439  0.441
2016 Yoo H, Ghittorelli M, Smits EC, Gelinck GH, Lee HK, Torricelli F, Kim JJ. Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors. Scientific Reports. 6: 35585. PMID 27762321 DOI: 10.1038/srep35585  0.326
2016 Kwon J, Kyung S, Yoon S, Kim J, Jung S. Integrated Circuits: Solution-Processed Vertically Stacked Complementary Organic Circuits with Inkjet-Printed Routing (Adv. Sci. 5/2016) Advanced Science. 3. DOI: 10.1002/Advs.201670024  0.358
2016 Yoo H, Smits ECP, Breemen AJJMv, Steen JPJvd, Torricelli F, Ghittorelli M, Lee J, Gelinck GH, Kim J. Charge Injection: Asymmetric Split‐Gate Ambipolar Transistor and Its Circuit Application to Complementary Inverter (Adv. Mater. Technol. 4/2016) Advanced Materials and Technologies. 1. DOI: 10.1002/Admt.201670017  0.368
2015 Shin I, Kim JJ, Lin YS, Shin Y. One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2409118  0.312
2015 Shin I, Kim JJ, Shin Y. Aggressive voltage scaling through fast correction of multiple errors with seamless pipeline operation Ieee Transactions On Circuits and Systems I: Regular Papers. 62: 468-477. DOI: 10.1109/Tcsi.2014.2364691  0.351
2015 Yoo H, Choi HH, Shin TJ, Rim T, Cho K, Jung S, Kim J. Self‐Assembled, Millimeter‐Sized TIPS‐Pentacene Spherulites Grown on Partially Crosslinked Polymer Gate Dielectric Advanced Functional Materials. 25: 3658-3665. DOI: 10.1002/Adfm.201501381  0.3
2013 Ghosh A, Rao RM, Kim JJ, Chuang CT, Brown RB. Slew-rate monitoring circuit for on-chip process variation detection Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 1683-1692. DOI: 10.1109/Tvlsi.2012.2218838  0.447
2011 Chang IJ, Kim J, Kim K, Roy K. Robust Level Converter for Sub-Threshold/Super-Threshold Operation:100 mV to 2.5 V Ieee Transactions On Very Large Scale Integration Systems. 19: 1429-1437. DOI: 10.1109/Tvlsi.2010.2051240  0.714
2011 Mukhopadhyay S, Rao RM, Kim JJ, Chuang CT. SRAM write-ability improvement with transient negative bit-line voltage Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 24-32. DOI: 10.1109/Tvlsi.2009.2029114  0.636
2010 Mojumder NN, Mukhopadhyay S, Kim JJ, Chuang CT, Roy K. Self-repairing SRAM using on-chip detection and compensation Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 75-84. DOI: 10.1109/Tvlsi.2008.2008808  0.704
2009 Kim JJ, Bansal A, Rao R, Lo SH, Chuang CT. Relaxing conflict between read stability and writability in 6T SRAM cell using asymmetric transistors Ieee Electron Device Letters. 30: 852-854. DOI: 10.1109/Led.2009.2024014  0.598
2009 Rao R, Jenkins KA, Kim JJ. A local random variability detector with complete digital on-chip measurement circuitry Ieee Journal of Solid-State Circuits. 44: 2616-2623. DOI: 10.1109/Jssc.2009.2025342  0.434
2009 Chang IJ, Kim J, Park SP, Roy K. A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS Ieee Journal of Solid-State Circuits. 44: 650-658. DOI: 10.1109/Jssc.2008.2011972  0.717
2009 Bansal A, Rao R, Kim JJ, Zafar S, Stathis JH, Chuang CT. Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability Microelectronics Reliability. 49: 642-649. DOI: 10.1016/J.Microrel.2009.03.016  0.576
2008 Bansal A, Kim J, Kim K, Mukhopadhyay S, Chuang C, Roy K. Optimal Dual-$V_{T}$ Design in Sub-100-nm PD/SOI and Double-Gate Technologies Ieee Transactions On Electron Devices. 55: 1161-1169. DOI: 10.1109/Ted.2008.918426  0.72
2007 Mukhopadhyay S, Kim K, Kim J, Lo S, Joshi RV, Chuang C, Roy K. Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices Microelectronics Journal. 38: 931-941. DOI: 10.1016/J.Mejo.2006.03.010  0.625
2006 Kim J, Roy K. A leakage-tolerant low-swing circuit style in partially depleted silicon-on-insulator CMOS technologies Ieee Transactions On Very Large Scale Integration Systems. 14: 549-552. DOI: 10.1109/Tvlsi.2006.876110  0.578
2005 Kim CH, Kim J, Mukhopadhyay S, Roy K. A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations Ieee Transactions On Very Large Scale Integration Systems. 13: 349-357. DOI: 10.1109/Tvlsi.2004.842903  0.673
2004 Kim J, Roy K. Double gate-MOSFET subthreshold circuit for ultralow power applications Ieee Transactions On Electron Devices. 51: 1468-1474. DOI: 10.1109/Ted.2004.833965  0.571
2003 Plouchart J, Zamdmer N, Kim J, Sherony M, Tan Y, Ray A, Talbi M, Wagner LF, Wu K, Lustig NE, Narasimha S, O'Neil P, Phan N, Rohn M, Strom J, et al. Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits Ibm Journal of Research and Development. 47: 611-629. DOI: 10.1147/Rd.475.0611  0.484
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