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Xiang Hu, Ph.D. - Publications

Affiliations: 
2012 Electrical Engineering (Electronic Circuits and Systems) University of California, San Diego, La Jolla, CA 
Area:
Electronics and Electrical Engineering
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8 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2014 Hu X, Du P, Weng SH, Cheng CK. Worst case noise prediction with nonzero current transition times for power grid planning Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 607-620. DOI: 10.1109/Tvlsi.2013.2252210  0.617
2013 Hu X, Du P, Buckwalter JF, Cheng CK. Modeling and analysis of power distribution networks in 3-D ICs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 354-366. DOI: 10.1109/Tvlsi.2012.2183904  0.562
2012 Wang Y, Hu X, Cheng C, Pang GKH, Wong N. Corrigendum to “A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints” [Jan 12 109-120] Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 452-452. DOI: 10.1109/Tcad.2012.2186340  0.493
2012 Wang Y, Hu X, Cheng C, Pang GKH, Wong N. A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 109-120. DOI: 10.1109/Tcad.2011.2167328  0.529
2011 Zhang Y, Hu X, Deutsch A, Engin AE, Buckwalter JF, Cheng CK. Prediction and comparison of high-performance on-chip global interconnection Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1154-1166. DOI: 10.1109/Tvlsi.2010.2047415  0.502
2010 Zhang W, Zhang L, Shayan A, Yu W, Hu X, Zhu Z, Engin E, Cheng CK. On-chip power network optimization with decoupling capacitors and controlled-ESRs Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 119-124. DOI: 10.1109/ASPDAC.2010.5419910  0.44
2009 Zhang Y, Hu X, Deutsch A, Engin AE, Buckwalter JF, Cheng CK. Prediction of high-performance on-chip global interconnection International Workshop On System Level Interconnect Prediction, Slip. 61-68. DOI: 10.1145/1572471.1572482  0.462
2009 Zhang W, Yu W, Hu X, Zhang L, Shi R, Peng H, Zhu Z, Chua-Eoan L, Murgai R, Shibuya T, Ito N, Cheng C. Efficient Power Network Analysis Considering Multidomain Clock Gating Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1348-1358. DOI: 10.1109/Tcad.2009.2024711  0.604
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