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Sangyeun Cho, Ph.D. - Publications

Affiliations: 
2002 University of Minnesota, Twin Cities, Minneapolis, MN 
Area:
Computer Science
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15 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2017 Baek S, Cho S, Choi J. Don't make cache too complex: A simple probability-based cache management scheme for SSDs. Plos One. 12: e0174375. PMID 28358897 DOI: 10.1371/Journal.Pone.0174375  0.37
2016 Maddah R, Cho S, Melhem R. Symbol Shifting: Tolerating More Faults in PCM Blocks Ieee Transactions On Computers. 65: 2270-2283. DOI: 10.1109/Tc.2015.2479593  0.307
2016 Kim S, Oh H, Park C, Cho S, Lee SW, Moon B. In-storage processing of database scans and joins Information Sciences. 327: 183-200. DOI: 10.1016/J.Ins.2015.07.056  0.325
2015 Maddah R, Melhem R, Cho S. RDIS: Tolerating many stuck-at faults in resistive memory Ieee Transactions On Computers. 64: 847-861. DOI: 10.1109/Tc.2013.2295825  0.325
2014 Rahman M, Childers BR, Cho S. COMeT+: Continuous online memory testing with multi-threading extension Ieee Transactions On Computers. 63: 1668-1681. DOI: 10.1109/Tc.2013.65  0.336
2014 Baek S, Cho S, Melhem R. Refresh now and then Ieee Transactions On Computers. 63: 3114-3126. DOI: 10.1109/Tc.2013.164  0.329
2013 Maddah R, Cho S, Melhem R. Data dependent sparing to manage better-than-bad blocks Ieee Computer Architecture Letters. 12: 43-46. DOI: 10.1109/L-Ca.2012.20  0.304
2013 Lee K, Cho S. Accurately modeling superscalar processor performance with reduced trace Journal of Parallel and Distributed Computing. 73: 509-521. DOI: 10.1016/J.Jpdc.2012.12.002  0.305
2011 Lee H, Cho S, Childers BR. DEFCAM: A design and evaluation framework for defect-tolerant cache memories Transactions On Architecture and Code Optimization. 8. DOI: 10.1145/2019608.2019616  0.321
2011 Hanna M, Demetriades S, Cho S, Melhem R. Advanced hashing schemes for packet forwarding using set associative memory architectures Journal of Parallel and Distributed Computing. 71: 1-15. DOI: 10.1016/J.Jpdc.2010.10.006  0.337
2010 Lee H, Cho S, Childers BR. PERFECTORY: A fault-tolerant directory memory architecture Ieee Transactions On Computers. 59: 638-650. DOI: 10.1109/Tc.2009.138  0.327
2010 Hammoud M, Cho S, Melhem R. A dynamic pressure-aware associative placement strategy for large scale chip multiprocessors Ieee Computer Architecture Letters. 9: 29-32. DOI: 10.1109/L-Ca.2010.7  0.327
2001 Cho S, Yew PC, Lee G. A high-bandwidth memory pipeline for wide issue processors Ieee Transactions On Computers. 50: 709-723. DOI: 10.1109/12.936237  0.54
1999 Lee G, Quattlebaum BW, Cho S, Kinney LL. Design of a bus-based shared-memory multiprocessor DICE Microprocessors and Microsystems. 22: 403-411. DOI: 10.1016/S0141-9331(98)00097-0  0.342
1999 Cho S, Kong J, Lee G. Coherence and Replacement Protocol of DICE —A Bus-Based COMA Multiprocessor Journal of Parallel and Distributed Computing. 57: 14-32. DOI: 10.1006/Jpdc.1998.1524  0.36
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