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Wuxi Li - Publications

Affiliations: 
2019 University of Texas at Austin, Austin, Texas, U.S.A. 
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6 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Lin Y, Jiang Z, Gu J, Li W, Dhar S, Ren H, Khailany B, Pan DZ. DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2020.3003843  0.612
2020 Lin Y, Li W, Gu J, Ren H, Khailany B, Pan DZ. ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2020.2971531  0.755
2019 Li W, Pan DZ. A New Paradigm for FPGA Placement Without Explicit Packing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 2113-2126. DOI: 10.1109/Tcad.2018.2877017  0.506
2019 Li M, Yu B, Lin Y, Xu X, Li W, Pan DZ. A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 1585-1598. DOI: 10.1109/Tcad.2018.2859402  0.7
2018 Li W, Lin Y, Li M, Dhar S, Pan DZ. UTPlaceF 2.0 Acm Transactions On Design Automation of Electronic Systems. 23: 1-23. DOI: 10.1145/3174849  0.657
2018 Li W, Dhar S, Pan DZ. UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 869-882. DOI: 10.1109/Tcad.2017.2729349  0.725
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