Igor L. Markov, Ph.D.

Affiliations: 
2001 University of California, Los Angeles, Los Angeles, CA 
Area:
Computer Science, Electronics and Electrical Engineering, Mathematics
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"Igor Markov"

Parents

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Andrew B. Kahng grad student 2001 UCLA
 (Top-down timing -driven placement with direct minimization of maximal signal delay.)
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Publications

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Kahng AB, Lienig J, Markov IL, et al. (2011) VLSI physical design: From graph partitioning to timing closure Vlsi Physical Design: From Graph Partitioning to Timing Closure. 1-310
Kahng AB, Markov IL, Reda S. (2004) Boosting: Min-cut placement with improved signal delay Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 2: 1098-1103
Kahng AB, Markov IL, Reda S. (2004) On legalization of row-based placements Proceedings of the Acm Great Lakes Symposium On Vlsi. 214-219
Caldwell AE, Kahng AB, Markov IL. (2003) Hierarchical whitespace allocation in top-down placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1550-1556
Kahng AB, Mantik S, Markov IL. (2002) Min-max placement for large-scale timing optimization Proceedings of the International Symposium On Physical Design. 143-148
Caldwell AE, Markov IL, Kahng AB. (2002) Toward CAD-IP reuse: A web bookshelf of fundamental algorithms Ieee Design and Test of Computers. 19: 72-81
Baldick R, Kahng AB, Kennings A, et al. (2001) Efficient optimization by modifying the objective function: Applications to timing-driven VLSI layout Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 48: 947-956
Kahng AB, Lach J, Mangione-Smith WH, et al. (2001) Constraint-based watermarking techniques for design IP protection Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1236-1252
Caldwell AE, Kahng AB, Markov IL. (2000) Improved algorithms for hypergraph bipartitioning Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 661-666
Caldwell AE, Kahng AB, Markov IL. (2000) Optimal partitioners and end-case placers for standard-cell layout Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 1304-1313
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