Stefanus Mantik, Ph.D.

Affiliations: 
2003 University of California, Los Angeles, Los Angeles, CA 
Area:
Computer Science
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"Stefanus Mantik"

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Andrew B. Kahng grad student 2003 UCLA
 (METRICS: Automatic data collection infrastructure for continuous IC design process improvement.)
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Publications

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Caldwell AE, Choi HJ, Kahng AB, et al. (2004) Effective iterative techniques for fingerprinting design IP Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 208-215
Gupta P, Kahng AB, Mantik S. (2003) A proposal for routing-based timing-driven scan chain ordering Proceedings - International Symposium On Quality Electronic Design, Isqed. 2003: 339-343
Gupta P, Kahng AB, Mantik S. (2003) Routing-aware scan chain ordering Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2003: 857-862
Kahng AB, Mantik S. (2002) Measurement of inherent noise in EDA tools Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 206-211
Kahng AB, Mantik S, Markov IL. (2002) Min-max placement for large-scale timing optimization Proceedings of the International Symposium On Physical Design. 143-148
Kahng AB, Mantik S. (2001) A system for automatic recording and prediction of design quality metrics Proceedings - International Symposium On Quality Electronic Design, Isqed. 2001: 81-86
Kahng AB, Lach J, Mangione-Smith WH, et al. (2001) Constraint-based watermarking techniques for design IP protection Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1236-1252
Kahng AB, Mantik S, Stroobandt D. (2001) Toward accurate models of achievable routing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 648-659
Boese KD, Kahng AB, Mantik S. (2001) On the relevance of wire load models 2001 International Workshop On System-Level Interconnect Prediction (Slip 2001). 91-98
Caldwell AE, Kahng AB, Mantik S, et al. (1999) On wirelength estimations for row-based placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1265-1278
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