Vidyasagar Nookala, Ph.D.

Affiliations: 
2007 University of Minnesota, Twin Cities, Minneapolis, MN 
Area:
Electronics and Electrical Engineering
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"Vidyasagar Nookala"

Parents

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David J. Lilja grad student 2007 UMN
 (Physically-aware synthesis and microarchitecture design.)
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Publications

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Nookala V, Lilja DJ, Sapatnekar SS. (2006) Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis Proceedings of the International Symposium On Low Power Electronics and Design. 2006: 298-303
Nookala V, Chen Y, Lilja DJ, et al. (2006) Comparing simulation techniques for microarchitecture-aware floorplanning Ispass 2006: Ieee International Symposium On Performance Analysis of Systems and Software, 2006. 2006: 80-88
Nookala V, Sapatnekar SS. (2005) Designing optimized pipelined global interconnects: Algorithms and methodology impact Proceedings - Ieee International Symposium On Circuits and Systems. 608-611
Singh J, Nookala V, Luo ZQ, et al. (2005) Robust gate sizing by geometric programming Proceedings - Design Automation Conference. 315-320
Nookala V, Chen Y, Lilja DJ, et al. (2005) Microarchitecture-aware floorplanning using a statistical design of experiments approach Proceedings - Design Automation Conference. 579-584
Nookala V, Sapatnekar SS. (2004) A method for correcting the functionality of a wire-pipelined circuit Proceedings - Design Automation Conference. 570-575
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