Guillermo J. Serrano, Ph.D.
Affiliations: | 2007 | Georgia Institute of Technology, Atlanta, GA |
Area:
Electronics and Electrical EngineeringGoogle:
"Guillermo Serrano"Parents
Sign in to add mentorJennifer Hasler | grad student | 2007 | Georgia Tech (BME Tree) | |
(High performance analog circuit design using floating-gate techniques.) |
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Publications
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Román HX, Serrano GJ. (2015) A 1μA linear regulator with programmable NMOS pass device 2015 Ieee Dallas Circuits and Systems Conference: Enabling Technologies For a Connected World, Dcas 2015 |
Román HX, Serrano GJ. (2013) A 1μA bandgap-less programmable voltage regulator Midwest Symposium On Circuits and Systems. 5-8 |
Mendez-Delgado E, Serrano GJ. (2011) A 300mV Low-voltage start-up circuit for energy harvesting systems Proceedings - Ieee International Symposium On Circuits and Systems. 829-832 |
Román HX, Serrano GJ. (2010) A system architecture for automated charge modification of analog memories Midwest Symposium On Circuits and Systems. 1069-1072 |
Serrano G, Hasler P. (2008) A precision low-TC wide-range CMOS current reference Ieee Journal of Solid-State Circuits. 43: 558-565 |
Chawla R, Adil F, Serrano G, et al. (2007) Programmable |
Srinivasan V, Serrano GJ, Gray J, et al. (2007) A precision CMOS amplifier using floating-gate transistors for offset cancellation Ieee Journal of Solid-State Circuits. 42: 280-291 |
Bandyopadhyay A, Serrano GJ, Hasler P. (2006) Adaptive algorithm using hot-electron injection for programming analog computational memory elements within 0.2% of accuracy over 3.5 decades Ieee Journal of Solid-State Circuits. 41: 2107-2114 |
Srinivasan V, Serrano GJ, Gray J, et al. (2005) A precision CMOS amplifier using floating-gates for offset cancellation Proceedings of the Custom Integrated Circuits Conference. 2005: 734-737 |