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Jennifer Hasler - Publications

Affiliations: 
1992-1997 Computation and Neural Systems California Institute of Technology, Pasadena, CA 
 1997- Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA 
Area:
Biomedical Engineering, Electronics and Electrical Engineering, Artificial Intelligence
Website:
http://hasler.ece.gatech.edu
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38 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Shah S, Toreyin H, Gungor CB, Hasler J. A Real-Time Vital-Sign Monitoring in the Physical Domain on a Mixed-Signal Reconfigurable Platform. Ieee Transactions On Biomedical Circuits and Systems. PMID 31670678 DOI: 10.1109/Tbcas.2019.2949778  0.386
2019 Hasler J. Analog Architecture Complexity Theory Empowering Ultra-Low Power Configurable Analog and Mixed Mode SoC Systems Journal of Low Power Electronics and Applications. 9: 4. DOI: 10.3390/Jlpea9010004  0.419
2018 Thakur CS, Molin JL, Cauwenberghs G, Indiveri G, Kumar K, Qiao N, Schemmel J, Wang R, Chicca E, Hasler JO, Seo JS, Yu S, Cao Y, van Schaik A, Etienne-Cummings R. Corrigendum: Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain. Frontiers in Neuroscience. 12: 991. PMID 30666180 DOI: 10.3389/Fnins.2018.00991  0.476
2018 Natarajan A, Hasler J. Hodgkin-Huxley Neuron and FPAA Dynamics. Ieee Transactions On Biomedical Circuits and Systems. PMID 30010587 DOI: 10.1109/Tbcas.2018.2837055  0.372
2018 Hasler J, Natarajan A, Kim S. Enabling Energy-Efficient Physical Computing through Analog Abstraction and IP Reuse Journal of Low Power Electronics and Applications. 8: 47. DOI: 10.3390/Jlpea8040047  0.437
2018 Hasler J, Shah S. Security Implications for Ultra-Low Power Configurable SoC FPAA Embedded Systems Journal of Low Power Electronics and Applications. 8: 17. DOI: 10.3390/Jlpea8020017  0.322
2018 Shah S, Toreyin H, Hasler J, Natarajan A. Temperature Sensitivity and Compensation on a Reconfigurable Platform Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 604-607. DOI: 10.1109/Tvlsi.2017.2773399  0.389
2018 Shah S, Hasler J. SoC FPAA Hardware Implementation of a VMM+WTA Embedded Learning Classifier Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 8: 28-37. DOI: 10.1109/Jetcas.2017.2777784  0.405
2018 Hasler J, Shah S. VMM + WTA Embedded Classifiers Learning Algorithm Implementable on SoC FPAA Devices Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 8: 65-76. DOI: 10.1109/Jetcas.2017.2771392  0.322
2017 Shah S, Toreyin H, Hasler J, Natarajan A. Models and Techniques for Temperature Robust Systems on a Reconfigurable Platform Journal of Low Power Electronics and Applications. 7: 21. DOI: 10.3390/Jlpea7030021  0.383
2017 Hasler J. Starting Framework for Analog Numerical Analysis for Energy-Efficient Computing Journal of Low Power Electronics and Applications. 7: 17. DOI: 10.3390/Jlpea7030017  0.36
2017 Kim S, Shah S, Hasler J. Calibration of Floating-Gate SoC FPAA System Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 25: 2649-2657. DOI: 10.1109/Tvlsi.2017.2710020  0.403
2017 Koziol S, Wunderlich R, Hasler J, Stilman M. Single-Objective Path Planning for Autonomous Robots Using Reconfigurable Analog VLSI Ieee Transactions On Systems, Man, and Cybernetics: Systems. 47: 1301-1314. DOI: 10.1109/Tsmc.2016.2573833  0.391
2017 Shah S, Hasler J. Tuning of Multiple Parameters With a BIST System Ieee Transactions On Circuits and Systems I: Regular Papers. 64: 1772-1780. DOI: 10.1109/Tcsi.2017.2652123  0.36
2017 Wang T, Peng S, Hasler J. A compact low-power algorithmic A/D converter implemented on a large scale FPAA chip Analog Integrated Circuits and Signal Processing. 94: 65-74. DOI: 10.1007/S10470-017-1084-2  0.62
2017 Natarajan A, Hasler J. Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA Analog Integrated Circuits and Signal Processing. 91: 119-130. DOI: 10.1007/S10470-016-0914-Y  0.404
2016 Hasler J, Shah S, Kim S, Lal IK, Collins M. Remote system setup using large-scale field programmable analog arrays (FPAA) to enabling wide accessibility of configurable devices Journal of Low Power Electronics and Applications. 6. DOI: 10.3390/Jlpea6030014  0.407
2016 Hasler J, Kim S, Adil F. Scaling Floating-Gate Devices Predicting Behavior for Programmable and Configurable Circuits and Systems Journal of Low Power Electronics and Applications. 6: 13. DOI: 10.3390/Jlpea6030013  0.396
2016 Collins M, Hasler J, George S. An open-source tool set enabling analog-digital-software co-design Journal of Low Power Electronics and Applications. 6. DOI: 10.3390/Jlpea6010003  0.361
2016 George S, Kim S, Shah S, Hasler J, Collins M, Adil F, Wunderlich R, Nease S, Ramakrishnan S. A Programmable and Configurable Mixed-Mode FPAA SoC Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2504119  0.428
2016 Degnan B, Marr B, Hasler J. Assessing Trends in Performance per Watt for Signal Processing Applications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 24: 58-66. DOI: 10.1109/Tvlsi.2015.2392942  0.568
2015 Kim S, Hasler J, George S. Integrated Floating-Gate Programming Environment for System-Level ICs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2504118  0.352
2015 Laiho M, Hasler JO, Zhou J, Du C, Lu W, Lehtonen E, Poikonen JH. FPAA/Memristor Hybrid Computing Infrastructure Ieee Transactions On Circuits and Systems I: Regular Papers. 62: 906-915. DOI: 10.1109/Tcsi.2014.2386773  0.334
2014 Delbruck T, van Schaik A, Hasler J. Research topic: neuromorphic engineering systems and applications. A snapshot of neuromorphic systems engineering. Frontiers in Neuroscience. 8: 424. PMID 25565952 DOI: 10.3389/Fnins.2014.00424  0.541
2014 Marr B, Hasler J. Compiling probabilistic, bio-inspired circuits on a field programmable analog array. Frontiers in Neuroscience. 8: 86. PMID 24847199 DOI: 10.3389/Fnins.2014.00086  0.571
2014 Lani SW, Wasequr Rashid M, Hasler J, Sabra KG, Levent Degertekin F. Capacitive micromachined ultrasonic transducer arrays as tunable acoustic metamaterials. Applied Physics Letters. 104: 051914. PMID 24753623 DOI: 10.1063/1.4864635  0.341
2014 Gurun G, Tekes C, Zahorian J, Xu T, Satir S, Karaman M, Hasler J, Degertekin FL. Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging. Ieee Transactions On Ultrasonics, Ferroelectrics, and Frequency Control. 61: 239-50. PMID 24474131 DOI: 10.1109/Tuffc.2014.6722610  0.712
2014 Koziol S, Brink S, Hasler J. A neuromorphic approach to path planning using a reconfigurable neuron array IC Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 2724-2737. DOI: 10.1109/Tvlsi.2013.2297056  0.576
2014 Brink S, Hasler J, Wunderlich R. Adaptive floating-gate circuit enabled large-scale FPAA Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 2307-2315. DOI: 10.1109/Tvlsi.2013.2290305  0.621
2014 Schlottmann CR, Hasler J. High-level modeling of analog computational elements for signal processing applications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 1945-1953. DOI: 10.1109/Tvlsi.2013.2280718  0.42
2014 Ramakrishnan S, Hasler J. Vector-matrix multiply and winner-take-all as an analog classifier Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 353-361. DOI: 10.1109/Tvlsi.2013.2245351  0.347
2014 Ramakrishnan S, Basu A, Chiu LK, Hasler J, Anderson D, Brink S. Speech processing on a reconfigurable analog platform Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 430-433. DOI: 10.1109/Tvlsi.2013.2241089  0.58
2013 Ramakrishnan S, Wunderlich R, Hasler J, George S. Neuron array with plastic synapses and programmable dendrites. Ieee Transactions On Biomedical Circuits and Systems. 7: 631-42. PMID 24144669 DOI: 10.1109/Tbcas.2013.2282616  0.364
2013 Hasler J, Marr B. Finding a roadmap to achieve large neuromorphic hardware systems. Frontiers in Neuroscience. 7: 118. PMID 24058330 DOI: 10.3389/Fnins.2013.00118  0.567
2013 George S, Hasler J, Koziol S, Nease S, Ramakrishnan S. Low power dendritic computation for wordspotting Journal of Low Power Electronics and Applications. 3: 73-98. DOI: 10.3390/Jlpea3020073  0.342
2013 Tekes C, Zahorian J, Xu T, Rashid MW, Satir S, Gurun G, Karaman M, Hasler J, Degertekin FL. CMUT-based volumetric ultrasonic imaging array design for forward looking ICE and IVUS applications Progress in Biomedical Optics and Imaging - Proceedings of Spie. 8675. DOI: 10.1117/12.2007042  0.706
2013 Brink S, Hasler J, Wunderlich R. A large-scale FPAA enabling adaptive floating-gate circuits Midwest Symposium On Circuits and Systems. 285-288. DOI: 10.1109/MWSCAS.2013.6674641  0.326
2012 Tekes C, Gurun G, Rashid MW, Zahorian J, Xu T, Hasler J, Degertekin FL. 3-D real-time volumetric imaging using 20 MHz 1.5-mm diameter single-chip CMUT-on-CMOS array Ieee International Ultrasonics Symposium, Ius. DOI: 10.1109/ULTSYM.2012.0514  0.698
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