Andrew B. Kahng - Publications

Affiliations: 
University of California, Los Angeles, Los Angeles, CA 
Area:
Computer Science, Electronics and Electrical Engineering, Mathematics

246 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Han K, Kahng AB, Lee H. Scalable detailed placement legalization for complex sub-14nm constraints 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 867-873. DOI: 10.1109/ICCAD.2015.7372662  1
2016 Dobre S, Kahng AB, Li J. Mixed cell-height implementation for improved design quality in advanced nodes 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 854-860. DOI: 10.1109/ICCAD.2015.7372660  1
2016 Kahng AB, Luo M, Nam GJ, Nath S, Pan DZ, Robins G. Toward metrics of design automation research impact 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 263-270. DOI: 10.1109/ICCAD.2015.7372579  1
2016 Kahng AB, Koushanfar F. Evolving EDA beyond its E-roots: An overview 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 247-254. DOI: 10.1109/ICCAD.2015.7372577  1
2016 Alaghi A, Chan WTJ, Hayes JP, Kahng AB, Li J. Optimizing stochastic circuits for accuracy-energy tradeoffs 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 178-185. DOI: 10.1109/ICCAD.2015.7372568  1
2015 Kahng AB. New game, new goal posts: A recent history of timing closure Proceedings - Design Automation Conference. 2015. DOI: 10.1145/2744769.2747937  1
2015 Han K, Kahng AB, Lee H. Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router Proceedings - Design Automation Conference. 2015. DOI: 10.1145/2744769.2744839  1
2015 Escalante M, Kahng AB, Kishinevsky M, Ogras U, Samadi K. Multi-product floorplan and uncore design framework for chip multiprocessors International Workshop On System Level Interconnect Prediction, Slip. 2015. DOI: 10.1109/SLIP.2015.7171713  1
2015 Bang S, Han K, Kahng AB, Srinivas V. Clock clustering and IO optimization for 3D integration International Workshop On System Level Interconnect Prediction, Slip. 2015. DOI: 10.1109/SLIP.2015.7171709  1
2015 Kahng AB, Luo M, Nath S. SI for free: Machine learning of interconnect coupling delay and transition effects International Workshop On System Level Interconnect Prediction, Slip. 2015. DOI: 10.1109/SLIP.2015.7171706  1
2015 Kahng AB, Lin B, Nath S. ORION3.0: A comprehensive noc router estimation tool Ieee Embedded Systems Letters. 7: 41-45. DOI: 10.1109/LES.2015.2402197  1
2015 Chen Y, Kahng AB, Liu B, Wang W. Crosstalk-aware signal probability-based dynamic statistical timing analysis Proceedings - International Symposium On Quality Electronic Design, Isqed. 2015: 424-429. DOI: 10.1109/ISQED.2015.7085463  1
2015 Chan TB, Gupta P, Han K, Kagalwalla AA, Kahng AB, Sahouria E. Benchmarking of mask fracturing heuristics Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2015: 246-253. DOI: 10.1109/ICCAD.2014.7001359  1
2014 Kahng AB, Kang I. Co-optimization of memory BIST grouping, test scheduling, and logic placement Proceedings -Design, Automation and Test in Europe, Date. DOI: 10.7873/DATE2014.209  1
2014 Jerke G, Kahng AB. Mission profile aware IC design - A case study Proceedings -Design, Automation and Test in Europe, Date. DOI: 10.7873/DATE2014.077  1
2014 Kahng AB, Kang S, Li J. A new methodology for reduced cost of resilience Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 157-162. DOI: 10.1145/2591513.2591600  1
2014 Kahng AB, Lee H. Minimum implant area-aware gate sizing and placement Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 57-62. DOI: 10.1145/2591513.2591542  1
2014 Kahng AB. Lithography-induced limits to scaling of design quality Proceedings of Spie - the International Society For Optical Engineering. 9053. DOI: 10.1117/12.2047391  1
2014 Jouppi NP, Kahng AB, Muralimanohar N, Srinivas V. CACTI-IO: CACTI With OFF-chip Power-Area-Timing Models Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/TVLSI.2014.2334635  1
2014 Kahng AB. Toward holistic modeling, margining and tolerance of IC variability Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 284-289. DOI: 10.1109/ISVLSI.2014.118  1
2014 Chan TB, Kahng AB, Li J. NOLO: A no-loop, predictive useful skew methodology for improved timing in IC implementation Proceedings - International Symposium On Quality Electronic Design, Isqed. 504-509. DOI: 10.1109/ISQED.2014.6783368  1
2014 Kahng AB, Nath S. Optimal reliability-constrained overdrive frequency selection in multicore systems Proceedings - International Symposium On Quality Electronic Design, Isqed. 300-308. DOI: 10.1109/ISQED.2014.6783340  1
2014 Chan TB, Dobre S, Kahng AB. Improved signoff methodology with tightened BEOL corners 2014 32nd Ieee International Conference On Computer Design, Iccd 2014. 311-316. DOI: 10.1109/ICCD.2014.6974699  1
2014 Chan WTJ, Kahng AB, Nath S, Yamamoto I. The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap 2014 32nd Ieee International Conference On Computer Design, Iccd 2014. 153-160. DOI: 10.1109/ICCD.2014.6974675  1
2014 Carballo JA, Chan WTJ, Gargini PA, Kahng AB, Nath S. ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap 2014 32nd Ieee International Conference On Computer Design, Iccd 2014. 139-146. DOI: 10.1109/ICCD.2014.6974673  1
2013 Kahng AB. The ITRS design technology and system drivers roadmap: Process and status Proceedings - Design Automation Conference. DOI: 10.1145/2463209.2488776  1
2013 Chan TB, Kahng AB. Post-routing back-end-of-line layout optimization for improved time-dependent dielectric breakdown reliability Proceedings of Spie - the International Society For Optical Engineering. 8684. DOI: 10.1117/12.2011645  1
2013 Kahng AB, Kang S, Kumar R, Sartori J. Enhancing the efficiency of energy-constrained DVFS designs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 1769-1782. DOI: 10.1109/TVLSI.2012.2219084  1
2013 Kahng AB, Lin B, Nath S. High-dimensional metamodeling for prediction of clock tree synthesis outcomes International Workshop On System Level Interconnect Prediction, Slip. DOI: 10.1109/SLIP.2013.6681685  1
2013 Chan TB, Kahng AB, Li J. Toward quantifying the IC design value of interconnect technology improvements International Workshop On System Level Interconnect Prediction, Slip. DOI: 10.1109/SLIP.2013.6681680  1
2013 Chan TB, Kahng AB, Li J. Reliability-constrained die stacking order in 3DICs under manufacturing variability Proceedings - International Symposium On Quality Electronic Design, Isqed. 16-23. DOI: 10.1109/ISQED.2013.6523584  1
2013 Chan WTJ, Kahng AB, Kang S, Kumar R, Sartori J. Statistical analysis and modeling for error composition in approximate computation circuits 2013 Ieee 31st International Conference On Computer Design, Iccd 2013. 47-53. DOI: 10.1109/ICCD.2013.6657024  1
2013 Kahng AB, Kang I, Nath S. Incremental multiple-scan chain ordering for eco flip-flop insertion Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 705-712. DOI: 10.1109/ICCAD.2013.6691192  1
2013 Kahng AB, Kang S, Lee H, Markov IL, Thapar P. High-performance gate sizing with a signoff timer Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 450-457. DOI: 10.1109/ICCAD.2013.6691156  1
2013 Kahng AB, Kang S, Park B. Active-mode leakage reduction with data-retained power gating Proceedings -Design, Automation and Test in Europe, Date. 1209-1214.  1
2013 Kahng AB, Lin B, Nath S. Enhanced metamodeling techniques for high-dimensional IC design estimation problems Proceedings -Design, Automation and Test in Europe, Date. 1861-1866.  1
2012 Kahng AB, Kang S. Accuracy-configurable adder for approximate arithmetic designs Proceedings - Design Automation Conference. 820-825. DOI: 10.1145/2228360.2228509  1
2012 Kahng AB, Lin B, Nath S. Explicit modeling of control and data for improved NoC router estimation Proceedings - Design Automation Conference. 392-397. DOI: 10.1145/2228360.2228430  1
2012 Kahng AB, Kang S. Construction of realistic gate sizing benchmarks with known optimal solutions Proceedings of the International Symposium On Physical Design. 153-160. DOI: 10.1145/2160916.2160949  1
2012 Kahng AB, Li B, Peh LS, Samadi K. Orion 2.0: A power-area simulator for interconnection networks Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 191-196. DOI: 10.1109/TVLSI.2010.2091686  1
2012 Kahng AB, Kang S, Kumar R, Sartori J. Recovery-driven design: Exploiting error resilience in design of energy-efficient processors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 404-417. DOI: 10.1109/TCAD.2011.2172610  1
2012 Kahng AB. Predicting the future of information technology and society [The Road Ahead] Ieee Design and Test of Computers. 29: 101-102. DOI: 10.1109/MDT.2012.2228599  1
2012 Chan TB, Kahng AB. Improved path clustering for adaptive path-delay testing Proceedings - International Symposium On Quality Electronic Design, Isqed. 13-20. DOI: 10.1109/ISQED.2012.6187468  1
2012 Chan TB, Kahng AB. Tunable sensors for process-aware voltage scaling Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 7-14.  1
2011 Chan TB, Jeong K, Kahng AB. Performance and variability driven guidelines for BEOL layout decomposition with LELE double patterning Proceedings of Spie - the International Society For Optical Engineering. 8166. DOI: 10.1117/12.899553  1
2011 Jeong K, Kahng AB, Progler CJ. Cost-driven mask strategies considering parametric yield, defectivity, and production volume Journal of Micro/Nanolithography, Mems, and Moems. 10. DOI: 10.1117/1.3633246  1
2011 Kahng AB, Srinivas V. Mobile system considerations for SDRAM interface trends International Workshop On System Level Interconnect Prediction, Slip. DOI: 10.1109/SLIP.2011.6135437  1
2011 Jeong K, Kahng AB. Toward PDN resource estimation: A law of general power density International Workshop On System Level Interconnect Prediction, Slip. DOI: 10.1109/SLIP.2011.6135432  1
2011 Kahng AB, Srinivasan V. Big chips Ieee Micro. 31: 3-5. DOI: 10.1109/MM.2011.72  1
2011 Kahng AB. The future of signoff Ieee Design and Test of Computers. 28: 86-89. DOI: 10.1109/MDT.2011.66  1
2011 Kahng AB. Roads not taken Ieee Design and Test of Computers. 28: 74-75. DOI: 10.1109/MDT.2011.37  1
2011 Kahng AB. Product futures Ieee Design and Test of Computers. 28: 88-89. DOI: 10.1109/MDT.2011.130  1
2011 Kahng AB. Design for manufacturability: Then and now Ieee Design and Test of Computers. 28: 76-77. DOI: 10.1109/MDT.2011.12  1
2011 Kahng AB. Roadmapping power Ieee Design and Test of Computers. 28: 104-106. DOI: 10.1109/MDT.2011.115  1
2010 Kahng AB, Kang S, Kumar R, Sartori J. Recovery-driven design: A power minimization methodology for error-tolerant processor modules Proceedings - Design Automation Conference. 825-830. DOI: 10.1145/1837274.1837481  1
2010 Carloni LP, Kahng AB, Muddu SV, Pinto A, Samadi K, Sharma P. Accurate predictive interconnect modeling for system-level design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 679-684. DOI: 10.1109/TVLSI.2009.2014772  1
2010 Kahng AB. When is 3D 2B? Ieee Design and Test of Computers. 27: 70-71. DOI: 10.1109/MDT.2010.92  1
2010 Kahng AB. Scaling: More than Moore's law Ieee Design and Test of Computers. 27: 86-87. DOI: 10.1109/MDT.2010.71  1
2010 Jeong K, Kahng AB. Methodology from chaos in IC implementation Proceedings of the 11th International Symposium On Quality Electronic Design, Isqed 2010. 885-892. DOI: 10.1109/ISQED.2010.5450475  1
2010 Jeong K, Kahng AB, Kang S. Toward effective utilization of timing exceptions in design optimization Proceedings of the 11th International Symposium On Quality Electronic Design, Isqed 2010. 54-61. DOI: 10.1109/ISQED.2010.5450401  1
2010 Kahng AB, Lin B, Samadi K. Improved on-chip router analytical power and area modeling Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 241-246. DOI: 10.1109/ASPDAC.2010.5419887  1
2010 Kahng AB, Kang S, Kumar R, Sartori J. Slack redistribution for graceful degradation under voltage overscaling Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 825-831. DOI: 10.1109/ASPDAC.2010.5419690  1
2010 Kahng AB, Kang S, Kumar R, Sartori J. Designing a processor from the ground up to allow voltage/reliability tradeoffs Proceedings - International Symposium On High-Performance Computer Architecture 1
2009 Greenway RT, Hendel R, Jeong K, Kahng AB, Petersen JS, Rao Z, Smayling MC. Interference assisted lithography for patterning of 1D gridded design Proceedings of Spie - the International Society For Optical Engineering. 7271. DOI: 10.1117/12.812033  1
2009 Jeong K, Kahng AB, Samadi K. Impact of guardband reduction on design outcomes: A quantitative approach Ieee Transactions On Semiconductor Manufacturing. 22: 552-565. DOI: 10.1109/TSM.2009.2031789  1
2009 Jeong K, Kahng AB. A power-constrained MPU roadmap for the International Technology Roadmap for Semiconductors (ITRS) 2009 International Soc Design Conference, Isocc 2009. 49-52. DOI: 10.1109/SOCDC.2009.5423856  1
2009 Jeong K, Kahng AB, Samadi K. Architectural-level prediction of interconnect wirelength and fanout 2009 International Soc Design Conference, Isocc 2009. 53-56. DOI: 10.1109/SOCDC.2009.5423853  1
2009 Jeong K, Kahng AB, Yao H. Revisiting the linear programming framework for leakage power vs. performance optimization Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 127-134. DOI: 10.1109/ISQED.2009.4810282  1
2009 Kahng AB, Samadi K, Topaloglu RO. Recent topics in CMP-related IC design for manufacturing Advanced Metallization Conference (Amc). 403-414.  1
2009 Gupta M, Jeong K, Kahng AB. Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 607-614.  1
2008 Kahng AB. How to get real MAD Proceedings of the International Symposium On Physical Design. 69. DOI: 10.1145/1353629.1353645  1
2008 Kahng AB. Lithography and design in partnership: A new roadmap Proceedings of Spie - the International Society For Optical Engineering. 7122. DOI: 10.1117/12.813418  1
2008 Greenway RT, Jeong K, Kahng AB, Park CH, Petersen JS. 32nm 1-D regular pitch SRAM bitcell design for interference-assisted lithography Proceedings of Spie - the International Society For Optical Engineering. 7122. DOI: 10.1117/12.801883  1
2008 Kahng AB, Muddu SV. Predictive modeling of lithography-induced linewidth variation Proceedings of Spie - the International Society For Optical Engineering. 7028. DOI: 10.1117/12.793029  1
2008 Kahng AB, Muddu S, Park CH. Auxiliary pattern-based optical proximity correction for better printability, timing, and leakage control Journal of Micro/Nanolithography, Mems, and Moems. 7. DOI: 10.1117/1.2898504  1
2008 Kahng AB, Topaloglu RO. DOE-based extraction of CMP, active and via fill impact on capacitances Ieee Transactions On Semiconductor Manufacturing. 21: 22-32. DOI: 10.1109/TSM.2007.913188  1
2008 Kahng AB, Samadi K. CMP fill synthesis: A survey of recent studies Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 3-19. DOI: 10.1109/TCAD.2007.907061  1
2008 Kahng AB, Samadi K. Communication modeling for system-level design 2008 International Soc Design Conference, Isocc 2008. 1. DOI: 10.1109/SOCDC.2008.4815592  1
2008 Jeong K, Kahng AB, Yao H. On modeling and sensitivity of via count in SOC physical implementation 2008 International Soc Design Conference, Isocc 2008. 1. DOI: 10.1109/SOCDC.2008.4815589  1
2008 Jeong K, Kahng AB, Samadi K. Quantified impacts of guardband reduction on design process outcomes Proceedings of the 9th International Symposium On Quality Electronic Design, Isqed 2008. 790-797. DOI: 10.1109/ISQED.2008.4479839  1
2008 Kahng AB. Key directions and a roadmap for electrical design for manufacturability Essderc 2007 - Proceedings of the 37th European Solid-State Device Research Conference. 2007: 83-88. DOI: 10.1109/ESSDERC.2007.4430885  1
2008 Gupta P, Kahng AB. Bounded-lifetime integrated circuits Proceedings - Design Automation Conference. 347-348. DOI: 10.1109/DAC.2008.4555839  1
2008 Carloni L, Kahng AB, Muddu S, Pinto A, Samadi K, Sharma P. Interconnect modeling for improved system-level design optimization Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 258-264. DOI: 10.1109/ASPDAC.2008.4483952  1
2008 Wong B, Zach F, Moroz V, Mittal A, Starr G, Kahng A. Nano-CMOS Design for Manufacturabililty: Robust Circuit and Physical Design for Sub-65 nm Technology Nodes Nano-Cmos Design For Manufacturabililty: Robust Circuit and Physical Design For Sub-65 Nm Technology Nodes. 1-385. DOI: 10.1002/9780470382820  1
2007 Kahng AB, Muddu S, Sharma P. Detailed placement for leakage reduction using systematic through-pitch variation Proceedings of the International Symposium On Low Power Electronics and Design. 110-115. DOI: 10.1145/1283780.1283804  1
2007 Kahng AB, Liu B, Wang Q. Stochastic power/ground supply voltage prediction and optimization via analytical placement Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 904-911. DOI: 10.1109/TVLSI.2007.900745  1
2007 Kahng AB, Liu B, Xu X. Statistical timing analysis in the presence of signal-integrity effects Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1873-1877. DOI: 10.1109/TCAD.2007.895771  1
2007 Kahng AB, Mǎndoiu II, Xu X, Zelikovsky AZ. Enhanced design flow and optimizations for multiproject wafers Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 301-310. DOI: 10.1109/TCAD.2006.883922  1
2007 Chiang C, Kahng AB, Sinha S, Xu X, Zelikovsky AZ. Fast and efficient bright-field AAPSM conflict detection and correction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 115-126. DOI: 10.1109/TCAD.2006.882642  1
2007 Kahng AB, Reda S, Sharma P. On-line adjustable buffering for runtime power reduction Proceedings - Eighth International Symposium On Quality Electronic Design, Isqed 2007. 550-555. DOI: 10.1109/ISQED.2007.110  1
2007 Kahng AB, Topaloglu RO. A DOE set for normalization-based extraction of fill impact on capacitances Proceedings - Eighth International Symposium On Quality Electronic Design, Isqed 2007. 464-474. DOI: 10.1109/ISQED.2007.11  1
2007 Kahng AB. Variability mitigation in highly scaled CMOS: Challenges for EDA Technical Digest - International Electron Devices Meeting, Iedm. 644. DOI: 10.1109/IEDM.2007.4419023  1
2007 Kahng AB. Design challenges at 65nm and beyond Proceedings -Design, Automation and Test in Europe, Date. 1466-1467. DOI: 10.1109/DATE.2007.364505  1
2007 Liu B, Kahng AB. Expected performance centering for analog/RF designs Bmas 2006 - Proceedings of the 2006 Ieee International Behavioral Modeling and Simulation Workshop. 126-131. DOI: 10.1109/BMAS.2006.283482  1
2007 Liu B, Kahng AB. Statistical gate level simulation via voltage controlled current source models Bmas 2006 - Proceedings of the 2006 Ieee International Behavioral Modeling and Simulation Workshop. 23-27. DOI: 10.1109/BMAS.2006.283464  1
2007 Liu B, Kahng AB, Xu X, Hu J, Venkataraman G. A global minimum clock distribution network augmentation algorithm for guaranteed clock skew yield Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 25-31. DOI: 10.1109/ASPDAC.2007.357787  1
2007 Kahng AB, Topaloglu RO. A TCAD-based study of fill pattern and via fill impact on low-k dielectric stress 2007 Proceedings - 12th International Chemical-Mechanical Planarization For Ulsi Multilevel Interconnection Conference, Cmp-Mic 2007. 337-346.  1
2007 Kahng AB, Topaloglu RO. Performance-aware CMP fill pattern optimization 2007 Proceedings - 24th International Vlsi Multilevel Interconnection Conference, Vmic 2007. 135-144.  1
2006 Kahng AB, Park CH, Xu. Fast dual graph based hotspot detection Proceedings of Spie - the International Society For Optical Engineering. 6349. DOI: 10.1117/12.692949  1
2006 Kahng AB, Park CH. Auxiliary pattern for cell-based OPC Proceedings of Spie - the International Society For Optical Engineering. 6349. DOI: 10.1117/12.692582  1
2006 Kahng AB, Xu X. A general framework for multi-flow multi-layer multi-project reticles design Proceedings of Spie - the International Society For Optical Engineering. 6349. DOI: 10.1117/12.686324  1
2006 Kahng AB, Xu X, Zelikovsky A. Fast yield-driven fracture for variable shaped-beam mask writing Proceedings of Spie - the International Society For Optical Engineering. 6283. DOI: 10.1117/12.681805  1
2006 Gupta P, Kahng AB. Efficient design and analysis of robust power distribution meshes Proceedings of the Ieee International Conference On Vlsi Design. 2006: 337-342. DOI: 10.1109/VLSID.2006.79  1
2006 Kahng AB, Reda S. Zero-change netlist transformations: A new technique for placement benchmarking Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2806-2819. DOI: 10.1109/TCAD.2006.882473  1
2006 Nam GJ, Reda S, Alpert CJ, Villarrubia PG, Kahng AB. A fast hierarchical quadratic placement algorithm Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 678-691. DOI: 10.1109/TCAD.2006.870079  1
2006 Kahng AB, Reda S. Wirelength minimization for min-cut placements via placement feedback Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1301-1312. DOI: 10.1109/TCAD.2005.855917  1
2006 Kahng AB, Reda S. New and improved BIST diagnosis methods from combinatorial group testing theory Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 533-543. DOI: 10.1109/TCAD.2005.854635  1
2006 Kahng AB, Muddu S, Sharma P. Impact of gate-length biasing on threshold-voltage selection Proceedings - International Symposium On Quality Electronic Design, Isqed. 747-754. DOI: 10.1109/ISQED.2006.72  1
2006 Kahng AB, Liu B, Xu X. Constructing current-based gate models based on existing timing library Proceedings - International Symposium On Quality Electronic Design, Isqed. 37-42. DOI: 10.1109/ISQED.2006.39  1
2006 Kahng AB, Samadi K, Sharma P. Study of floating fill impact on interconnect capacitance Proceedings - International Symposium On Quality Electronic Design, Isqed. 691-696. DOI: 10.1109/ISQED.2006.126  1
2006 Kahng AB, Liu B, Tan S. SMM: Scalable analysis of power delivery networks by stochastic moment matching Proceedings - International Symposium On Quality Electronic Design, Isqed. 638-643. DOI: 10.1109/ISQED.2006.119  1
2006 Kahng AB, Topaloglu RO. Interconnect matching design rule inferring and optimization through correlation extraction Ieee International Conference On Computer Design, Iccd 2006. 222-229. DOI: 10.1109/ICCD.2006.4380821  1
2006 Kahng AB, Sharma P, Zelikovsky A. Fill for shallow trench isolation CMP Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 661-668. DOI: 10.1109/ICCAD.2006.320033  1
2006 Kahng AB, Mǎndoiu II, Reda S, Xu X, Zelikovsky AZ. Computer-aided optimization of DNA array design and manufacturing Design Automation Methods and Tools For Microfluidics-Based Biochips. 235-269. DOI: 10.1007/1-4020-5123-9_10  1
2006 Kahng AB, Topaloglu RO. Generation of design guarantees for interconnect matching International Workshop On System Level Interconnect Prediction, Slip. 2006: 29-34.  1
2006 Jacobsson J, Kahng AB. Designers need more than process data Electronic Engineering Times 1
2006 Kahng AB, Reda S. A tale of two nets: Studies of wirelength progression in physical design International Workshop On System Level Interconnect Prediction, Slip. 2006: 17-24.  1
2006 Kahng AB, Wang Q. A faster implementation of APlace Proceedings of the International Symposium On Physical Design. 2006: 218-220.  1
2006 Kahng AB, Liu B, Xu X. Statistical gate delay calculation with crosstalk alignment consideration Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 2006: 223-228.  1
2006 Kahng AB, Bao L, Xu X. Statistical crosstalk aggressor alignment aware interconnect delay calculation International Workshop On System Level Interconnect Prediction, Slip. 2006: 91-97.  1
2005 Kahng AB, Mandoiu I, Xu X, Zelikovsky A. Yield-driven multi-project reticle design and wafer dicing Proceedings of Spie - the International Society For Optical Engineering. 5992. DOI: 10.1117/12.632036  1
2005 Gupta P, Kahng AB, Park CH. Improving OPC quality via interactions within the design-to-manufacturing flow Proceedings of Spie - the International Society For Optical Engineering. 5853: 131-140. DOI: 10.1117/12.617372  1
2005 He L, Kahng AB, Tam KH, Xiong J. Design of integrated-circuit interconnects with accurate modeling of chemical-mechanical planarization Proceedings of Spie - the International Society For Optical Engineering. 5756: 109-119. DOI: 10.1117/12.605222  1
2005 Gupta P, Kahng AB, Park CH. Manufacturing-aware design methodology for assist feature correctness Proceedings of Spie - the International Society For Optical Engineering. 5756: 131-140. DOI: 10.1117/12.604872  1
2005 Chen Y, Kahng AB, Robins G, Zelikovsky A, Zheng Y. Compressible area fill synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1169-1187. DOI: 10.1109/TCAD.2005.850859  1
2005 Kahng AB, Wang Q. Implementation and extensibility of an analytic placer Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 734-747. DOI: 10.1109/TCAD.2005.846366  1
2005 Kahng AB, Liu B, Wang Q. Supply voltage degradation aware analytical placement Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 437-443. DOI: 10.1109/ICCD.2005.101  1
2005 Kahng AB, Reda S, Wang Q. Architecture and details of a high quality, large-scale analytical placer Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 890-897. DOI: 10.1109/ICCAD.2005.1560188  1
2005 Kahng AB, Reda S. Intrinsic shortest path length: A new, accurate a priori wirelength estimator Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 173-180. DOI: 10.1109/ICCAD.2005.1560059  1
2005 Chiang C, Kahng AB, Sinha S, Xu X. Fast and efficient phase conflict detection and correction in standard-cell layouts Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 149-156. DOI: 10.1109/ICCAD.2005.1560055  1
2005 Chiang C, Kahng A, Sinha S, Xu X, Zelikovsky A. Bright-field AAPSM conflict detection and correction Proceedings -Design, Automation and Test in Europe, Date '05. 908-913. DOI: 10.1109/DATE.2005.84  1
2005 Kahng AB, Reda S. Evaluation of placer suboptimality via zero-change netlist transformations Proceedings of the International Symposium On Physical Design. 208-215.  1
2005 Kahng AB, Reda S, Wang Q. APlace: A general analytic placement framework Proceedings of the International Symposium On Physical Design. 233-235.  1
2005 Kahng AB, Muddu S, Sharma P. Defocus-aware leakage estimation and control Proceedings of the International Symposium On Low Power Electronics and Design. 263-268.  1
2004 Kahng AB, Măndoiu II, Pevzner PA, Reda S, Zelikovsky AZ. Scalable heuristics for design of DNA probe arrays. Journal of Computational Biology : a Journal of Computational Molecular Cell Biology. 11: 429-47. PMID 15285900 DOI: 10.1089/1066527041410391  1
2004 Kahng AB, Xu X, Zelikovsky A. Yield- And cost-driven fracturing for variable shaped-beam mask writing Proceedings of Spie - the International Society For Optical Engineering. 5567: 360-371. DOI: 10.1117/12.568526  1
2004 Kahng AB, Xu X. Local Unidirectional Bias for Cutsize-Delay Tradeoff in Performance-Driven Bipartitioning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 464-471. DOI: 10.1109/TCAD.2004.825847  1
2004 Caldwell AE, Choi HJ, Kahng AB, Mantik S, Potkonjak M, Qu G, Wong JL. Effective iterative techniques for fingerprinting design IP Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 208-215. DOI: 10.1109/TCAD.2003.822126  1
2004 Kahng AB, Liu B, Mǎndoiu II. Nontree Routing for Reliability and Yield Improvement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 148-156. DOI: 10.1109/TCAD.2003.819426  1
2004 Hill D, Kahng AB. Guest Editors' Introduction: RTL to GDSII - From Foilware to Standard Practice Ieee Design and Test of Computers. 21: 9-12. DOI: 10.1109/MDT.2004.1261845  1
2004 Kahng AB, Reda S. Reticle floorplanning with guaranteed yield for multi-project wafers Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 106-110. DOI: 10.1109/ICCD.2004.1347908  1
2004 Kahng AB, Markov IL, Reda S. Boosting: Min-cut placement with improved signal delay Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 2: 1098-1103. DOI: 10.1109/DATE.2004.1269039  1
2004 Kahng AB. Design for yield needed for further scaling Iee Electronics Systems and Software. 2: 48. DOI: 10.1049/ess:20040211  1
2004 Kahng AB, Reda S. Match twice and stitch: A new TSP tour construction heuristic Operations Research Letters. 32: 499-509. DOI: 10.1016/j.orl.2004.04.001  1
2004 Gupta P, Kahng AB. Wire swizzling to reduce delay uncertainty due to capacitive coupling Proceedings of the Ieee International Conference On Vlsi Design. 17: 431-436.  1
2004 Kahng AB, Reda S. Combinatorial group testing methods for the BIST diagnosis problem Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 113-116.  1
2004 Kahng AB, Reda S. Placement feedback: A concept and method for better min-cut placements Proceedings - Design Automation Conference. 357-362.  1
2004 Kahng AB, Wang Q. An analytic placer for mixed-size placement and timing-driven placement Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 565-572.  1
2004 Kahng AB, Mǎndou I, Wang Q, Xu X, Zelikovsky AZ. Multi-project reticle floorplanning and wafer dicing Proceedings of the International Symposium On Physical Design. 70-77.  1
2004 Chen Y, Kahng AB, Robins G, Zelikovsky A, Zheng Y. Evaluation of the new OASIS format for layout fill compression 11th Ieee International Conference On Electronics, Circuits and Systems, Icecs 2004. 377-382.  1
2003 Chen Y, Gupta P, Kahng AB. Performance-impact limited area fill synthesis Proceedings - Design Automation Conference. 22-27. DOI: 10.1117/12.487732  1
2003 Gupta P, Kahng AB, Sylvester D, Yang J. Toward performance-driven reduction of the cost of RET-based lithography control Proceedings of Spie - the International Society For Optical Engineering. 5043: 123-133. DOI: 10.1117/12.485277  1
2003 Ellis RB, Kahng AB, Zheng Y. Compression Algorithms for "Dummy Fill" VLSI Layout Data Proceedings of Spie - the International Society For Optical Engineering. 5042: 233-245. DOI: 10.1117/12.485247  1
2003 Caldwell AE, Kahng AB, Markov IL. Hierarchical whitespace allocation in top-down placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1550-1556. DOI: 10.1109/TCAD.2003.818375  1
2003 Albrecht C, Kahng AB, Liu B, Mǎndoiu II, Zelikovsky AZ. On the skew-bounded minimum-buffer routing tree problem Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 937-945. DOI: 10.1109/TCAD.2003.814238  1
2003 Alpert CJ, Kahng AB, Liu B, Mǎndoiu II, Zelikovsky AZ. Minimum buffered routing with bounded capacitive load for slew rate and reliability control Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 241-253. DOI: 10.1109/TCAD.2002.807888  1
2003 Kahng AB. How much variability can designers tolerate? Ieee Design and Test of Computers. 20: 96-97. DOI: 10.1109/MDT.2003.1246168  1
2003 Kahng AB, Liu B. Q-Tree: a new iterative improvement approach for buffered interconnect optimization Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 2003: 183-188. DOI: 10.1109/ISVLSI.2003.1183444  1
2003 Gupta P, Kahng AB, Mantik S. A proposal for routing-based timing-driven scan chain ordering Proceedings - International Symposium On Quality Electronic Design, Isqed. 2003: 339-343. DOI: 10.1109/ISQED.2003.1194755  1
2003 Gupta P, Kahng AB. Quantifying error in dynamic power estimation of CMOS circuits Proceedings - International Symposium On Quality Electronic Design, Isqed. 2003: 273-278. DOI: 10.1109/ISQED.2003.1194745  1
2003 Kahng AB, Markov IL. Impact of interoperability on CAD-IP reuse: an academic viewpoint Proceedings - International Symposium On Quality Electronic Design, Isqed. 2003: 208-213. DOI: 10.1109/ISQED.2003.1194733  1
2003 Chen Y, Kahng AB, Robins G, Zelikovsky A, Zheng Y. Area fill generation with inherent data volume reduction Proceedings -Design, Automation and Test in Europe, Date. 868-873. DOI: 10.1109/DATE.2003.1253715  1
2003 Dasgupta P, Kahng AB, Muddu S. A novel metric for interconnect architecture performance Proceedings -Design, Automation and Test in Europe, Date. 448-453. DOI: 10.1109/DATE.2003.1253650  1
2003 Gupta P, Kahng AB, Mantik S. Routing-aware scan chain ordering Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2003: 857-862. DOI: 10.1109/ASPDAC.2003.1195137  1
2003 Kahng AB, Mǎndoiu II, Zelikovsky AZ. Highly scalable algorithms for rectilinear and octilinear Steiner trees Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2003: 827-833. DOI: 10.1109/ASPDAC.2003.1195132  1
2003 Kahng AB. Research directions for coevolution of rules and routers Proceedings of the International Symposium On Physical Design. 122-125.  1
2003 Kahng AB. Bringing down NRE Ieee Design and Test of Computers. 20: 110-111.  1
2003 Kahng AB, Xu X. Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning Proceedings of the International Symposium On Physical Design. 81-86.  1
2003 Kahng AB, Xu X. Accurate Pseudo-Constructive Wirelength and Congestion Estimation International Workshop On System Level Interconnect Prediction. 61-68.  1
2003 Gupta P, Kahng AB. Manufacturing-Aware Physical Design Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 681-687.  1
2003 Kahng AB, Mǎndoiu I, Pevzner P, Reda S, Zelikovsky A. Engineering a scalable placement heuristic for DNA probe arrays Proceedings of the Annual International Conference On Computational Molecular Biology, Recomb. 148-156.  1
2003 Kahng AB, Mǎndoiu II, Reda S, Xu X, Zelikovsky AZ. Design flow enhancements for DNA arrays Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 116-123.  1
2002 Kahng AB, Liu B, Mǎndoiu II. Non-tree routing for reliability and yield improvement Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 260-266. DOI: 10.1145/774572.774611  1
2002 Chen Y, Kahng AB, Robins G, Zelikovsky A. Monte-Carlo methods for chemical-mechanical planarization on multiple-layer and dual-material models Proceedings of Spie - the International Society For Optical Engineering. 4692: 421-432. DOI: 10.1117/12.475677  1
2002 Kahng AB. Design-process integration and shared red bricks Proceedings of Spie - the International Society For Optical Engineering. 4692: 390-400. DOI: 10.1117/12.475674  1
2002 Chen Y, Kahng AB, Robins G, Zelikovsky A. Area fill synthesis for uniform layout density Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 1132-1147. DOI: 10.1109/TCAD.2002.802278  1
2002 Kahng AB. Directions for drivers and design Ieee Circuits and Devices Magazine. 18: 32-39. DOI: 10.1109/MCD.2002.1021120  1
2002 Kahng AB, Mantik S. Measurement of inherent noise in EDA tools Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 206-211. DOI: 10.1109/ISQED.2002.996731  1
2002 Kahng AB, Smith G. A new design cost model for the 2001 ITRS Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 190-193. DOI: 10.1109/ISQED.2002.996728  1
2002 Albrecht C, Kahng AB, Mǎndoiu I, Zelikovsky A. Floorplan evaluation with timing-driven global wireplanning, pin assignment, and buffer/wire sizing Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference On Vlsi Design, Asp-Dac/Vlsi Design 2002. 580-587. DOI: 10.1109/ASPDAC.2002.994986  1
2002 Dragan FF, Kahng AB, Mǎndoiu II, Muddu S, Zelikovsky A. Provably good global buffering by generalized multiterminal multicommodity flow approximation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 263-274. DOI: 10.1109/43.986421  1
2002 Cooper JN, Ellis RB, Kahng AB. Asymmetric binary covering codes Journal of Combinatorial Theory. Series A. 100: 232-249. DOI: 10.1006/jcta.2002.3290  1
2002 Kahng AB. A roadmap and vision for physical design Proceedings of the International Symposium On Physical Design. 112-117.  1
2002 Kahng AB. The significance of packaging Ieee Design and Test of Computers. 19: 104-105.  1
2002 Kahng AB, Mantik S, Markov IL. Min-max placement for large-scale timing optimization Proceedings of the International Symposium On Physical Design. 143-148.  1
2002 Chen Y, Kahng AB, Robins G, Zelikovsky A. Closing the smoothness and uniformity gap in area fill synthesis Proceedings of the International Symposium On Physical Design. 137-142.  1
2002 Kahng AB, Măndoiu II, Pevzner PA, Reda S, Zelikovsky AZ. Border length minimization in dna array design Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2452: 435-448.  1
2001 Joyner WH, Kahng AB. Roadmaps and visions for design and test Ieee Design and Test of Computers. 18: 4-5. DOI: 10.1109/MDT.2001.970414  1
2001 Kahng AB, Mantik S. A system for automatic recording and prediction of design quality metrics Proceedings - International Symposium On Quality Electronic Design, Isqed. 2001: 81-86. DOI: 10.1109/ISQED.2001.915210  1
2001 Kahng AB. Design technology productivity in the DSM era Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2001: 443-448. DOI: 10.1109/ASPDAC.2001.913348  1
2001 Chen Y, Kahng AB, Robins G, Zelikovsky A. Hierarchical dummy fill for process uniformity Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2001: 139-144. DOI: 10.1109/ASPDAC.2001.913294  1
2001 Kahng AB, Vaya S, Zelikovsky A. New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2001: 133-138. DOI: 10.1109/ASPDAC.2001.913293  1
2001 Dragan FF, Kahng AB, Mandoiu I, Muddu S, Zelikovsky A. Provably good global buffering by multiterminal multicommodity flow approximation Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2001: 120-125. DOI: 10.1109/ASPDAC.2001.913291  1
2001 Baldick R, Kahng AB, Kennings A, Markov IL. Efficient optimization by modifying the objective function: Applications to timing-driven VLSI layout Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 48: 947-956. DOI: 10.1109/81.940185  1
2001 Bryant RE, Cheng KT, Kahng AB, Keutzer K, Maly W, Newton R, Pileggi L, Rabaey JM, Sangiovanni-Vincentelli A. Limitations and challenges of computer-aided design technology for CMOS VLSI Proceedings of the Ieee. 89: 341-363. DOI: 10.1109/5.915378  1
2001 Kahng AB, Lach J, Mangione-Smith WH, Mantik S, Markov IL, Potkonjak M, Tucker P, Wang H, Wolfe G. Constraint-based watermarking techniques for design IP protection Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1236-1252. DOI: 10.1109/43.952740  1
2001 Kahng AB, Mantik S, Stroobandt D. Toward accurate models of achievable routing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 648-659. DOI: 10.1109/43.920697  1
2001 Dragan FF, Kahng AB, M Ã Ndoiu II, Muddu S, Zelikovsky A. Practical approximation algorithms for separable packing linear programs Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2125: 325-337. DOI: 10.1007/3-540-44634-6_30  1
2001 Cheng CK, Kahng AB, Liu B. Interconnect implications of growth-based structural models for VLSI circuits 2001 International Workshop On System-Level Interconnect Prediction (Slip 2001). 99-106.  1
2001 Alpert C, Kahng AB, Liu B, Mǎndoiu I, Zelikovsky A. Minimum-buffered routing of non-critical nets for slew rate and reliability control Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 408-415.  1
2000 Caldwell AE, Kahng AB, Markov IL. Improved algorithms for hypergraph bipartitioning Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 661-666. DOI: 10.1145/368434.368864  1
2000 Chen Y, Kahng AB, Robins G, Zelikovsky A. Monte-Carlo algorithms for layout density control Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 523-528. DOI: 10.1145/368434.368778  1
2000 Caldwell AE, Kahng AB, Markov IL. Optimal partitioners and end-case placers for standard-cell layout Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 1304-1313. DOI: 10.1109/43.892854  1
2000 Alpert CJ, Caldwell AE, Kahng AB, Markov IL. Hypergraph partitioning with fixed vertices Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 267-272. DOI: 10.1109/43.828555  1
2000 Berman P, Kahng AB, Vidhani D, Wang H, Zelikovsky A. Optimal phase conflict removal for layout of dark field alternating phase shifting masks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 175-187. DOI: 10.1109/43.828546  1
2000 Kahng AB, Stroobandt D. Wiring layer assignments with consistent stage delays International Workshop On System-Level Interconnect Prediction (Slip 2000). 115-122.  1
2000 Stroobandt D, Christie P, Kahng AB. International Workshop on System-Level Interconnect Prediction (SLIP 2000): Foreword International Workshop On System-Level Interconnect Prediction (Slip 2000) 1
2000 Caldwell AE, Kahng AB, Markov IL. Iterative partitioning with varying node weights Vlsi Design. 11: 249-258.  1
2000 Caldwell AE, Kahng AB, Markov IL. Optimal partitioners and endcase placers for standardcell layout Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 13041313.  1
1999 Caldwell AE, Kahng AB, Mantik S, Markov IL, Zelikovsky A. On wirelength estimations for row-based placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1265-1278. DOI: 10.1109/43.784119  1
1999 Kahng AB, Robins G, Singh A, Zelikovsky A. Filling algorithms and analyses for layout density control Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 445-462. DOI: 10.1109/43.752928  1
1999 Kahng AB, Pati YC. Subwavelength optical lithography: Challenges and impact on physical design Proceedings of the International Symposium On Physical Design. 112-119.  1
1999 Kahng AB, Muddu S, Sarto E. Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs Vlsi Design. 10: 21-34.  1
1999 Alpert CJ, Kahng AB, Yao SZ. Spectral partitioning with multiple eigenvectors Discrete Applied Mathematics. 90: 3-26.  1
1999 Alpert CJ, Caldwell AE, Kahng AB, Markov IL. Partitioning with terminals: A `new' problem and new benchmarks Proceedings of the International Symposium On Physical Design. 151-157.  1
1999 Berman P, Kahng AB, Vidhani D, Zelikovsky A. The T-join problem in sparse graphs: Applications to phase assignment problem in VLSI mask layout Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1663: 25-36.  1
1998 Alpert CJ, Huang JH, Kahng AB. Multilevel circuit partitioning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 655-667. DOI: 10.1109/43.712098  1
1998 Cong J, Kahng AB, Leung KS. Efficient algorithms for the minimum shortest path steiner arborescence problem with applications to VLSI physical design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 24-39. DOI: 10.1109/43.673630  1
1998 Alpert CJ, Chan TF, Kahng AB, Markov IL, Mulet P. Faster minimization of linear wirelength for global placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 3-13. DOI: 10.1109/43.673628  1
1998 Kahng AB, Robins G, Walkup EA. How to test a tree Networks. 32: 189-197.  1
1998 Cong J, Kahng AB, Koh CK, Albert Tsao CW. Bounded-skew clock and steiner routing Acm Transactions On Design Automation of Electronic Systems. 3: 341-388.  1
1997 Kahng AB, Muddu S. An analytical delay model for RLC interconnects Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 1507-1514. DOI: 10.1109/43.664231  1
1997 Hagen LW, Huang DJH, Kahng AB. On implementation choices for iterative improvement partitioning algorithms Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 1199-1205. DOI: 10.1109/43.662682  1
1997 Hagen LW, Kahng AB. Combining problem reduction and adaptive multistart: A new technique for superior iterative partitioning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 709-717. DOI: 10.1109/43.644032  1
1997 Alpert CJ, Kahng AB. Splitting an ordering into a partition to minimize diameter Journal of Classification. 14: 51-74.  1
1997 Kahng AB, Muddu S. Analysis of RC interconnections under ramp input Acm Transactions On Design Automation of Electronic Systems. 2: 168-192.  1
1997 Kahng AB, Tsao CWA. Practical Bounded-Skew Clock Routing Journal of Vlsi Signal Processing Systems For Signal, Image, and Video Technology. 16: 199-215.  1
1996 Alpert CJ, Kahng AB. A general framework for vertex orderings with applications to circuit clustering Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 4: 240-246. DOI: 10.1109/92.502195  1
1996 Kahng AB, Tsao CWA. Planar-DME: A single-layer zero-skew clock tree router Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 8-19. DOI: 10.1109/43.486268  1
1995 Alpert CJ, Kahng AB. Multiway Partitioning Via Geometric Embeddings, Orderings, and Dynamic Programming Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 1342-1358. DOI: 10.1109/43.469661  1
1995 Alpert CJ, Kahng AB. Recent directions in netlist partitioning: a survey Integration, the Vlsi Journal. 19: 1-81. DOI: 10.1016/0167-9260(95)00008-4  1
1994 Hagen L, Kurdahi FJ, Kahng AB, Ramachandran C. On the Intrinsic Rent Parameter and Spectra-Based Partitioning Methodologies Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 27-37. DOI: 10.1109/43.273752  1
1994 Boese KD, Kahng AB. Best-so-far vs. where-you-are: implications for optimal finite-time annealing Systems and Control Letters. 22: 71-78. DOI: 10.1016/0167-6911(94)90028-0  1
1994 Boese KD, Kahng AB, Muddu S. A new adaptive multi-start technique for combinatorial global optimizations Operations Research Letters. 16: 101-113. DOI: 10.1016/0167-6377(94)90065-5  1
1994 Alpert CJ, Kahng AB. Multi-way partitioning via spacefilling curves and dynamic programming Proceedings - Design Automation Conference. 652-657.  1
1994 Alpert CJ, Kahng AB. General framework for vertex orderings, with applications to netlist clustering Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 63-67.  1
1993 Hu TC, Kahng AB, Robins G. Optimal Robust Path Planning in General Environments Ieee Transactions On Robotics and Automation. 9: 775-784. DOI: 10.1109/70.265921  1
1993 Cong J, Kahng AB, Robins G. Matching-Based Methods for High-Performance Clock Routing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 1157-1169. DOI: 10.1109/43.238608  1
1993 Alpert CJ, Kahng AB. Geometric embeddings for faster and better multi-way netlist partitioning Proceedings - Design Automation Conference. 743-748.  1
1993 Boese KD, Kahng AB, Tsao CWA. Best-so far vs where you are: New perspectives on simulated annealing for CAD European Design Automation Conference - Proceedings. 78-83.  1
1993 Alpert CJ, Hu TC, Huang JH, Kahng AB. Direct combination of the prim and Dijkstra constructions for improved performance-driven global routing Proceedings - Ieee International Symposium On Circuits and Systems. 3: 1869-1872.  1
1992 Kahng AB, Robins G. On Performance Bounds for a Class of Rectilinear Steiner Tree Heuristics in Arbitrary Dimension Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 11: 1462-1465. DOI: 10.1109/43.177409  1
1992 Hagen L, Kahng AB. New Spectral Methods for Ratio Cut Partitioning and Clustering Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 11: 1074-1085. DOI: 10.1109/43.159993  1
1992 Kahng AB, Robins G. A New Class of Iterative Steiner Tree Heuristics with Good Performance Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 11: 893-902. DOI: 10.1109/43.144853  1
1992 Hu TC, Kahng AB, Robins G. Solution of the discrete Plateau problem Proceedings of the National Academy of Sciences of the United States of America. 89: 9235-9236. DOI: 10.1073/pnas.89.19.9235  1
1991 Kahng AB, Robins G. Optimal algorithms for extracting spatial regularity in images Pattern Recognition Letters. 12: 757-764. DOI: 10.1016/0167-8655(91)90073-U  1
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