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Igor L. Markov, Ph.D. - Publications

Affiliations: 
2001 University of California, Los Angeles, Los Angeles, CA 
Area:
Computer Science, Electronics and Electrical Engineering, Mathematics
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85 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2015 Plaza SM, Markov IL. Solving the third-shift problem in IC piracy with test-aware logic locking Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 961-971. DOI: 10.1109/Tcad.2015.2404876  0.306
2015 Garcia HJ, Markov IL. Simulation of quantum circuits via stabilizer frames Ieee Transactions On Computers. 64: 2323-2336. DOI: 10.1109/Tc.2014.2360532  0.321
2014 Markov IL. Limits on fundamental limits to computation. Nature. 512: 147-54. PMID 25119233 DOI: 10.1038/Nature13570  0.39
2013 Nadakuditi RR, Markov IL. On bottleneck analysis in stochastic stream processing Acm Transactions On Design Automation of Electronic Systems. 18. DOI: 10.1145/2491477.2491478  0.359
2013 Kim MC, Lee DJ, Markov IL. SimPL: An algorithm for placing VLSI circuits Communications of the Acm. 56: 105-113. DOI: 10.1145/2461256.2461279  0.419
2013 Saeedi M, Markov IL. Synthesis and optimization of reversible circuits-a survey Acm Computing Surveys. 45. DOI: 10.1145/2431211.2431220  0.389
2013 Kahng AB, Kang S, Lee H, Markov IL, Thapar P. High-performance gate sizing with a signoff timer Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 450-457. DOI: 10.1109/ICCAD.2013.6691156  0.518
2013 Markov IL, Saeedi M. Faster quantum number factoring via circuit synthesis Physical Review a - Atomic, Molecular, and Optical Physics. 87. DOI: 10.1103/Physreva.87.012310  0.373
2013 Papa DA, Markov IL. Co-optimization of latches and clock networks Lecture Notes in Electrical Engineering. 166: 133-148. DOI: 10.1007/978-1-4614-1356-1-9  0.318
2012 Lee DJ, Markov IL. Obstacle-aware clock-tree shaping during placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 205-216. DOI: 10.1109/Tcad.2011.2173490  0.399
2012 Kim MC, Lee DJ, Markov IL. SimPL: An effective placement algorithm Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 50-60. DOI: 10.1109/Tcad.2011.2170567  0.391
2011 Papa D, Viswanathan N, Sze C, Li Z, Nam GJ, Alpert C, Markov IL. Physical synthesis with clock-network optimization for large systems on chips Ieee Micro. 31: 51-62. DOI: 10.1109/Mm.2011.41  0.402
2011 Markov IL. Getting Your Bits in Order Ieee Design & Test of Computers. 28: 98-101. DOI: 10.1109/Mdt.2011.86  0.363
2011 Kahng AB, Lienig J, Markov IL, Hu J. VLSI physical design: From graph partitioning to timing closure Vlsi Physical Design: From Graph Partitioning to Timing Closure. 1-310. DOI: 10.1007/978-90-481-9591-6  0.368
2010 Lee D, Markov IL. Contango: Integrated optimization of SoC clock networks Proceedings -Design, Automation and Test in Europe, Date. 1468-1473. DOI: 10.1155/2011/407507  0.388
2010 Chang KH, Bertacco V, Markov IL, Mishchenko A. Logic synthesis and circuit customization using extensive external don't-cares Acm Transactions On Design Automation of Electronic Systems. 15. DOI: 10.1145/1754405.1754411  0.331
2010 Markov I. Chips in 3D Ieee Design & Test of Computers. 27: 68-69. DOI: 10.1109/Mdt.2010.81  0.345
2010 Papa D, Moffitt MD, Alpert CJ, Markov IL. Speeding up physical synthesis with transactional timing analysis Ieee Design and Test of Computers. 27: 14-24. DOI: 10.1109/Mdt.2010.76  0.377
2010 Roy JA, Koushanfar F, Markov IL. Ending piracy of integrated circuits Computer. 43: 30-38. DOI: 10.1109/Mc.2010.284  0.327
2010 Katebi H, Markov IL. Large-scale boolean matching Proceedings -Design, Automation and Test in Europe, Date. 771-776.  0.305
2009 Krishnaswamy S, Plaza SM, Markov IL, Hayes JP. Signature-based SER analysis and design of logic circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 74-86. DOI: 10.1109/Tcad.2008.2009139  0.407
2009 Markov I. Book Review: A physical-design picture book Ieee Design & Test of Computers. 26: 100-101. DOI: 10.1109/Mdt.2009.68  0.379
2009 Roy JA, Ng AN, Aggarwal R, Ramachandran V, Markov IL. Solving modern mixed-size placement instances Integration, the Vlsi Journal. 42: 262-275. DOI: 10.1016/J.Vlsi.2008.09.003  0.423
2009 Aloul FA, Ramani A, Markov IL, Sakallah KA. Dynamic symmetry-breaking for Boolean satisfiability Annals of Mathematics and Artificial Intelligence. 57: 59-73. DOI: 10.1007/S10472-010-9173-2  0.348
2008 Roy JA, Papa DA, Markov IL. Fine control of local whitespace in placement Vlsi Design. 2008. DOI: 10.1155/2008/517919  0.434
2008 Markov I. What is post-silicon debug? Acm Sigda Newsletter. 38: 1-1. DOI: 10.1145/1862828.1862829  0.356
2008 Krishnaswamy S, Viamontes GF, Markov IL, Hayes JP. Probabilistic transfer matrices in symbolic reliability analysis of logic circuits Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1297666.1297674  0.329
2008 Aloul FA, Ramani A, Markov IL, Sakallah KA. Symmetry breaking for pseudo-Boolean formulas Journal of Experimental Algorithmics. 12. DOI: 10.1145/1227161.1278375  0.333
2008 Markov IL, Shi Y. Simulating quantum computation by contracting tensor networks Siam Journal On Computing. 38: 963-981. DOI: 10.1137/050644756  0.303
2008 Roy JA, Markov IL. High-performance routing at the nanometer scale Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1066-1077. DOI: 10.1109/Tcad.2008.923255  0.389
2008 Plaza SM, Markov IL, Bertacco VM. Optimizing nonmonotonic interconnect using functional simulation and logic restructuring Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 2107-2119. DOI: 10.1109/TCAD.2008.2006156  0.359
2008 Plaza SM, Markov IL, Bertacco V. Optimizing non-monotonic interconnect using functional simulation and logic restructuring Proceedings of the International Symposium On Physical Design. 95-102. DOI: 10.1109/Tcad.2008.2006156  0.466
2008 Papa DA, Luo T, Moffitt MD, Sze CN, Li Z, Nam GJ, Alpert CJ, Markov IL. RUMBLE: An incremental timing-driven physical-synthesis optimization algorithm Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 2156-2168. DOI: 10.1109/Tcad.2008.2006155  0.442
2008 Chang KH, Markov IL, Bertacco V. Fixing design errors with counterexamples and resynthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 184-188. DOI: 10.1109/Tcad.2007.907257  0.355
2008 Chang KH, Markov IL, Bertacco V. Automating postsilicon debugging and repair Computer. 41: 47-54. DOI: 10.1109/Mc.2008.212  0.351
2008 Chang Kh, Markov IL, Bertacco V. SafeResynth: A new technique for physical synthesis Integration, the Vlsi Journal. 41: 544-556. DOI: 10.1016/J.Vlsi.2008.01.004  0.402
2007 Chang KH, Markov IL, Bertacco V. Postplacement rewiring by exhaustive search for functional symmetries Acm Transactions On Design Automation of Electronic Systems. 12. DOI: 10.1145/1255456.1255469  0.413
2007 Roy JA, Markov IL. ECO-system: Embracing the change in placement Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 147-152. DOI: 10.1109/Tcad.2007.907271  0.403
2007 Roy JA, Markov IL. Seeing the forest and the trees: Steiner wirelength optimization in placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 632-644. DOI: 10.1109/Tcad.2006.888260  0.389
2007 Aloul FA, Ramani A, Sakallah KA, Markov IL. Solution and optimization of systems of pseudo-Boolean constraints Ieee Transactions On Computers. 56: 1415-1424. DOI: 10.1109/Tc.2007.1075  0.368
2007 Chang KH, Papa DA, Markov IL, Bertacco V. InVerS: An incremental verification system with circuit similarity metrics and error visualization Proceedings - Eighth International Symposium On Quality Electronic Design, Isqed 2007. 487-492. DOI: 10.1109/ISQED.2007.94  0.301
2007 Chang KH, Markov IL, Bertacco V. Safe delay optimization for physical synthesis Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 628-633. DOI: 10.1109/ASPDAC.2007.358056  0.308
2006 Ramani A, Markov IL, Sakallah KA, Aloul FA. Breaking instance-independent symmetries in exact graph coloring Journal of Artificial Intelligence Research. 26: 289-322. DOI: 10.1613/Jair.1637  0.376
2006 Moffitt MD, Ng AN, Markov IL, Pollack ME. Constraint-driven floorplan repair Proceedings - Design Automation Conference. 1103-1108. DOI: 10.1145/1391962.1391975  0.459
2006 Prasad AK, Shende VV, Markov IL, Hayes JP, Patel KN. Data structures and algorithms for simplifying reversible circuits Acm Journal On Emerging Technologies in Computing Systems. 2: 277-293. DOI: 10.1145/1216396.1216399  0.4
2006 Roy JA, Adya SN, Papa DA, Markov IL. Min-cut floorplacement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1313-1326. DOI: 10.1109/Tcad.2005.855969  0.452
2006 Shende VV, Bullock SS, Markov IL. Synthesis of quantum-logic circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1000-1010. DOI: 10.1109/Tcad.2005.855930  0.364
2006 Svore KM, Aho AV, Cross AW, Chuang I, Markov IL. A layered software architecture for quantum computing design tools Computer. 39: 74-83. DOI: 10.1109/Mc.2006.4  0.358
2006 Adya SN, Markov IL, Villarrubia PG. On whitespace and stability in physical synthesis Integration, the Vlsi Journal. 39: 340-362. DOI: 10.1016/J.Vlsi.2005.08.003  0.424
2006 Ng A, Markov IL, Aggarwal R, Ramachandran V. Solving hard instances of floorplacement Proceedings of the International Symposium On Physical Design. 2006: 170-177.  0.319
2005 Adya SN, Markov IL. Combinatorial techniques for mixed-size placement Acm Transactions On Design Automation of Electronic Systems. 10: 58-90. DOI: 10.1145/1044111.1044116  0.421
2005 Chang KH, Bertacco V, Markov IL. Simulation-based bug trace minimization with BMC-based refinement Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 1042-1048. DOI: 10.1109/Tcad.2006.882511  0.385
2005 Motter DB, Roy JA, Markov IL. Resolution cannot polynomially simulate compressed-BFS Annals of Mathematics and Artificial Intelligence. 44: 121-156. DOI: 10.1007/S10472-004-8427-2  0.37
2004 Viamontes GF, Markov IL, Hayes JP. Graph-based simulation of quantum computation in the density matrix representation Proceedings of Spie - the International Society For Optical Engineering. 5436: 285-296. DOI: 10.1117/12.542767  0.328
2004 Patel KN, Markov IL. Error-correction and crosstalk avoidance in DSM busses Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 1076-1080. DOI: 10.1109/Tvlsi.2004.827565  0.331
2004 Adya SN, Yildiz MC, Markov IL, Villarrubia PG, Parakh PN, Madden PH. Benchmarking for Large-Scale Placement and Beyond Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 472-487. DOI: 10.1109/Tcad.2004.825852  0.397
2004 Kahng AB, Markov IL, Reda S. Boosting: Min-cut placement with improved signal delay Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 2: 1098-1103. DOI: 10.1109/DATE.2004.1269039  0.478
2004 Shende VV, Bullock SS, Markov IL. Recognizing small-circuit structure in two-qubit operators Physical Review a - Atomic, Molecular, and Optical Physics. 70: 012310-1-012310-5. DOI: 10.1103/Physreva.70.012310  0.312
2004 Shende VV, Markov IL, Bullock SS. Minimal universal two-qubit controlled-NOT-based circuits Physical Review a - Atomic, Molecular, and Optical Physics. 69: 062321-1. DOI: 10.1103/Physreva.69.062321  0.329
2004 Adya SN, Chaturvedi S, Roy JA, Papa DA, Markov IL. Unification of partitioning, placement and floorplanning Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 550-557.  0.348
2004 Darga PT, Liffiton MH, Sakallah KA, Markov IL. Exploiting structure in symmetry detection for CNF Proceedings - Design Automation Conference. 530-534.  0.301
2003 Adya SN, Markov IL. Fixed-outline floorplanning: Enabling hierarchical design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 1120-1135. DOI: 10.1109/Tvlsi.2003.817546  0.429
2003 Cao Y, Hu C, Huang X, Kahng AB, Markov IL, Oliver M, Stroobandt D, Sylvester D. Improved a priori interconnect predictions and technology extrapolation in the GTX system Ieee Transactions On Very Large Scale Integration Systems. 11: 3-14. DOI: 10.1109/Tvlsi.2002.808479  0.515
2003 Patel KN, Hayes JP, Markov IL. Fault testing for reversible circuits Proceedings of the Ieee Vlsi Test Symposium. 2003: 410-416. DOI: 10.1109/Tcad.2004.831576  0.335
2003 Caldwell AE, Kahng AB, Markov IL. Hierarchical whitespace allocation in top-down placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1550-1556. DOI: 10.1109/Tcad.2003.818375  0.592
2003 Aloul FA, Ramani A, Markov IL, Sakallah KA. Solving difficult instances of Boolean satisfiability in the presence of symmetry Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1117-1137. DOI: 10.1109/Tcad.2003.816218  0.352
2003 Shende VV, Prasad AK, Markov IL, Hayes JP. Synthesis of reversible logic circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 710-722. DOI: 10.1109/Tcad.2003.811448  0.368
2003 Aloul FA, Sakallah KA, Markov IL. Efficient symmetry breaking for Boolean satisfiability Ijcai International Joint Conference On Artificial Intelligence. 271-276. DOI: 10.1109/Tc.2006.75  0.333
2003 Kahng AB, Markov IL. Impact of interoperability on CAD-IP reuse: an academic viewpoint Proceedings - International Symposium On Quality Electronic Design, Isqed. 2003: 208-213. DOI: 10.1109/ISQED.2003.1194733  0.397
2003 Viamontes GF, Markov IL, Hayes JP. Improving Gate-Level Simulation of Quantum Circuits Quantum Information Processing. 2: 347-380. DOI: 10.1023/B:Qinp.0000022725.70000.4A  0.304
2002 Caldwell AE, Markov IL, Kahng AB. Toward CAD-IP reuse: a web bookshelf of fundamental algorithms Ieee Design & Test of Computers. 19: 72-81. DOI: 10.1109/Mdt.2002.1003801  0.534
2002 Kahng AB, Mantik S, Markov IL. Min-max placement for large-scale timing optimization Proceedings of the International Symposium On Physical Design. 143-148.  0.746
2001 Baldick R, Kahng AB, Kennings A, Markov IL. Efficient optimization by modifying the objective function: Applications to timing-driven VLSI layout Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 48: 947-956. DOI: 10.1109/81.940185  0.56
2001 Kahng AB, Lach J, Mangione-Smith WH, Mantik S, Markov IL, Potkonjak M, Tucker P, Wang H, Wolfe G. Constraint-based watermarking techniques for design IP protection Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1236-1252. DOI: 10.1109/43.952740  0.75
2000 Caldwell AE, Kahng AB, Markov IL. Iterative partitioning with varying node weights Vlsi Design. 11: 249-258. DOI: 10.1155/2000/15862  0.517
2000 Caldwell AE, Kahng AB, Markov IL. Improved algorithms for hypergraph bipartitioning Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 661-666. DOI: 10.1145/368434.368864  0.453
2000 Caldwell AE, Kahng AB, Markov IL. Design and implementation of move-based heuristics for VLSI hypergraph partitioning Acm Journal of Experimental Algorithmics. 5: 5. DOI: 10.1145/351827.384247  0.596
2000 Caldwell AE, Kahng AB, Markov IL. Optimal partitioners and end-case placers for standard-cell layout Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 1304-1313. DOI: 10.1109/43.892854  0.429
2000 Caldwell AE, Kahng AB, Markov IL. Optimal partitioners and endcase placers for standardcell layout Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 13041313. DOI: 10.1109/43.892854  0.594
2000 Alpert CJ, Caldwell AE, Kahng AB, Markov IL. Hypergraph partitioning with fixed vertices Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 267-272. DOI: 10.1109/43.828555  0.572
1999 Alpert CJ, Caldwell AE, Chan TF, Huang DJ, Kahng AB, Markov IL, Moroz MS. Analytical Engines are Unnecessary in Top-down Partitioning-based Placement Vlsi Design. 10: 99-116. DOI: 10.1155/1999/93607  0.53
1999 Caldwell AE, Kahng AB, Mantik S, Markov IL, Zelikovsky A. On wirelength estimations for row-based placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1265-1278. DOI: 10.1109/43.784119  0.715
1999 Alpert CJ, Caldwell AE, Kahng AB, Markov IL. Partitioning with terminals: A `new' problem and new benchmarks Proceedings of the International Symposium On Physical Design. 151-157.  0.43
1998 Alpert CJ, Chan TF, Kahng AB, Markov IL, Mulet P. Faster minimization of linear wirelength for global placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 3-13. DOI: 10.1109/43.673628  0.53
1998 Kahng AB, Lach J, Mangione-Smith WH, Mantik S, Markov IL, Potkonjak M, Tucker P, Wang H, Wolfe G. Watermarking techniques for intellectual property protection Proceedings - Design Automation Conference. 776-781.  0.753
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