Year |
Citation |
Score |
2020 |
Charles S, Lyu Y, Mishra P. Real-time Detection and Localization of Distributed DoS Attacks in NoC based SoCs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2020.2972524 |
0.355 |
|
2020 |
Lyu Y, Mishra P. Scalable Concolic Testing of RTL Models Ieee Transactions On Computers. 1-1. DOI: 10.1109/Tc.2020.2997644 |
0.331 |
|
2019 |
Charles S, Ahmed A, Ogras UY, Mishra P. Efficient Cache Reconfiguration Using Machine Learning in NoC-Based Many-Core CMPs Acm Transactions On Design Automation of Electronic Systems. 24: 60. DOI: 10.1145/3350422 |
0.414 |
|
2019 |
Ahmed A, Huang Y, Mishra P. Cache Reconfiguration Using Machine Learning for Vulnerability-aware Energy Optimization Acm Transactions in Embedded Computing Systems. 18: 15. DOI: 10.1145/3309762 |
0.39 |
|
2019 |
Huang Y, Mishra P. Vulnerability-Aware Energy Optimization for Reconfigurable Caches in Multitasking Systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 809-821. DOI: 10.1109/Tcad.2018.2834410 |
0.368 |
|
2019 |
Lyu Y, Qin X, Chen M, Mishra P. Directed Test Generation for Validation of Cache Coherence Protocols Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 163-176. DOI: 10.1109/Tcad.2018.2801239 |
0.576 |
|
2019 |
Farahmandi F, Mishra P. Automated Test Generation for Debugging Multiple Bugs in Arithmetic Circuits Ieee Transactions On Computers. 68: 182-197. DOI: 10.1109/Tc.2018.2868362 |
0.444 |
|
2018 |
Huang Y, Bhunia S, Mishra P. Scalable Test Generation for Trojan Detection Using Side Channel Analysis Ieee Transactions On Information Forensics and Security. 13: 2746-2760. DOI: 10.1109/Tifs.2018.2833059 |
0.343 |
|
2017 |
Gupta U, Patil CA, Bhat G, Mishra P, Ogras UY. DyPO: Dynamic Pareto-Optimal Configuration Selection for Heterogeneous MpSoCs Acm Transactions in Embedded Computing Systems. 16: 123. DOI: 10.1145/3126530 |
0.303 |
|
2017 |
Guo X, Dutta RG, Mishra P, Jin Y. Automatic Code Converter Enhanced PCH Framework for SoC Trust Verification Ieee Transactions On Very Large Scale Integration Systems. 25: 3390-3400. DOI: 10.1109/Tvlsi.2017.2751615 |
0.386 |
|
2017 |
Mishra P, Morad R, Ziv A, Ray S. Post-Silicon Validation in the SoC Era: A Tutorial Introduction Ieee Design & Test of Computers. 34: 68-92. DOI: 10.1109/Mdat.2017.2691348 |
0.325 |
|
2016 |
Rahmani K, Ray S, Mishra P. Postsilicon Trace Signal Selection Using Machine Learning Techniques Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2593902 |
0.353 |
|
2016 |
Rahmani K, Proch S, Mishra P. Efficient Selection of Trace and Scan Signals for Post-Silicon Debug Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 24: 313-323. DOI: 10.1109/Tvlsi.2015.2396083 |
0.35 |
|
2016 |
Chen M, Zhang X, Pu G, Fu X, Mishra P. Efficient Resource Constrained Scheduling Using Parallel Structure-Aware Pruning Techniques Ieee Transactions On Computers. 65: 2059-2073. DOI: 10.1109/Tc.2015.2468230 |
0.537 |
|
2014 |
Chen M, Qin X, Mishra P. Learning-oriented Property Decomposition for Automated Generation of Directed Tests Journal of Electronic Testing. 30: 287-306. DOI: 10.1007/S10836-014-5452-X |
0.556 |
|
2013 |
Basu K, Mishra P. RATS: Restoration-Aware Trace Signal Selection for Post-Silicon Validation Ieee Transactions On Very Large Scale Integration Systems. 21: 605-613. DOI: 10.1109/Tvlsi.2012.2192457 |
0.31 |
|
2013 |
Basu K, Murthy C, Mishra P. Bitmask aware compression of NISC control words Integration. 46: 131-141. DOI: 10.1016/J.Vlsi.2012.02.004 |
0.38 |
|
2012 |
Chen M, Mishra P, Kalita D. Automatic RTL Test Generation from SystemC TLM Specifications Acm Transactions in Embedded Computing Systems. 11: 38. DOI: 10.1145/2220336.2220350 |
0.585 |
|
2012 |
Wang W, Mishra P, Gordon-Ross A. Dynamic Cache Reconfiguration for Soft Real-Time Systems Acm Transactions in Embedded Computing Systems. 11: 28. DOI: 10.1145/2220336.2220340 |
0.386 |
|
2012 |
Qin X, Mishra P. Directed test generation for validation of multicore architectures Acm Transactions On Design Automation of Electronic Systems. 17: 24. DOI: 10.1145/2209291.2209297 |
0.466 |
|
2012 |
Wang W, Mishra P. System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking Systems Ieee Transactions On Very Large Scale Integration Systems. 20: 902-910. DOI: 10.1109/Tvlsi.2011.2116814 |
0.357 |
|
2012 |
Qin X, Wang W, Mishra P. TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking Systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1159-1168. DOI: 10.1109/Tcad.2012.2190824 |
0.371 |
|
2012 |
Wang W, Ranka S, Mishra P. Energy-aware dynamic slack allocation for real-time multitasking systems Sustainable Computing: Informatics and Systems. 2: 128-137. DOI: 10.1016/J.Suscom.2012.04.001 |
0.373 |
|
2012 |
Hajimiri H, Rahmani K, Mishra P. Compression-aware dynamic cache reconfiguration for embedded systems ☆ Sustainable Computing: Informatics and Systems. 2: 71-80. DOI: 10.1016/J.Suscom.2012.01.003 |
0.383 |
|
2011 |
Wang W, Mishra P. Dynamic Reconfiguration of Two-Level Cache Hierarchy in Real-Time Embedded Systems Journal of Low Power Electronics. 7: 17-28. DOI: 10.1166/Jolpe.2011.1113 |
0.415 |
|
2011 |
Qin X, Muthry C, Mishra P. Decoding-Aware Compression of FPGA Bitstreams Ieee Transactions On Very Large Scale Integration Systems. 19: 411-419. DOI: 10.1109/Tvlsi.2009.2035704 |
0.369 |
|
2011 |
Chen M, Mishra P. Property Learning Techniques for Efficient Generation of Directed Tests Ieee Transactions On Computers. 60: 852-864. DOI: 10.1109/Tc.2011.49 |
0.559 |
|
2011 |
Mishra P, Zilic Z, Shukla S. Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models Ieee Design & Test of Computers. 28: 6-9. DOI: 10.1109/Mdt.2011.62 |
0.354 |
|
2011 |
Shukla S, Mishra P, Zilic Z. A Brief History of Multiprocessors and EDA Ieee Design & Test of Computers. 28: 96-96. DOI: 10.1109/Mdt.2011.50 |
0.326 |
|
2011 |
Wang W, Ranka S, Mishra P. Energy-aware dynamic reconfiguration algorithms for real-time multitasking systems Sustainable Computing: Informatics and Systems. 1: 35-45. DOI: 10.1016/J.Suscom.2010.10.006 |
0.357 |
|
2010 |
Basu K, Mishra P. Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods Ieee Transactions On Very Large Scale Integration Systems. 18: 1277-1286. DOI: 10.1109/Tvlsi.2009.2024116 |
0.42 |
|
2010 |
Chen M, Mishra P. Functional Test Generation Using Efficient Property Clustering and Learning Techniques Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 396-404. DOI: 10.1109/Tcad.2010.2041846 |
0.593 |
|
2010 |
Chen M, Mishra P, Kalita D. Efficient test case generation for validation of UML activity diagrams Design Automation For Embedded Systems. 14: 105-130. DOI: 10.1007/S10617-010-9052-4 |
0.576 |
|
2009 |
Koo H, Mishra P. Functional test generation using design and property decomposition techniques Acm Transactions in Embedded Computing Systems. 8: 32. DOI: 10.1145/1550987.1550995 |
0.486 |
|
2009 |
Reshadi M, Mishra P, Dutt N. Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation Transactions On Embedded Computing Systems. 8. DOI: 10.1145/1509288.1509292 |
0.334 |
|
2009 |
Qin X, Mishra P. A Universal Placement Technique of Compressed Instructions for Efficient Parallel Decompression Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1224-1236. DOI: 10.1109/Tcad.2009.2021730 |
0.403 |
|
2009 |
Mishra P. Guest editor introduction: Special issue on nano/bio-inspired applications and architectures International Journal of Parallel Programming. 37: 343-344. DOI: 10.1007/S10766-009-0112-Y |
0.343 |
|
2008 |
Mishra P, Dutt N. Specification-driven directed test generation for validation of pipelined processors Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1367045.1367051 |
0.437 |
|
2008 |
Seong S, Mishra P. Bitmask-Based Code Compression for Embedded Systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 673-685. DOI: 10.1109/Tcad.2008.917563 |
0.374 |
|
2006 |
Reshadi M, Dutt N, Mishra P. A retargetable framework for instruction-set architecture simulation Acm Transactions On Embedded Computing Systems. 5: 431-452. DOI: 10.1145/1151074.1151083 |
0.358 |
|
2005 |
Mishra P, Dutt ND, Krishnamurthy N, Abadir MS. A methodology for validation of microprocessors using symbolic simulation International Journal of Embedded Systems. 1: 14-22. DOI: 10.1504/Ijes.2005.008805 |
0.405 |
|
2005 |
Mishra P. Processor validation: A top-down approach Ieee Potentials. 24: 29-33. DOI: 10.1109/Mp.2005.1405799 |
0.412 |
|
2004 |
Mishra P, Dutt N. Modeling and validation of pipeline specifications Acm Transactions On Embedded Computing Systems. 3: 114-139. DOI: 10.1145/972627.972633 |
0.411 |
|
2004 |
Mishra P, Dutt N, Krishnamurthy N, Ababir MS. A top-down methodology for microprocessor validation Ieee Design & Test of Computers. 21: 122-131. DOI: 10.1109/Mdt.2004.1277905 |
0.384 |
|
2003 |
Mishra P, Dutt N, Tomiyama H. Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications Design Automation For Embedded Systems. 8: 249-265. DOI: 10.1023/B:Daem.0000003965.80744.1C |
0.423 |
|
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