☰

Sudeep Pasricha, Ph.D. - Publications

Affiliations: 
2002-2008 University of California, Irvine, Irvine, CA 
 2008-2016 ECE Colorado State University, Fort Collins, CO 
Area:
Computer Science
Website:
http://www.engr.colostate.edu/~sudeep/
Tree Info Similar researchers PubMed Report error

59 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Kukkala VK, Pasricha S, Bradley T. SEDAN: Security-Aware Design of Time-Critical Automotive Networks Ieee Transactions On Vehicular Technology. 69: 9017-9030. DOI: 10.1109/Tvt.2020.2999533  0.322
2020 Raparti VY, Pasricha S. Approximate NoC and Memory Controller Architectures for GPGPU Accelerators Ieee Transactions On Parallel and Distributed Systems. 31: 25-39. DOI: 10.1109/Tpds.2019.2958344  0.431
2020 Tiku S, Pasricha S, Notaros B, Han Q. A Hidden Markov Model based smartphone heterogeneity resilient portable indoor localization framework Journal of Systems Architecture. 108: 101806. DOI: 10.1016/J.Sysarc.2020.101806  0.348
2019 Fusella E, Nikdast M, O'Connor I, Flich J, Pasricha S. Guest Editors’ Introduction: Emerging Networks-on-Chip Designs, Technologies, and Applications Acm Journal On Emerging Technologies in Computing Systems. 15: 1-2. DOI: 10.1145/3296021  0.363
2019 Khune A, Pasricha S. Mobile Network-Aware Middleware Framework for Cloud Offloading: Using Reinforcement Learning to Make Reward-Based Decisions in Smartphone Applications Ieee Consumer Electronics Magazine. 8: 42-48. DOI: 10.1109/Mce.2018.2867972  0.339
2018 Chittamuru SVR, Thakkar IG, Pasricha S. HYDRA: Heterodyne Crosstalk Mitigation With Double Microring Resonators and Data Encoding for Photonic NoCs Ieee Transactions On Very Large Scale Integration Systems. 26: 168-181. DOI: 10.1109/Tvlsi.2017.2749967  0.323
2018 Chittamuru SVR, Dang D, Pasricha S, Mahapatra R. BiGNoC: Accelerating Big Data Computing with Application-Specific Photonic Network-on-Chip Architectures Ieee Transactions On Parallel and Distributed Systems. 29: 2402-2415. DOI: 10.1109/Tpds.2018.2833876  0.397
2018 Thakkar IG, Pasricha S. DyPhase: A Dynamic Phase Change Memory Architecture With Symmetric Write Latency and Restorable Endurance Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1760-1773. DOI: 10.1109/Tcad.2017.2762921  0.355
2018 Xiang Y, Pasricha S. Mixed-criticality scheduling on heterogeneous multicore systems powered by energy harvesting Integration. 61: 114-124. DOI: 10.1016/J.Vlsi.2017.11.007  0.393
2018 Oxley MA, Jonardi E, Pasricha S, Maciejewski AA, Siegel HJ, Burns PJ, Koenig GA. Rate-based thermal, power, and co-location aware resource management for heterogeneous data centers Journal of Parallel and Distributed Computing. 112: 126-139. DOI: 10.1016/J.Jpdc.2017.04.015  0.375
2017 Biran Y, Dubow J, Pasricha S, Collins G, Borky JM. Considerations for Planning a Multi-Platform Energy Utility System Energy and Power Engineering. 9: 723-749. DOI: 10.4236/Epe.2017.912046  0.385
2017 Chittamuru SVR, Desai S, Pasricha S. SWIFTNoC: A Reconfigurable Silicon-Photonic Network with Multicast-Enabled Channel Sharing for Multicore Architectures Acm Journal On Emerging Technologies in Computing Systems. 13: 58. DOI: 10.1145/3060517  0.398
2017 Mahajan HS, Bradley T, Pasricha S. Application of systems theoretic process analysis to a lane keeping assist system Reliability Engineering & System Safety. 167: 177-183. DOI: 10.1016/J.Ress.2017.05.037  0.347
2016 Bahirat S, Pasricha S. A software framework for rapid application-specific hybrid photonic network-on-chip synthesis Electronics (Switzerland). 5. DOI: 10.3390/Electronics5020021  0.439
2016 Kapadia N, Pasricha S. A Runtime Framework for Robust Application Scheduling With Adaptive Parallelism in the Dark-Silicon Era Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2594238  0.399
2016 Kapadia N, Pasricha S. A System-Level Cosynthesis Framework for Power Delivery and On-Chip Data Networks in Application-Specific 3-D ICs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 24: 3-16. DOI: 10.1109/Tvlsi.2015.2399279  0.419
2016 Raparti VY, Pasricha S. Memory-aware circuit overlay NoCs for latency optimized GPGPU architectures Proceedings - International Symposium On Quality Electronic Design, Isqed. 2016: 63-68. DOI: 10.1109/ISQED.2016.7479177  0.34
2016 Dauwe D, Jonardi E, Friese RD, Pasricha S, Maciejewski AA, Bader DA, Siegel HJ. HPC node performance and energy modeling with the co-location of applications The Journal of Supercomputing. 72: 4771-4809. DOI: 10.1007/S11227-016-1783-Y  0.426
2015 Xiang Y, Pasricha S. Run-Time Management for Multicore Embedded Systems with Energy Harvesting Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 2876-2889. DOI: 10.1109/Tvlsi.2014.2381658  0.351
2015 Oxley MA, Pasricha S, Maciejewski AA, Siegel HJ, Apodaca J, Young D, Briceño L, Smith J, Bahirat S, Khemka B, Ramirez A, Zou Y. Makespan and Energy Robust Stochastic Static Resource Allocation of a Bag-of-Tasks to a Heterogeneous Computing System Ieee Transactions On Parallel and Distributed Systems. 26: 2791-2805. DOI: 10.1109/Tpds.2014.2362921  0.337
2015 Al-Qawasmeh AM, Pasricha S, Maciejewski AA, Siegel HJ. Power and Thermal-Aware Workload Allocation in Heterogeneous Data Centers Ieee Transactions On Computers. 64: 477-491. DOI: 10.1109/Tc.2013.116  0.353
2015 Thakkar I, Pasricha S. 3-D wired: A novel wide i/o dram with energy-efficient 3-D Bank Organization Ieee Design and Test. 32: 71-80. DOI: 10.1109/Mdat.2015.2440411  0.336
2015 Chittamuru SVR, Pasricha S. Crosstalk mitigation for high-radix and low-diameter photonic NoC architectures Ieee Design and Test. 32: 29-39. DOI: 10.1109/Mdat.2015.2414417  0.368
2015 Khemka B, Friese R, Pasricha S, Maciejewski AA, Siegel HJ, Koenig GA, Powers S, Hilton M, Rambharos R, Poole S. Utility maximizing dynamic resource management in an oversubscribed energy-constrained heterogeneous computing system Sustainable Computing: Informatics and Systems. 5: 14-30. DOI: 10.1016/J.Suscom.2014.08.001  0.361
2015 Pasricha S, Donohoo BK, Ohlsen C. A middleware framework for application-aware and user-specific energy optimization in smart mobile devices Pervasive and Mobile Computing. 20: 47-63. DOI: 10.1016/J.Pmcj.2015.01.004  0.35
2015 Kukkala VK, Bradley TH, Pasricha S. Priority-based Multi-level Monitoring of Signal Integrity in a Distributed Powertrain Control System Ifac-Papersonline. 48: 462-469. DOI: 10.1016/J.Ifacol.2015.10.066  0.308
2015 Kapadia N, Pasricha S. VARSHA: Variation and reliability-aware application scheduling with adaptive parallelism in the dark-silicon era Proceedings -Design, Automation and Test in Europe, Date. 2015: 1060-1065.  0.31
2014 Bahirat S, Pasricha S. METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures Acm Transactions in Embedded Computing Systems. 13: 116. DOI: 10.1145/2567940  0.417
2014 Donohoo BK, Ohlsen C, Pasricha S, Xiang Y, Anderson C. Context-Aware Energy Enhancements for Smart Mobile Devices Ieee Transactions On Mobile Computing. 13: 1720-1732. DOI: 10.1109/Tmc.2013.94  0.334
2014 Pasricha S, Xu Y. Guest editors' introduction: Silicon nanophotonics for future multicore architectures Ieee Design and Test. 31: 6-8. DOI: 10.1109/Mdat.2014.2355512  0.431
2014 Xu Y, Pasricha S. Silicon nanophotonics for future multicore architectures: Opportunities and challenges Ieee Design and Test. 31: 9-17. DOI: 10.1109/Mdat.2014.2332153  0.358
2014 Bahirat S, Pasricha S. HELIX: Design and synthesis of hybrid nanophotonic application-specific network-on-chip architectures Proceedings - International Symposium On Quality Electronic Design, Isqed. 91-98. DOI: 10.1109/ISQED.2014.6783311  0.346
2014 Pimpalkhute T, Pasricha S. An application-aware heterogeneous prioritization framework for NoC based chip multiprocessors Proceedings - International Symposium On Quality Electronic Design, Isqed. 76-83. DOI: 10.1109/ISQED.2014.6783309  0.342
2013 Bathen LAD, Ahn Y, Pasricha S, Dutt ND. MultiMaKe Acm Transactions On Embedded Computing Systems. 12: 1-25. DOI: 10.1145/2435227.2435255  0.589
2013 Kapadia N, Pasricha S. VERVE: A framework for variation-aware energy efficient synthesis of NoC-based MPSoCs with voltage islands Proceedings - International Symposium On Quality Electronic Design, Isqed. 603-610. DOI: 10.1109/ISQED.2013.6523673  0.338
2013 Kapadia N, Pasricha S. A co-synthesis methodology for power delivery and data interconnection networks in 3D ICs Proceedings - International Symposium On Quality Electronic Design, Isqed. 73-79. DOI: 10.1109/ISQED.2013.6523593  0.327
2013 Young BD, Apodaca J, Briceño LD, Smith J, Pasricha S, MacIejewski AA, Siegel HJ, Khemka B, Bahirat S, Ramirez A, Zou Y. Deadline and energy constrained dynamic resource allocation in a heterogeneous computing environment Journal of Supercomputing. 63: 326-347. DOI: 10.1007/S11227-012-0740-7  0.327
2012 Zou Y, Xiang Y, Pasricha S. Characterizing Vulnerability of Network Interfaces in Embedded Chip Multiprocessors Ieee Embedded Systems Letters. 4: 41-44. DOI: 10.1109/Les.2012.2193553  0.361
2012 Bahirat S, Pasricha S. A particle swarm optimization approach for synthesizing application-specific hybrid photonic networks-on-chip Proceedings - International Symposium On Quality Electronic Design, Isqed. 78-83. DOI: 10.1109/ISQED.2012.6187477  0.301
2012 Kapadia N, Pasricha S. A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands Integration, the Vlsi Journal. 45: 271-281. DOI: 10.1016/J.Vlsi.2011.11.010  0.395
2011 Kapadia N, Pasricha S. VISION: A framework for voltage island aware synthesis of interconnection networks-on-chip Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 31-36. DOI: 10.1145/1973009.1973017  0.307
2011 Park Y, Pasricha S, Kurdahi FJ, Dutt N. A Multi-Granularity Power Modeling Methodology for Embedded Processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 668-681. DOI: 10.1109/Tvlsi.2009.2039153  0.581
2010 Pasricha S, Kurdahi FJ, Dutt N. Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1376-1380. DOI: 10.1109/Tvlsi.2009.2024118  0.518
2010 Pasricha S, Park Y, Kurdahi FJ, Dutt N. CAPPS: A Framework for Power–Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 209-221. DOI: 10.1109/Tvlsi.2008.2009304  0.619
2010 Zou Y, Pasricha S. NARCO: Neighbor aware turn model-based fault tolerant routing for NoCs Ieee Embedded Systems Letters. 2: 85-89. DOI: 10.1109/Les.2010.2063415  0.353
2009 Pasricha S, Sharma S. FPGA based design of Reed Solomon codes Indian Journal of Science and Technology. 2: 48-52. DOI: 10.17485/ijst/2009/v2i4/29431  0.305
2009 Bahirat S, Pasricha S. Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors Embedded Systems Week 2009 - 7th Ieee/Acm International Conference On Hardware/Software-Co-Design and System Synthesis, Codes+Isss 2009. 129-136. DOI: 10.1145/1629435.1629453  0.309
2009 Pasricha S, Park Y, Dutt N, Kurdahi FJ. System-level PVT variation-aware power exploration of on-chip communication architectures Acm Transactions On Design Automation of Electronic Systems. 14: 1-25. DOI: 10.1145/1497561.1497563  0.552
2009 Madl G, Pasricha S, Dutt N, Abdelwahed S. Cross-abstraction functional verification and performance analysis of chip multiprocessor designs Ieee Transactions On Industrial Informatics. 5: 241-256. DOI: 10.1109/Tii.2009.2026896  0.742
2009 Cho D, Pasricha S, Issenin I, Dutt ND, Ahn M, Paek Y. Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 554-567. DOI: 10.1109/Tcad.2009.2014002  0.699
2008 Pasricha S, Dutt N. Trends in emerging On-chip interconnect technologies Ipsj Transactions On System Lsi Design Methodology. 1: 2-17. DOI: 10.2197/Ipsjtsldm.1.2  0.558
2008 Pasricha S, Dutt N, Ben-Romdhane M. Fast exploration of bus-based communication architectures at the CCATB abstraction Transactions On Embedded Computing Systems. 7. DOI: 10.1145/1331331.1331346  0.589
2008 Pasricha S, Dutt N. ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 789-794. DOI: 10.1109/ASPDAC.2008.4484059  0.494
2007 Pasricha S, Dutt N, Ben-Romdhane M. BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1454-1464. DOI: 10.1109/Tcad.2007.891376  0.579
2007 Pasricha S, Dutt ND. A framework for cosynthesis of memory and communication architectures for MPSoC Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 408-420. DOI: 10.1109/Tcad.2006.884487  0.597
2007 Shin C, Grun P, Romdhane N, Lennard C, Madl G, Pasricha S, Dutt N, Noll M. Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications Design Automation For Embedded Systems. 11: 119-140. DOI: 10.1007/S10617-007-9003-X  0.674
2006 Pasricha S, Dutt ND, Bozorgzadeh E, Ben-Romdhane M. FABSYN: Floorplan-aware bus architecture synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 241-253. DOI: 10.1109/Tvlsl2006.871763  0.598
2006 Pasricha S, Dutt N. COSMECA: Application specific co-synthesis of memory and communication architectures for MPSoC Proceedings -Design, Automation and Test in Europe, Date. 1.  0.553
2004 Pasricha S, Luthra M, Mohapatra S, Dutt N, Venkatasubramanian N. Dynamic backlight adaptation for low-power handheld devices Ieee Design and Test of Computers. 21: 398-405. DOI: 10.1109/Mdt.2004.57  0.5
Show low-probability matches.