Year |
Citation |
Score |
2020 |
Zhang X, Li S, Siferd R, Ren S. High-sensitivity high-speed dynamic comparator with parallel input clocked switches Aeu-International Journal of Electronics and Communications. 122: 153236. DOI: 10.1016/J.Aeue.2020.153236 |
0.452 |
|
2019 |
Abraham I, Ren S, Siferd RE. Logistic Function Based Memristor Model With Circuit Application Ieee Access. 7: 166451-166462. DOI: 10.1109/Access.2019.2951673 |
0.326 |
|
2019 |
Boppana NVVK, Kommareddy J, Ren S. Low-Cost and High-Performance 8 × 8 Booth Multiplier Circuits Systems and Signal Processing. 38: 4357-4368. DOI: 10.1007/S00034-019-01044-X |
0.42 |
|
2018 |
Xue H, Benedik CR, Zhang X, Li S, Ren S. Numerical Solution for Accurate Bondwire Modeling Ieee Transactions On Semiconductor Manufacturing. 31: 258-265. DOI: 10.1109/Tsm.2018.2818168 |
0.329 |
|
2018 |
Xue H, Patel R, Boppana NVVK, Ren S. Low-power-delay-product radix-4 8*8 Booth multiplier in CMOS Electronics Letters. 54: 344-346. DOI: 10.1049/El.2017.3996 |
0.429 |
|
2018 |
Li S, Zhang X, Xue H, Ren S. On-chip self-calibration system for CMOS active inductor band pass filter Aeu-International Journal of Electronics and Communications. 92: 64-68. DOI: 10.1016/J.Aeue.2018.05.007 |
0.377 |
|
2017 |
Xue H, Ren S. Low power-delay-product dynamic CMOS circuit design techniques Electronics Letters. 53: 302-304. DOI: 10.1049/El.2016.4173 |
0.413 |
|
2016 |
Vijaya Krishna Boppana NV, Ren S. A Low-Power and Area-Efficient 64-Bit Digital Comparator Journal of Circuits, Systems and Computers. 25. DOI: 10.1142/S0218126616501486 |
0.409 |
|
2016 |
Li S, Zhang X, Ren S. High Frequency Unity Gain Buffer in 90-nm CMOS Technology Journal of Circuits, Systems and Computers. DOI: 10.1142/S0218126616500717 |
0.439 |
|
2015 |
Suraparaju ER, Arja PVR, Ren S. Simple high-resolution CMOS phase frequency detector Electronics Letters. 51: 1647-1649. DOI: 10.1049/El.2015.2992 |
0.431 |
|
2013 |
Ren S, Lee GY. A Robust Low Power Carbon Nanotube Sensor Interface Circuit in 180 nm CMOS Technology Ieee Sensors Journal. 13: 4786-4795. DOI: 10.1109/Jsen.2013.2274655 |
0.392 |
|
2013 |
Muppala P, Ren S, Lee GY. Design of high-frequency wide-range all digital phase locked loop in 90 nm CMOS Analog Integrated Circuits and Signal Processing. 75: 133-145. DOI: 10.1007/S10470-013-0043-9 |
0.418 |
|
2011 |
Ren S, Emmert J, Siferd R. Design and performance of a robust 180 nm CMOS standalone VCO and the integrated PLL Analog Integrated Circuits and Signal Processing. 68: 285-298. DOI: 10.1007/S10470-011-9644-3 |
0.373 |
|
2008 |
Ren S, Siferd R. 1GS/s pipelined delta sigma modulator ADC using residue averaging technique Analog Integrated Circuits and Signal Processing. 54: 31-44. DOI: 10.1007/S10470-007-9116-Y |
0.378 |
|
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