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Sudhakar M. Reddy - Publications

Affiliations: 
Electrical and Computer Engineering University of Iowa, Iowa City, IA 
Area:
Electronics and Electrical Engineering
Website:
https://www.engineering.uiowa.edu/faculty-staff/sudhakar-m-reddy
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159 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Liu Y, Mukherjee N, Rajski J, Reddy SM, Tyszer J. Deterministic Stellar BIST for Automotive ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 1699-1710. DOI: 10.1109/Tcad.2019.2925353  0.507
2020 Kung Y, Lee K, Reddy SM. Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 1340-1345. DOI: 10.1109/Tcad.2019.2921345  0.567
2020 Martínez LH, Khursheed S, Reddy SM. LFSR generation for high test coverage and low hardware overhead Iet Computers and Digital Techniques. 14: 27-36. DOI: 10.1049/Iet-Cdt.2019.0042  0.498
2019 Wang N, Pomeranz I, Reddy SM, Sinha A, Venkataraman S. Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design Acm Transactions On Design Automation of Electronic Systems. 24: 42. DOI: 10.1145/3325066  0.473
2019 Wu C, Lee K, Reddy SM. An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction Ieee Transactions On Very Large Scale Integration Systems. 27: 2105-2118. DOI: 10.1109/Tvlsi.2019.2919233  0.581
2018 Wu C, Lin S, Lee K, Reddy SM. A Repair-for-Diagnosis Methodology for Logic Circuits Ieee Transactions On Very Large Scale Integration Systems. 26: 2254-2267. DOI: 10.1109/Tvlsi.2018.2856527  0.559
2018 Burchard J, Erb D, Reddy SM, Singh AD, Becker B. On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 2152-2165. DOI: 10.1109/Tcad.2017.2772825  0.605
2017 Acero C, Feltham D, Liu Y, Moghaddam E, Mukherjee N, Patyra M, Rajski J, Reddy SM, Tyszer J, Zawada J. Embedded Deterministic Test Points Ieee Transactions On Very Large Scale Integration Systems. 25: 2949-2961. DOI: 10.1109/Tvlsi.2017.2717844  0.531
2015 Kumar A, Kassab M, Moghaddam E, Mukherjee N, Rajski J, Reddy SM, Tyszer J, Wang C. Isometric Test Data Compression Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 1847-1859. DOI: 10.1109/Tcad.2015.2432133  0.53
2014 Reddy SM, Zhang Z. On achieving minimal size test sets for scan designs Information Technology. 56: 150-156. DOI: 10.1515/Itit-2013-1039  0.519
2012 Pomeranz I, Reddy SM. Resolution of Diagnosis Based on Transition Faults Ieee Transactions On Very Large Scale Integration Systems. 20: 172-176. DOI: 10.1109/Tvlsi.2010.2091975  0.513
2012 Pomeranz I, Reddy SM. Reset and partial-reset-based functional broadside tests Iet Computers and Digital Techniques. 6: 232-239. DOI: 10.1049/Iet-Cdt.2011.0131  0.526
2011 Pomeranz I, Reddy SM. Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan Journal of Low Power Electronics. 7: 245-253. DOI: 10.1166/Jolpe.2011.1132  0.378
2011 Pomeranz I, Reddy SM. Reducing the switching activity of test sequences under transparent-scan Acm Transactions On Design Automation of Electronic Systems. 16: 17. DOI: 10.1145/1929943.1929949  0.491
2011 Pomeranz I, Reddy SM. Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits Ieee Transactions On Very Large Scale Integration Systems. 19: 1907-1911. DOI: 10.1109/Tvlsi.2010.2057459  0.601
2011 Pomeranz I, Reddy SM. Reducing the Storage Requirements of a Test Sequence by Using One or Two Background Vectors Ieee Transactions On Very Large Scale Integration Systems. 19: 1755-1764. DOI: 10.1109/Tvlsi.2010.2055588  0.344
2011 Pomeranz I, Reddy SM. Static Test Data Volume Reduction Using Complementation or Modulo- $M$ Addition Ieee Transactions On Very Large Scale Integration Systems. 19: 1108-1112. DOI: 10.1109/Tvlsi.2010.2044819  0.459
2011 Pomeranz I, Reddy SM. Broadside and Functional Broadside Tests for Partial-Scan Circuits Ieee Transactions On Very Large Scale Integration Systems. 19: 1104-1108. DOI: 10.1109/Tvlsi.2010.2044049  0.594
2011 Pomeranz I, Reddy SM. On Functional Broadside Tests With Functional Propagation Conditions Ieee Transactions On Very Large Scale Integration Systems. 19: 1094-1098. DOI: 10.1109/Tvlsi.2010.2043695  0.546
2011 Pomeranz I, Reddy SM. Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits Ieee Transactions On Very Large Scale Integration Systems. 19: 333-337. DOI: 10.1109/Tvlsi.2009.2031865  0.629
2011 Pomeranz I, Reddy SM. Fixed-State Tests for Delay Faults in Scan Designs Ieee Transactions On Very Large Scale Integration Systems. 19: 142-146. DOI: 10.1109/Tvlsi.2009.2030811  0.607
2011 Polian I, Hayes JP, Reddy SM, Becker B. Modeling and Mitigating Transient Errors in Logic Circuits Ieee Transactions On Dependable and Secure Computing. 8: 537-547. DOI: 10.1109/Tdsc.2010.26  0.484
2011 Pomeranz I, Reddy SM. Sizes of test sets for path delay faults using strong and weak non-robust tests Iet Computers and Digital Techniques. 5: 405-414. DOI: 10.1049/Iet-Cdt.2010.0049  0.605
2011 Pomeranz I, Reddy SM. Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation Iet Computers and Digital Techniques. 5: 415-423. DOI: 10.1049/Iet-Cdt.2010.0014  0.572
2011 Pomeranz I, Reddy SM. Primary input cones based on test sequences in synchronous sequential circuits Iet Computers and Digital Techniques. 5: 16-24. DOI: 10.1049/Iet-Cdt.2009.0087  0.596
2011 Pomeranz I, Reddy SM. Two-dimensional partially functional broadside tests Iet Computers and Digital Techniques. 5: 247-253. DOI: 10.1049/Iet-Cdt.2009.0022  0.506
2010 Pomeranz I, Reddy SM. Test Sequences with Reduced and Increased Switching Activity Journal of Low Power Electronics. 6: 350-358. DOI: 10.1166/Jolpe.2010.1077  0.515
2010 Pomeranz I, Reddy SM. Switching Activity as a Test Compaction Heuristic for Transition Faults Ieee Transactions On Very Large Scale Integration Systems. 18: 1357-1361. DOI: 10.1109/Tvlsi.2009.2022474  0.633
2010 Pomeranz I, Reddy SM. Robust Fault Models Where Undetectable Faults Imply Logic Redundancy Ieee Transactions On Very Large Scale Integration Systems. 18: 1230-1234. DOI: 10.1109/Tvlsi.2009.2020592  0.525
2010 Pomeranz I, Reddy SM. Path Selection for Transition Path Delay Faults Ieee Transactions On Very Large Scale Integration Systems. 18: 401-409. DOI: 10.1109/Tvlsi.2008.2011913  0.511
2010 Pomeranz I, Reddy SM. Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests Ieee Transactions On Very Large Scale Integration Systems. 18: 333-337. DOI: 10.1109/Tvlsi.2008.2010216  0.527
2010 Pomeranz I, Reddy SM. On Undetectable Faults and Fault Diagnosis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1832-1837. DOI: 10.1109/Tcad.2010.2053476  0.515
2010 Pomeranz I, Reddy SM. Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1449-1453. DOI: 10.1109/Tcad.2010.2049462  0.498
2010 Pomeranz I, Reddy SM. On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1135-1140. DOI: 10.1109/Tcad.2010.2046448  0.548
2010 Pomeranz I, Reddy SM. TOV: Sequential Test Generation by Ordering of Test Vectors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 454-465. DOI: 10.1109/Tcad.2010.2041985  0.599
2010 Pomeranz I, Reddy SM. On Test Generation With Test Vector Improvement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 502-506. DOI: 10.1109/Tcad.2010.2041853  0.524
2010 Pomeranz I, Reddy SM. Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis Ieee Transactions On Computers. 59: 150-158. DOI: 10.1109/Tc.2009.112  0.515
2010 Pomeranz I, Reddy SM. Static test compaction for diagnostic test sets of full-scan circuits Iet Computers and Digital Techniques. 4: 365-373. DOI: 10.1049/Iet-Cdt.2009.0110  0.598
2010 Pomeranz I, Reddy SM. Diagnosis of path delay faults based on low-coverage tests Iet Computers and Digital Techniques. 4: 89-103. DOI: 10.1049/Iet-Cdt.2008.0154  0.59
2010 Czutro A, Polian I, Lewis MDT, Engelke P, Reddy SM, Becker B. Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis International Journal of Parallel Programming. 38: 185-202. DOI: 10.1007/S10766-009-0124-7  0.517
2009 Pomeranz I, Reddy SM. Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits Acm Transactions On Design Automation of Electronic Systems. 15: 7. DOI: 10.1145/1640457.1640464  0.633
2009 Pomeranz I, Reddy SM. Random Test Generation With Input Cube Avoidance Ieee Transactions On Very Large Scale Integration Systems. 17: 45-54. DOI: 10.1109/Tvlsi.2008.2001943  0.589
2009 Pomeranz I, Reddy SM. Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits Ieee Transactions On Dependable and Secure Computing. 6: 231-240. DOI: 10.1109/Tdsc.2008.34  0.606
2009 Pomeranz I, Reddy SM. Forward-Looking Reverse Order Fault Simulation for $n$ -Detection Test Sets Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1424-1428. DOI: 10.1109/Tcad.2009.2023193  0.574
2009 Ingelsson U, Al-Hashimi BM, Khursheed S, Reddy SM, Harrod P. Process Variation-Aware Test for Resistive Bridges Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1269-1274. DOI: 10.1109/Tcad.2009.2021728  0.555
2009 Khursheed S, Al-Hashimi BM, Reddy SM, Harrod P. Diagnosis of Multiple-Voltage Design With Bridge Defect Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 406-416. DOI: 10.1109/Tcad.2009.2013540  0.431
2009 Pomeranz I, Reddy SM. Double–Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 426-432. DOI: 10.1109/Tcad.2009.2013281  0.536
2009 Pomeranz I, Reddy SM. Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 121-129. DOI: 10.1109/Tcad.2008.2009152  0.391
2009 Pomeranz I, Reddy SM. Test vector chains for increasing the fault coverage and numbers of detections Iet Computers and Digital Techniques. 3: 222-233. DOI: 10.1049/Iet-Cdt:20080056  0.549
2009 Pomeranz I, Reddy SM. Definition and generation of partially-functional broadside tests Iet Computers and Digital Techniques. 3: 1-13. DOI: 10.1049/Iet-Cdt:20070144  0.493
2009 Pomeranz I, Reddy SM. Test compaction methods for transition faults under transparent-scan Iet Computers and Digital Techniques. 3: 315-328. DOI: 10.1049/Iet-Cdt.2008.0115  0.595
2008 Pomeranz I, Reddy SM. Functional Broadside Tests with Minimum and Maximum Switching Activity Journal of Low Power Electronics. 4: 429-437. DOI: 10.1166/Jolpe.2008.196  0.602
2008 Pomeranz I, Reddy SM. Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion Ieee Transactions On Very Large Scale Integration Systems. 16: 931-936. DOI: 10.1109/Tvlsi.2008.2000453  0.605
2008 Pomeranz I, Reddy SM. Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects Ieee Transactions On Very Large Scale Integration Systems. 16: 98-107. DOI: 10.1109/Tvlsi.2007.909796  0.551
2008 Pomeranz I, Reddy SM. On the Saturation of $n$ -Detection Test Generation by Different Definitions With Increased $n$ Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 946-957. DOI: 10.1109/Tcad.2008.917577  0.529
2008 Lee H, Pomeranz I, Reddy SM. On Complete Functional Broadside Tests for Transition Faults Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 583-587. DOI: 10.1109/Tcad.2008.915531  0.618
2008 Pomeranz I, Reddy SM. Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 398-403. DOI: 10.1109/Tcad.2007.907231  0.53
2008 Pomeranz I, Reddy SM. Primary input vectors to avoid in random test sequences for synchronous sequential circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 193-197. DOI: 10.1109/Tcad.2007.907229  0.49
2008 Pomeranz I, Reddy SM. Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 137-146. DOI: 10.1109/Tcad.2007.907000  0.554
2008 Miyase K, Terashima K, Wen X, Kajihara S, Reddy SM. On Detection of Bridge Defects with Stuck-at Tests Ieice Transactions On Information and Systems. 91: 683-689. DOI: 10.1093/Ietisy/E91-D.3.683  0.62
2008 Pomeranz I, Reddy SM. A same/different fault dictionary: An extended pass/fail fault dictionary with improved diagnostic resolution Proceedings -Design, Automation and Test in Europe, Date. 1474-1479. DOI: 10.1049/Iet-Cdt:20080017  0.55
2007 Pomeranz I, Reddy SM. Forming N-detection test sets without test generation Acm Transactions On Design Automation of Electronic Systems. 12: 18. DOI: 10.1145/1230800.1230810  0.575
2007 Cai Y, Schmitz MT, Al-Hashimi BM, Reddy SM. Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints Acm Transactions On Design Automation of Electronic Systems. 12: 5. DOI: 10.1145/1188275.1188280  0.511
2007 Pomeranz I, Reddy SM, Venkataraman S. $z$ -Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1700-1712. DOI: 10.1109/Tcad.2007.895758  0.596
2007 Remersaro S, Lin X, Reddy SM, Pomeranz I, Rajski J. Scan-based tests with low switching activity Ieee Design and Test of Computers. 24: 268-275. DOI: 10.1109/Mdt.2007.80  0.66
2007 Pomeranz I, Reddy SM. Effectiveness of scan-based delay fault tests in diagnosis of transition faults Iet Computers and Digital Techniques. 1: 537-545. DOI: 10.1049/Iet-Cdt:20070029  0.597
2007 Pomeranz I, Reddy SM. Worst-case and average-case analysis of n-detection test sets and test generation strategies Iet Computers and Digital Techniques. 1: 353-363. DOI: 10.1049/Iet-Cdt:20060120  0.536
2007 Pomeranz I, Reddy SM. On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits Electronic Notes in Theoretical Computer Science. 174: 83-93. DOI: 10.1016/J.Entcs.2006.12.031  0.589
2006 Pomeranz I, Reddy SM. Improved $n$ -Detection Test Sequences Under Transparent Scan Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2492-2501. DOI: 10.1109/Tcad.2006.881334  0.465
2006 Pomeranz I, Reddy SM. Generation of functional broadside tests for transition faults Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2207-2218. DOI: 10.1109/Tcad.2005.860959  0.623
2006 Pomeranz I, Reddy SM. Using Dummy Bridging Faults to Define Reduced Sets of Target Faults Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2219-2227. DOI: 10.1109/Tcad.2005.860951  0.532
2006 Pomeranz I, Reddy SM. Transparent DFT: A design for testability and test generation approach for synchronous sequential circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1170-1175. DOI: 10.1109/Tcad.2005.855947  0.549
2006 Pomeranz I, Reddy SM. Scan-BIST based on transition probabilities for circuits with single and multiple scan chains Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 591-596. DOI: 10.1109/Tcad.2005.854634  0.575
2006 Pomeranz I, Reddy SM. On generating tests that avoid the detection of redundant faults in synchronous sequential circuits with full scan Ieee Transactions On Computers. 55: 491-495. DOI: 10.1109/Tc.2006.57  0.584
2005 Pomeranz I, Reddy SM. Autoscan: a scan design without external scan inputs or outputs Ieee Transactions On Very Large Scale Integration Systems. 13: 1087-1095. DOI: 10.1109/Tvlsi.2005.857157  0.576
2005 Pomeranz I, Reddy SM. Concurrent online testing of identical circuits using nonidentical input vectors Ieee Transactions On Dependable and Secure Computing. 2: 190-200. DOI: 10.1109/Tdsc.2005.30  0.589
2005 Cho Y, Pomeranz I, Reddy SM. On reducing test application time for scan circuits using limited scan operations and transfer sequences Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1594-1605. DOI: 10.1109/Tcad.2005.852285  0.527
2005 Pomeranz I, Reddy SM. On fault equivalence, fault dominance, and incompletely specified test sets Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1271-1274. DOI: 10.1109/Tcad.2005.850822  0.572
2005 Rajski J, Tyszer J, Reddy SM, Wang C. Finite memory test response compactors for embedded test applications Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 622-634. DOI: 10.1109/Tcad.2005.844111  0.428
2005 Pomeranz I, Reddy SM. On masking of redundant faults in synchronous sequential circuits with design-for-testability logic Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 288-294. DOI: 10.1109/Tcad.2004.840551  0.569
2004 Pomeranz I, Reddy SM, Kundu S. On the characterization and efficient computation of hard-to-detect bridging faults Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1640-1649. DOI: 10.1109/Tcad.2004.837725  0.549
2004 Pomeranz I, Reddy SM. Vector-restoration-based static compaction using random initial omission Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1587-1592. DOI: 10.1109/Tcad.2004.836720  0.516
2004 Pomeranz I, Reddy SM. A measure of quality for n-detection test sets Ieee Transactions On Computers. 53: 1497-1503. DOI: 10.1109/Tc.2004.87  0.563
2004 Pomeranz I, Kundu S, Reddy SM. Masking of unknown output values during output response compression by using comparison units Ieee Transactions On Computers. 53: 83-88. DOI: 10.1109/Tc.2004.1255794  0.574
2004 Pomeranz I, Reddy SM. Static test compaction for full-scan circuits based on combinational test sets and nonscan input sequences and a lower bound on the number of tests Ieee Transactions On Computers. 53: 1569-1581. DOI: 10.1109/Tc.2004.118  0.521
2003 Pomeranz I, Reddy SM. Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1663-1670. DOI: 10.1109/Tcad.2003.819424  0.528
2003 Pomeranz I, Reddy SM. Test data compression based on input-output dependence Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1450-1455. DOI: 10.1109/Tcad.2003.818122  0.519
2003 Pomeranz I, Reddy SM. Theorems for identifying undetectable faults in partial-scan circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1092-1097. DOI: 10.1109/Tcad.2003.814957  0.591
2003 Guo R, Reddy SM, Pomeranz I. PROPTEST: a property-based test generator for synchronous sequential circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1080-1091. DOI: 10.1109/Tcad.2003.814953  0.606
2003 Guo R, Reddy SM, Pomeranz I. Reverse-order-restoration-based static test compaction for synchronous sequential circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 293-304. DOI: 10.1109/Tcad.2002.807885  0.698
2002 Pomeranz I, Reddy SM. n-pass n-detection fault simulation and its applications Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 980-986. DOI: 10.1109/Tcad.2002.800453  0.469
2002 Pomeranz I, Reddy SM. Test compaction for at-speed testing of scan circuits based on nonscan test. sequences and removal of transfer sequences Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 706-714. DOI: 10.1109/Tcad.2002.1004314  0.52
2002 Pomeranz I, Reddy SM. A storage-based built-in test pattern generation method for scan circuits based on partitioning and reduction of a precomputed test set Ieee Transactions On Computers. 51: 1282-1293. DOI: 10.1109/Tc.2002.1047753  0.528
2002 Pomeranz I, Reddy SM. Enumeration of test sequences in increasing chronological order to improve the levels of compaction achieved by vector omission Ieee Transactions On Computers. 51: 866-872. DOI: 10.1109/Tc.2002.1017705  0.493
2002 Pomeranz I, Reddy SM. Property-based test generation for scan designs and the effects of the test application scheme and scan selection on the number of detectable faults Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 628-637. DOI: 10.1109/43.998633  0.603
2002 Pomeranz I, Reddy SM. Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of input sequences using single and multiple fault detection times Ieee Transactions On Computers. 51: 409-419. DOI: 10.1109/12.995451  0.486
2002 Shao Y, Reddy SM, Pomeranz I, Kajihara S. On selecting testable paths in scan designs Journal of Electronic Testing. 19: 447-456. DOI: 10.1023/A:1024648227669  0.437
2002 Huang Y, Cheng W, Tsai C, Mukherjee N, Samman O, Zaidan Y, Reddy SM. On Concurrent Test of Core-Based SOC Design Journal of Electronic Testing. 18: 401-414. DOI: 10.1023/A:1016541407006  0.441
2002 Huang Y, Tsai C, Mukherjee N, Samman O, Cheng W, Reddy SM. Synthesis of Scan Chains for Netlist Descriptions at RT-Level Journal of Electronic Testing. 18: 189-201. DOI: 10.1023/A:1014949727553  0.497
2001 Pomeranz I, Reddy SM. On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations Ieee International Test Conference (Tc). 211-220. DOI: 10.1109/Tvlsi.2004.830910  0.598
2001 Pomeranz I, Reddy SM. Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 679-689. DOI: 10.1109/92.953501  0.56
2001 Pomeranz I, Reddy SM. A built-in self-test method for diagnosis of synchronous sequential circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 290-296. DOI: 10.1109/92.924046  0.621
2001 Pomeranz I, Reddy SM. Forward-looking fault simulation for improved static compaction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1262-1265. DOI: 10.1109/43.952743  0.554
2001 Pomeranz I, Reddy SM. On diagnosis and diagnosis test generation for pattern-dependent transition faults Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 791-800. DOI: 10.1109/43.924832  0.528
2001 Pomeranz I, Reddy SM. Vector replacement to improve static-test compaction for synchronous sequential circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 336-342. DOI: 10.1109/43.908476  0.544
2001 Pomeranz I, Reddy SM. Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits Journal of Systems Architecture. 47: 357-373. DOI: 10.1016/S1383-7621(00)00054-0  0.589
2000 Pomeranz I, Reddy SM. On synchronizable circuits and their synchronizing sequences Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 10861092. DOI: 10.1109/43.863649  0.555
2000 Pomeranz I, Reddy SM. Procedures for static compaction of test sequences for synchronous sequential circuits Ieee Transactions On Computers. 49: 596-607. DOI: 10.1109/12.862219  0.548
2000 Pomeranz I, Reddy SM. On the use of fully specified initial states for testing of synchronous sequential circuits Ieee Transactions On Computers. 49: 175-182. DOI: 10.1109/12.833114  0.579
2000 Pomeranz I, Reddy SM. On finding a minimal functional description of a finite-state machine for test generation for adjacent machines Ieee Transactions On Computers. 49: 88-94. DOI: 10.1109/12.822567  0.38
1999 Sparmann U, Muller H, Reddy SM. Universal delay test sets for logic networks Ieee Transactions On Very Large Scale Integration Systems. 7: 156-166. DOI: 10.1109/92.766742  0.575
1999 Pomeranz I, Reddy SM. A comment on "Improving a nonenumerative method to estimate path delay fault coverage" Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 665-666. DOI: 10.1109/43.759083  0.372
1999 Pomeranz I, Reddy SM. A cone-based genetic optimization procedure for test generation and its application to n-detections in combinational circuits Ieee Transactions On Computers. 48: 1145-1152. DOI: 10.1109/12.805164  0.514
1998 Paik D, Reddy SM, Sahni S. Vertex Splitting In Dags And Applications To Partial Scan Designs And Lossy Circuits International Journal of Foundations of Computer Science. 9: 377-398. DOI: 10.1142/S0129054198000301  0.4
1998 Pomeranz I, Reddy SM. On methods to match a test pattern generator to a circuit-under-test Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 432-444. DOI: 10.1109/92.711314  0.609
1998 Dabholkar V, Chakravarty S, Pomeranz I, Reddy S. Techniques for minimizing power dissipation in scan and combinational circuits during test application Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 1325-1333. DOI: 10.1109/43.736572  0.5
1998 Pomeranz I, Reddy SM. Test sequences to achieve high defect coverage for synchronous sequential circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 1017-1029. DOI: 10.1109/43.728921  0.606
1998 Pomeranz I, Reddy SM. Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 269-278. DOI: 10.1109/43.700724  0.544
1998 Pomeranz I, Reddy SM. Location of stuck-at faults and bridging faults based on circuit partitioning Ieee Transactions On Computers. 47: 1124-1135. DOI: 10.1109/12.729795  0.536
1998 Pomeranz I, Reddy SM. Delay fault models for VLSI circuits Integration. 26: 21-40. DOI: 10.1016/S0167-9260(98)00019-4  0.548
1997 Reddy SM, Pomeranz I, Kajihara S. Compact test sets for high defect coverage Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 923-930. DOI: 10.1109/43.644620  0.581
1997 Pomeranz I, Reddy SM. On dictionary-based fault location in digital logic circuits Ieee Transactions On Computers. 46: 48-59. DOI: 10.1109/12.559802  0.562
1996 Pomeranz I, Reddy SM. On the number of tests to detect all path delay faults in combinational logic circuits Ieee Transactions On Computers. 45: 50-62. DOI: 10.1109/12.481486  0.607
1996 Pomeranz I, Reddy SM. On removing redundancies from synchronous sequential circuits with synchronizing sequences Ieee Transactions On Computers. 45: 20-32. DOI: 10.1109/12.481483  0.543
1995 Pomeranz I, Reddy SM, Uppaluri P. NEST: a nonenumerative test generation method for path delay faults in combinational circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 1505-1515. DOI: 10.1109/43.476581  0.591
1995 Kajihara S, Pomeranz I, Reddy SM, Kinoshita K. Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 1496-1504. DOI: 10.1109/43.476580  0.593
1995 Pomeranz I, Reddy SM. On correction of multiple design errors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 255-264. DOI: 10.1109/43.370421  0.364
1995 Pomeranz I, Reddy SM. Incredyble: A New Search Strategy for Design Automation Problems with Applications to Testing Ieee Transactions On Computers. 44: 792-804. DOI: 10.1109/12.391182  0.515
1995 Pomeranz I, Reddy SM. Brief Contributions On Fault Simulation for Synchronous Sequential Circuits Ieee Transactions On Computers. 44: 335-340. DOI: 10.1109/12.364543  0.563
1995 Pramanick AK, Reddy SM. Efficient multiple path propagating tests for delay faults Journal of Electronic Testing. 7: 157-172. DOI: 10.1007/Bf00995311  0.635
1994 Pomeranz I, Reddy SM. On achieving complete fault coverage for sequential machines Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 378-386. DOI: 10.1109/43.265679  0.574
1994 Pomeranz I, Reddy SM. SPADES-ACE: A Simulator for Path Delay Faults in Sequential Circuits with Extensions to Arbitrary Clocking Schemes Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 251-263. DOI: 10.1109/43.259948  0.562
1994 Pomeranz I, Reddy SM. An Efficient Nonenumerative Method to Estimate the Path Delay Fault Coverage in Combinational Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 13: 240-250. DOI: 10.1109/43.259947  0.572
1994 Pomeranz I, Reddy SM. On the role of hardware reset in synchronous sequential circuit test generation Ieee Transactions On Computers. 43: 1100-1105. DOI: 10.1109/12.312119  0.531
1993 Pomeranz I, Reddy SM. 3-Weight Pseudo Random Test Generation Based on a Deterministic Test Set for Combinational and Sequential Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 1050-1058. DOI: 10.1109/43.238041  0.534
1993 Pomeranz I, Reddy LN, Reddy SM. COMPACTEST: a method to generate compact test sets for combinational circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 1040-1049. DOI: 10.1109/43.238040  0.613
1993 Pomeranz I, Reddy SM. Testing of Fault-Tolerant Hardware Through Partial Control of Inputs Ieee Transactions On Computers. 42: 1267-1271. DOI: 10.1109/12.257713  0.535
1993 Pomeranz I, Reddy SM. Classification of Faults in Synchronous Sequential Circuits Ieee Transactions On Computers. 42: 1066-1077. DOI: 10.1109/12.241596  0.579
1992 Pomeranz I, Reddy SM. The Multiple Observation Time Test Strategy Ieee Transactions On Computers. 41: 627-637. DOI: 10.1109/12.142689  0.617
1992 Saluja KK, Liu C-, Reddy SM. Detection of bridging faults in programmable logic arrays Electronics Letters. 28: 1226-1228. DOI: 10.1049/El:19920774  0.519
1992 Ha DS, Reddy SM. On the design of random pattern testable PLA based on weighted random pattern testing Journal of Electronic Testing. 3: 149-157. DOI: 10.1007/Bf00137252  0.508
1991 Kundu S, Reddy SM, Jha NK. Design of robustly testable combinational logic circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 10: 1036-1048. DOI: 10.1109/43.85740  0.552
1989 Li WN, Reddy SM, Sahni SK. On Path Selection in Combinational Logic Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 8: 56-63. DOI: 10.1109/43.21819  0.442
1989 Kim JH, Reddy SM. On the design of fault-tolerant two-dimensional systolic arrays for yield enhancement Ieee Transactions On Computers. 38: 515-525. DOI: 10.1109/12.21144  0.469
1988 Reddy SM, Saluja KK, Karpovsky MG. A Data Compression Technique for Built-In Self-Test Ieee Transactions On Computers. 37: 1151-1156. DOI: 10.1109/12.2271  0.462
1988 Hosseini SH, Kuhl JG, Reddy SM. On Self-Fault Diagnosis of the Distributed Systems Ieee Transactions On Computers. 37: 248-251. DOI: 10.1109/12.2158  0.401
1987 Hosseini SH, Kuhl JG, Reddy SM. Distributed Fault-Tolerance of Tree Structures Ieee Transactions On Computers. 1378-1382. DOI: 10.1109/Tc.1987.5009481  0.368
1987 Reddy SM, Dandapani R. Scan Design Using Standard Flip-Flops Ieee Design & Test of Computers. 4: 52-54. DOI: 10.1109/Mdt.1987.295115  0.314
1986 Lin CJ, Reddy SM. ON DELAY FAULT TESTING IN LOGIC CIRCUITS . 148-151. DOI: 10.1109/Tcad.1987.1270315  0.628
1986 Reddy MK, Reddy SM. Detecting FET Stuck-Open Faults in CMOS Latches And Flip-Flops Ieee Design & Test of Computers. 3: 17-26. DOI: 10.1109/Mdt.1986.295040  0.524
1975 Saluja KK, Reddy SM. Fault Detecting Test Sets for Reed-Muller Canonic Networks Ieee Transactions On Computers. 995-998. DOI: 10.1109/T-C.1975.224108  0.505
1974 Saluja KK, Reddy SM. On Minimally Testable Logic Networks Ieee Transactions On Computers. 552-554. DOI: 10.1109/T-C.1974.223981  0.496
1974 Saluja KK, Reddy SM. Easily Testable Two-Dimensional Cellular Logic Arrays Ieee Transactions On Computers. 1204-1207. DOI: 10.1109/T-C.1974.223831  0.425
1974 Reddy SM, Wilson JR. Easily Testable Cellular Realizations for the (Exactly P)-out-of n and (p or More)-out-of n Logic Functions Ieee Transactions On Computers. 23: 98-100. DOI: 10.1109/T-C.1974.223787  0.402
1973 Pradhan DK, Reddy SM. Fault-Tolerant Asynchronous Networks Ieee Transactions On Computers. 22: 662-669. DOI: 10.1109/Tc.1973.5009132  0.443
1973 Reddy SM. Complete Test Sets for Logic Functions Ieee Transactions On Computers. 1016-1020. DOI: 10.1109/T-C.1973.223638  0.468
1973 Pradhan DK, Reddy SM. Techniques for the Design of Two-Level Fault-Tolerant Logic Networks. Computer-Aided Design. 5: 195. DOI: 10.1016/0010-4485(73)90118-8  0.486
1972 Reddy SM. A Design Procedure for Fault-Locatable Switching Circuits Ieee Transactions On Computers. 1421-1426. DOI: 10.1109/T-C.1972.223517  0.512
1972 Reddy SM. Easily testable realizations for logic functions Ieee Transactions On Computers. 1183-1188. DOI: 10.1109/T-C.1972.223475  0.546
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