Teresa Serrano-Gotarredona - Publications

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71 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2023 Gruel A, Hareb D, Grimaldi A, Martinet J, Perrinet L, Linares-Barranco B, Serrano-Gotarredona T. Stakes of neuromorphic foveation: a promising future for embedded event cameras. Biological Cybernetics. 117: 389-406. PMID 37733033 DOI: 10.1007/s00422-023-00974-9  0.573
2022 Ahmadi-Farsani J, Ricci S, Hashemkhani S, Ielmini D, Linares-Barranco B, Serrano-Gotarredona T. A CMOS-memristor hybrid system for implementing stochastic binary spike timing-dependent plasticity. Philosophical Transactions. Series a, Mathematical, Physical, and Engineering Sciences. 380: 20210018. PMID 35658675 DOI: 10.1098/rsta.2021.0018  0.66
2022 Frasser CF, Linares-Serrano P, de Los Rios ID, Moran A, Skibinsky-Gitlin ES, Font-Rossello J, Canals V, Roca M, Serrano-Gotarredona T, Rossello JL. Fully Parallel Stochastic Computing Hardware Implementation of Convolutional Neural Networks for Edge Computing Applications. Ieee Transactions On Neural Networks and Learning Systems. PMID 35452392 DOI: 10.1109/TNNLS.2022.3166799  0.323
2022 Patiño-Saucedo A, Rostro-González H, Serrano-Gotarredona T, Linares-Barranco B. Liquid State Machine on SpiNNaker for Spatio-Temporal Classification Tasks. Frontiers in Neuroscience. 16: 819063. PMID 35360182 DOI: 10.3389/fnins.2022.819063  0.598
2021 Shamsi J, Avedillo MJ, Linares-Barranco B, Serrano-Gotarredona T. Hardware Implementation of Differential Oscillatory Neural Networks Using VO -Based Oscillators and Memristor-Bridge Circuits. Frontiers in Neuroscience. 15: 674567. PMID 34335158 DOI: 10.3389/fnins.2021.674567  0.657
2020 Ahmadi-Farsani J, Zuniga-Gonzalez V, Serrano-Gotarredona T, Linares-Barranco B, de la Rosa JM. Enhanced Linearity in FD-SOI CMOS Body-Input Analog Circuits – Application to Voltage-Controlled Ring Oscillators and Frequency-Based ΣΔ ADCs Ieee Transactions On Circuits and Systems I: Regular Papers. 67: 3297-3308. DOI: 10.1109/Tcsi.2020.2978926  0.661
2019 Patiño-Saucedo A, Rostro-Gonzalez H, Serrano-Gotarredona T, Linares-Barranco B. Event-driven implementation of deep spiking convolutional neural networks for supervised classification using the SpiNNaker neuromorphic platform. Neural Networks : the Official Journal of the International Neural Network Society. 121: 319-328. PMID 31590013 DOI: 10.1016/J.Neunet.2019.09.008  0.674
2019 Camuñas-Mesa LA, Linares-Barranco B, Serrano-Gotarredona T. Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations. Materials (Basel, Switzerland). 12. PMID 31461877 DOI: 10.3390/Ma12172745  0.667
2019 Nouri M, Hayati M, Serrano-Gotarredona T, Abbott D. A Digital Neuromorphic Realization of the 2-D Wilson Neuron Model Ieee Transactions On Circuits and Systems Ii: Express Briefs. 66: 136-140. DOI: 10.1109/Tcsii.2018.2852598  0.373
2019 Yousefzadeh A, Serrano-Gotarredona T, Linares-Barranco B, Khoei MA, Hosseini S, Holanda P, Leroux S, Moreira O, Tapson J, Dhoedt B, Simoens P. Asynchronous Spiking Neurons, the Natural Key to Exploit Temporal Sparsity Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 9: 668-678. DOI: 10.1109/JETCAS.2019.2951121  0.758
2018 Yousefzadeh A, Stromatias E, Soto M, Serrano-Gotarredona T, Linares-Barranco B. On Practical Issues for Stochastic STDP Hardware With 1-bit Synaptic Weights. Frontiers in Neuroscience. 12: 665. PMID 30374283 DOI: 10.3389/Fnins.2018.00665  0.789
2018 Yousefzadeh A, Orchard G, Serrano-Gotarredona T, Linares-Barranco B. Active Perception With Dynamic Vision Sensors. Minimum Saccades With Optimum Recognition. Ieee Transactions On Biomedical Circuits and Systems. PMID 29994268 DOI: 10.1109/Tbcas.2018.2834428  0.756
2018 Camuñas-Mesa LA, Domínguez-Cordero YL, Linares-Barranco A, Serrano-Gotarredona T, Linares-Barranco B. A Configurable Event-Driven Convolutional Node with Rate Saturation Mechanism for Modular ConvNet Systems Implementation. Frontiers in Neuroscience. 12: 63. PMID 29515349 DOI: 10.3389/Fnins.2018.00063  0.672
2018 Mohan C, Camuñas-Mesa L, Vianello E, Periniolla L, Reita C, de la Rosa J, Serrano-Gotarredona T, Linares-Barranco B. Calibration of offset via bulk for low-power HfO2 based 1T1R memristive crossbar read-out system Microelectronic Engineering. 198: 35-47. DOI: 10.1016/J.Mee.2018.06.011  0.66
2017 Camunas-Mesa LA, Serrano-Gotarredona T, Ieng SH, Benosman R, Linares-Barranco B. Event-Driven Stereo Visual Tracking Algorithm to Solve Object Occlusion. Ieee Transactions On Neural Networks and Learning Systems. PMID 29989974 DOI: 10.1109/Tnnls.2017.2759326  0.629
2017 Sen-Bhattacharya B, Serrano-Gotarredona T, Balassa L, Bhattacharya A, Stokes AB, Rowley A, Sugiarto I, Furber S. A Spiking Neural Network Model of the Lateral Geniculate Nucleus on the SpiNNaker Machine. Frontiers in Neuroscience. 11: 454. PMID 28848380 DOI: 10.3389/Fnins.2017.00454  0.387
2017 Yousefzadeh A, Jablonski M, Iakymchuk T, Linares-Barranco A, Rosado A, Plana LA, Temple S, Serrano-Gotarredona T, Furber SB, Linares-Barranco B. On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems. Ieee Transactions On Biomedical Circuits and Systems. 11: 1133-1147. PMID 28809708 DOI: 10.1109/Tbcas.2017.2717341  0.79
2017 Stromatias E, Soto M, Serrano-Gotarredona T, Linares-Barranco B. An Event-Driven Classifier for Spiking Neural Networks Fed with Synthetic or Dynamic Vision Sensor Data. Frontiers in Neuroscience. 11: 350. PMID 28701911 DOI: 10.3389/Fnins.2017.00350  0.656
2016 Liu Q, Pineda-García G, Stromatias E, Serrano-Gotarredona T, Furber SB. Benchmarking Spike-Based Visual Recognition: A Dataset and Evaluation. Frontiers in Neuroscience. 10: 496. PMID 27853419 DOI: 10.3389/Fnins.2016.00496  0.418
2016 Yousefzadeh A, Plana LA, Temple S, Serrano-Gotarredona T, Furber SB, Linares-Barranco B. Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links Ieee Transactions On Circuits and Systems Ii: Express Briefs. 63: 763-767. DOI: 10.1109/Tcsii.2016.2531092  0.782
2015 Serrano-Gotarredona T, Linares-Barranco B. Poker-DVS and MNIST-DVS. Their History, How They Were Made, and Other Details. Frontiers in Neuroscience. 9: 481. PMID 26733794 DOI: 10.3389/Fnins.2015.00481  0.606
2015 Saïghi S, Mayr CG, Serrano-Gotarredona T, Schmidt H, Lecerf G, Tomas J, Grollier J, Boyn S, Vincent AF, Querlioz D, La Barbera S, Alibart F, Vuillaume D, Bichler O, Gamrat C, et al. Plasticity in memristive devices for spiking neural networks. Frontiers in Neuroscience. 9: 51. PMID 25784849 DOI: 10.3389/Fnins.2015.00051  0.622
2014 Camuñas-Mesa LA, Serrano-Gotarredona T, Ieng SH, Benosman RB, Linares-Barranco B. On the use of orientation filters for 3D reconstruction in event-driven stereo vision. Frontiers in Neuroscience. 8: 48. PMID 24744694 DOI: 10.3389/Fnins.2014.00048  0.623
2014 Zamarreno-Ramos C, Linares-Barranco A, Serrano-Gotarredona T, Linares-Barranco B. Multicasting mesh AER: a scalable assembly approach for reconfigurable neuromorphic structured AER systems. Application to ConvNets. Ieee Transactions On Biomedical Circuits and Systems. 7: 82-102. PMID 23853282 DOI: 10.1109/Tbcas.2012.2195725  0.666
2013 Zamarreno-Ramos C, Kulkarni R, Silva-Martinez J, Serrano-Gotarredona T, Linares-Barranco B. A 1.5 ns OFF/ON switching-time voltage-mode LVDS driver/receiver pair for asynchronous AER bit-serial chip grid links with up to 40 times event-rate dependent power savings. Ieee Transactions On Biomedical Circuits and Systems. 7: 722-31. PMID 24232633 DOI: 10.1109/Tbcas.2012.2232925  0.655
2013 Pérez-Carrasco JA, Zhao B, Serrano C, Acha B, Serrano-Gotarredona T, Chen S, Linares-Barranco B. Mapping from frame-driven to frame-free event-driven vision systems by low-rate rate coding and coincidence processing--application to feedforward ConvNets. Ieee Transactions On Pattern Analysis and Machine Intelligence. 35: 2706-19. PMID 24051730 DOI: 10.1109/Tpami.2013.71  0.652
2013 Serrano-Gotarredona T, Masquelier T, Prodromakis T, Indiveri G, Linares-Barranco B. STDP and STDP variations with memristors for spiking neuromorphic learning systems. Frontiers in Neuroscience. 7: 2. PMID 23423540 DOI: 10.3389/Fnins.2013.00002  0.773
2013 Serrano-Gotarredona T, Prodromakis T, Linares-Barranco B. A Proposal for Hybrid Memristor-CMOS Spiking Neuromorphic Learning Systems Ieee Circuits and Systems Magazine. 13: 74-88. DOI: 10.1109/Mcas.2013.2256271  0.668
2012 Zamarreño-Ramos C, Serrano-Gotarredona T, Linares-Barranco B. A 0.35 μm sub-ns wake-up time ON-OFF switchable LVDS driver-receiver chip I/O pad pair for rate-dependent power saving in AER bit-serial links. Ieee Transactions On Biomedical Circuits and Systems. 6: 486-97. PMID 23853235 DOI: 10.1109/Tbcas.2012.2186136  0.669
2012 Farabet C, Paz R, Pérez-Carrasco J, Zamarreño-Ramos C, Linares-Barranco A, Lecun Y, Culurciello E, Serrano-Gotarredona T, Linares-Barranco B. Comparison between Frame-Constrained Fix-Pixel-Value and Frame-Free Spiking-Dynamic-Pixel ConvNets for Visual Processing. Frontiers in Neuroscience. 6: 32. PMID 22518097 DOI: 10.3389/Fnins.2012.00032  0.687
2012 Serrano-Gotarredona T, Linares-Barranco B. Log-domain implementation of complex dynamics reaction-diffusion neural networks. Ieee Transactions On Neural Networks. 14: 1337-55. PMID 18244581 DOI: 10.1109/Tnn.2003.816374  0.602
2012 Linares-Barranco B, Serrano-Gotarredona T, Serrano-Gotarredona R. Compact low-power calibration mini-DACs for neural arrays with programmable weights. Ieee Transactions On Neural Networks. 14: 1207-16. PMID 18244572 DOI: 10.1109/Tnn.2003.816370  0.676
2012 Camunas-Mesa L, Zamarreno-Ramos C, Linares-Barranco A, Acosta-Jimenez AJ, Serrano-Gotarredona T, Linares-Barranco B. An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors Ieee Journal of Solid-State Circuits. 47: 504-517. DOI: 10.1109/Jssc.2011.2167409  0.655
2011 Indiveri G, Linares-Barranco B, Hamilton TJ, van Schaik A, Etienne-Cummings R, Delbruck T, Liu SC, Dudek P, Häfliger P, Renaud S, Schemmel J, Cauwenberghs G, Arthur J, Hynna K, Folowosele F, ... ... Serrano-Gotarredona T, et al. Neuromorphic silicon neuron circuits. Frontiers in Neuroscience. 5: 73. PMID 21747754 DOI: 10.3389/Fnins.2011.00073  0.672
2011 Zamarreño-Ramos C, Camuñas-Mesa LA, Pérez-Carrasco JA, Masquelier T, Serrano-Gotarredona T, Linares-Barranco B. On spike-timing-dependent-plasticity, memristive devices, and building a self-learning visual cortex. Frontiers in Neuroscience. 5: 26. PMID 21442012 DOI: 10.3389/Fnins.2011.00026  0.783
2011 Zamarreno-Ramos C, Serrano-Gotarredona T, Linares-Barranco B. An Instant-Startup Jitter-Tolerant Manchester-Encoding Serializer/Deserializer Scheme for Event-Driven Bit-Serial LVDS Interchip AER Links Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 2647-2660. DOI: 10.1109/Tcsi.2011.2151070  0.668
2011 Camunas-Mesa L, Acosta-Jimenez A, Zamarreno-Ramos C, Serrano-Gotarredona T, Linares-Barranco B. A 32$\,\times\,$32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 777-790. DOI: 10.1109/Tcsi.2010.2078851  0.657
2011 Lenero-Bardallo JA, Serrano-Gotarredona T, Linares-Barranco B. A 3.6 $\mu$s Latency Asynchronous Frame-Free Event-Driven Dynamic-Vision-Sensor Ieee Journal of Solid-State Circuits. 46: 1443-1455. DOI: 10.1109/Jssc.2011.2118490  0.611
2011 Alibart F, Pleutin S, Bichler O, Gamrat C, Serrano-Gotarredona T, Linares-Barranco B, Vuillaume D. A Memristive Nanoparticle/Organic Hybrid Synapstor for Neuroinspired Computing Advanced Functional Materials. 22: 609-616. DOI: 10.1002/Adfm.201101935  0.554
2010 Perez-Carrasco JA, Acha B, Serrano C, Camunas-Mesa L, Serrano-Gotarredona T, Linares-Barranco B. Fast vision through frameless event-based sensing and convolutional processing: application to texture recognition. Ieee Transactions On Neural Networks / a Publication of the Ieee Neural Networks Council. 21: 609-20. PMID 20181543 DOI: 10.1109/Tnn.2009.2039943  0.672
2010 Leñero-Bardallo JA, Serrano-Gotarredona T, Linares-Barranco B. A Five-Decade Dynamic-Range Ambient-Light-Independent Calibrated Signed-Spatial-Contrast AER Retina With 0.1-ms Latency and Optional Time-to-First-Spike Mode Ieee Transactions On Circuits and Systems I: Regular Papers. 57: 2632-2643. DOI: 10.1109/Tcsi.2010.2046971  0.659
2009 Serrano-Gotarredona R, Oster M, Lichtsteiner P, Linares-Barranco A, Paz-Vicente R, Gomez-Rodriguez F, Camunas-Mesa L, Berner R, Rivas-Perez M, Delbruck T, Liu SC, Douglas R, Hafliger P, Jimenez-Moreno G, Civit Ballcels A, ... Serrano-Gotarredona T, et al. CAVIAR: a 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing- learning-actuating system for high-speed visual object recognition and tracking. Ieee Transactions On Neural Networks / a Publication of the Ieee Neural Networks Council. 20: 1417-38. PMID 19635693 DOI: 10.1109/Tnn.2009.2023653  0.659
2009 Linares-Barranco B, Serrano-Gotarredona T. Memristance can explain Spike-Time-Dependent-Plasticity in Neural Synapses Nature Precedings. 1-1. DOI: 10.1038/Npre.2009.3010.1  0.642
2008 Serrano-Gotarredona R, Serrano-Gotarredona T, Acosta-Jimenez A, Serrano-Gotarredona C, Perez-Carrasco J, Linares-Barranco B, Linares-Barranco A, Jimenez-Moreno G, Civit-Ballcels A. On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing Ieee Transactions On Neural Networks. 19: 1196-1219. DOI: 10.1109/Tnn.2008.2000163  0.686
2008 Lenero-Bardallo J, Serrano-Gotarredona T, Linares-Barranco B. A Calibration Technique for Very Low Current and Compact Tunable Neuromorphic Cells: Application to 5-bit 20-nA DACs Ieee Transactions On Circuits and Systems Ii: Express Briefs. 55: 522-526. DOI: 10.1109/Tcsii.2007.916864  0.663
2008 Vicente-Sánchez G, Velarde-Ramírez J, Serrano-Gotarredona T, Linares-Barranco B. A weak-to-strong inversion mismatch model for analog circuit design Analog Integrated Circuits and Signal Processing. 59: 325-340. DOI: 10.1007/S10470-008-9256-8  0.645
2007 Serrano-Gotarredona R, Camunas-Mesa L, Serrano-Gotarredona T, Lenero-Bardallo JA, Linares-Barranco B. The Stochastic I-Pot: A Circuit Block for Programming Bias Currents Ieee Transactions On Circuits and Systems Ii: Express Briefs. 54: 760-764. DOI: 10.1109/Tcsii.2007.900881  0.65
2007 Costas-Santos J, Serrano-Gotarredona T, Serrano-Gotarredona R, Linares-Barranco B. A Spatial Contrast Retina With On-Chip Calibration for Neuromorphic Spike-Based AER Vision Systems Ieee Transactions On Circuits and Systems I: Regular Papers. 54: 1444-1458. DOI: 10.1109/Tcsi.2007.900179  0.674
2007 Linares-Barranco B, Serrano-Gotarredona T. On an Efficient CAD Implementation of the Distance Term in Pelgrom's Mismatch Model Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1534-1538. DOI: 10.1109/Tcad.2007.893546  0.602
2006 Serrano-Gotarredona T, Linares-Barranco B. A low-power current mode fuzzy-ART cell. Ieee Transactions On Neural Networks. 17: 1666-73. PMID 17131683 DOI: 10.1109/Tnn.2006.883725  0.625
2006 Serrano-Gotarredona R, Serrano-Gotarredona T, Acosta-Jimenez A, Linares-Barranco B. A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems Ieee Transactions On Circuits and Systems I: Regular Papers. 53: 2548-2566. DOI: 10.1109/Tcsi.2006.883843  0.681
2005 Velarde-Ramirez J, Vicente-Sanchez G, Serrano-Gotarredona T, Linares-Barranco B. A mismatch characterization and simulation environment for weak-to-strong inversion CMOS transistors Proceedings of Spie. 5837: 247-258. DOI: 10.1117/12.607710  0.631
2005 Camunas-Mesa L, Acosta-Jimenez A, Serrano-Gotarredona T, Linares-Barranco B. A digital pixel cell for address event representation image convolution processing Proceedings of Spie. 5839: 160-171. DOI: 10.1117/12.607709  0.692
2005 Santos JC, Serrano-Gotarredona T, Linares-Barranco B. A calibration scheme for subthreshold current mode circuits Proceedings of Spie. 5839: 369-380. DOI: 10.1117/12.607708  0.646
2005 Serrano-Gotarredona R, Serrano-Gotarredona T, Barranco BL. Event generators for address event representation transmitters Proceedings of Spie. 5839: 148-159. DOI: 10.1117/12.607707  0.425
2004 Linares-Barranco B, Serrano-Gotarredona T, Ramos-Martos J, Ceballos-Caceres J, Mora J, Linares-Barranco A. A Precise 90<tex>$^circ$</tex>Quadrature OTA-C Oscillator Tunable in the 50–130-MHz Range Ieee Transactions On Circuits and Systems I: Regular Papers. 51: 649-663. DOI: 10.1109/Tcsi.2004.823673  0.628
2004 Linares-Barranco B, Serrano-Gotarredona T, Serrano-Gotarredona R, Serrano-Gotarredona C. Current Mode Techniques for Sub-pico-Ampere Circuit Design Analog Integrated Circuits and Signal Processing. 38: 103-119. DOI: 10.1023/B:Alog.0000011162.52504.39  0.647
2003 Linares-Barranco B, Serrano-Gotarredona T. On the design and characterization of femtoampere current-mode circuits Ieee Journal of Solid-State Circuits. 38: 1353-1363. DOI: 10.1109/Jssc.2003.814415  0.653
2003 Linares-Barranco B, Serrano-Gotarredona T, Ramos-Martos J, Ceballos-Cáceres J, Miguel Mora J, Linares-Barranco A. Precise 90° quadrature current-controlled oscillator tunable between 50–130 MHz Electronics Letters. 39: 823. DOI: 10.1049/El:20030558  0.617
2002 Serrano-Gotarredona T, Linares-Barranco B. Current-mode fully-programmable piece-wise-linear block for neuro-fuzzy applications Electronics Letters. 38: 1165. DOI: 10.1049/El:20020831  0.654
2000 Serrano-Gotarredona T, Andreou AG, Linares-Barranco B. A programmable VLSI filter architecture for application in real-time vision processing systems. International Journal of Neural Systems. 10: 179-90. PMID 11011790 DOI: 10.1142/S0129065700000168  0.627
2000 Serrano-Gotarredona T, Linares-Barranco B. A new five-parameter MOS transistor mismatch model Ieee Electron Device Letters. 21: 37-39. DOI: 10.1109/55.817445  0.61
1999 Serrano-Gotarredona T, Linares-Barranco B, Andreou A. Very wide range tunable CMOS/bipolar current mirrors with voltage clamped input Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 46: 1398-1407. DOI: 10.1109/81.802845  0.655
1999 Serrano-Gotarredona T, Andreou A, Linares-Barranco B. AER image filtering architecture for vision-processing systems Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 46: 1064-1071. DOI: 10.1109/81.788808  0.627
1999 Serrano-Gotarredona T, Linares-Barranco B, Andreou A. A general translinear principle for subthreshold MOS transistors Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 46: 607-616. DOI: 10.1109/81.762926  0.635
1999 Serrano-Gotarredona T, Linares-Barranco B, Andreou A. Bipolar/CMOS current-source flip-flop for application in neuro-fuzzy systems Electronics Letters. 35: 1326. DOI: 10.1049/El:19990918  0.655
1999 Serrano-Gotarredona T, Linares-Barranco B. Analog Integrated Circuits and Signal Processing. 21: 271-296. DOI: 10.1023/A:1008330121404  0.645
1998 Serrano-Gotarredona T, Linares-Barranco B. A high-precision current-mode WTA-MAX circuit with multichip capability Ieee Journal of Solid-State Circuits. 33: 280-286. DOI: 10.1109/4.658631  0.656
1998 Serrano-Gotarredona T, Linares-Barranco B. 7-decade tuning range CMOS OTA-C sinusoidal VCO Electronics Letters. 34: 1621. DOI: 10.1049/El:19981200  0.637
1996 Linares-Barranco B, Serrano-Gotarredona T. A Modified ART 1 Algorithm more Suitable for VLSI Implementations. Neural Networks : the Official Journal of the International Neural Network Society. 9: 1025-1043. PMID 12662581 DOI: 10.1016/0893-6080(95)00145-X  0.627
1996 Serrano-Gotarredona T, Linares-Barranco B. A real-time clustering microchip neural engine Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 4: 195-209. DOI: 10.1109/92.502192  0.666
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