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Li-C Wang - Publications

Affiliations: 
Electrical & Computer Engineering University of California, Santa Barbara, Santa Barbara, CA, United States 
Area:
Computer Engineering
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9 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2017 Chen W, Ray S, Bhadra J, Abadir M, Wang L. Challenges and Trends in Modern SoC Design Verification Ieee Design & Test of Computers. 34: 7-22. DOI: 10.1109/Mdat.2017.2735383  0.311
2017 Abadir M, Bhadra J, Chen W, Wang L. Guest Editors’ Introduction: Emerging Challenges and Solutions in SoC Verification Ieee Design & Test of Computers. 34: 5-6. DOI: 10.1109/Mdat.2017.2729938  0.352
2013 Bastani P, Callegari N, Wang L, Abadir MS. Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained Ieee Design & Test of Computers. 1-1. DOI: 10.1109/Mdt.2009.130  0.661
2013 Ray S, Bhadra J, Abadir MS, Wang LC. Guest Editorial: Test and verification challenges for future microprocessors and SoC designs Journal of Electronic Testing: Theory and Applications (Jetta). 29: 621-623. DOI: 10.1007/S10836-013-5411-Y  0.403
2010 Guzey O, Wang LC, Levitt JR, Foster H. Increasing the efficiency of simulation-based functional verification through unsupervised support vector analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 138-148. DOI: 10.1109/Tcad.2009.2034347  0.669
2010 Bastani P, Callegari N, Wang LC, Abadir MS. Feature-ranking methodology to diagnose design-silicon timing mismatch Ieee Design and Test of Computers. 27: 42-52. DOI: 10.1109/Mdt.2009.95  0.682
2008 Ong C, Hong D, Cheng K, Wang L. A Clock-Less Jitter Spectral Analysis Technique Ieee Transactions On Circuits and Systems. 55: 2263-2272. DOI: 10.1109/Tcsi.2008.918235  0.605
2005 Feng T, Wang L, Cheng K(, Lin C(. Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator Acm Transactions On Design Automation of Electronic Systems. 10: 627-650. DOI: 10.1145/1109118.1109122  0.643
2003 Wang L, Feng T, Cheng K(, Abadir MS, Pandey M. Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems Design Automation For Embedded Systems. 8: 173-188. DOI: 10.1023/B:Daem.0000003961.86651.2B  0.664
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